WO1999024896A1

WO1999024896A1 - Information processor

Info

Publication number: WO1999024896A1
Application number: PCT/JP1998/004928
Authority: WO
Inventors: Takanori Shimura; Takanobu Naruse; Atsushi Nakamura; Mitsuaki Katagiri; Kazuo Tanaka; Kunio Uchiyama
Original assignee: Hitachi, Ltd.; Hitachi Ulsi Systems Co., Ltd.
Priority date: 1997-11-06
Filing date: 1998-10-30
Publication date: 1999-05-20
Also published as: TW436730B; JP3896250B2

Abstract

When a microcomputer and another arithmetic unit are connected to each other, semiconductor devices are so arranged and wired that clocks and address lines are provided at the shortest distances and memories are provided on both sides of the lines. The lines between the chips are short and data can be transferred via a high speed external bus. Moreover, since the inductances of the lines are small, it is also effective in reducing electromagnetic wave noise.

Description

Description Information processing equipment Technical field

The present invention relates to a control device to which a microcomputer (microcomputer) is applied, and more particularly, to a mounting device and a pin arrangement of a control device in a memory device, an image processing device, a portable information device, and a semiconductor control device such as a microcomputer and a logic LSI. . Background art

With the sophistication and speed of microcontrollers and semiconductor memories, external bus terminals on printed circuit boards, which previously operated at tens of MHz, are approaching hundreds of MHz. In the past, external bus connections were slow, so wiring on the printed circuit board was not a major problem in external bus system design, even if it was relatively long. However, for example, in the case of a 100 MHz bus, one bus cycle is 10 nanoseconds, so it is necessary to take into account the wiring delay on the printed circuit board (for example, 1 nanosecond 17 cm).

For this reason, in the chip design of microcomputers, the arrangement of chips on a printed circuit board and the routing of wiring are becoming major issues in high-speed bus design. One of the problems in realizing a high-speed external bus is the simultaneous switching noise of the output buffer. Hereinafter, the simultaneous switching noise will be described. When the output voltage of the output buffer of the semiconductor control device switches from high level to low level (or from low level to high level), the current flowing in the output buffer must be supplied from the external power supply of the chip. In this case, the current supplied from the outside Power / ground level inside the chip rises and falls between the power / ground inside the chip and the power ground Z on the printed circuit board to pass through the pins (bonding wire, lead frame) Generates a noise voltage. This is the switching noise of the output buffer. This causes the output pin or clock signal whose signal has not changed to appear as if it has changed, causing the circuit to malfunction.

To reduce this switching noise,

(1) Reduce the number of output buffers that switch simultaneously.

(2) Slow down the output buffer switching speed.

(3) Increase the number of power supply ground bins.

(4) Reduce the length of the power ground pin.

(5) Mount a large number of decoupling capacitors with low inductance on the printed circuit board.

(6) Reduce the load capacitance and wiring capacitance of the output pins.

Countermeasures such as are conceivable.

In the past, since the external bus clock was as slow as about 30 MHz, the switching speed of the output buffer of a semiconductor control device such as a microcomputer was slowed down to, for example, about 15 nanoseconds, and the number of power / duland pins was output. The problem was solved by preparing about one pin for every eight pins and mounting a large number of decoupling capacitors with low inductance on the printed circuit board.

In conventional microcontrollers, the pin arrangement of microcontrollers and peripheral chips was determined without considering the externally mounted semiconductor memory and peripheral chips.Therefore, when designing a printed circuit board, it was difficult to route the signal lines. Was. In some cases, the signal lines were too long, making it impossible to transfer data over a high-speed external bus.

An object of the present invention is to improve the pin arrangement of a logic LSI such as a microcomputer and a peripheral chip. To determine the layout of LSIs and memories on a printed circuit board, to facilitate wiring on the printed circuit board, and to provide a microcomputer control system that can transfer information over a high-speed external bus. is there.

In recent multimedia systems, the data transfer capacity required for an external bus to handle a large amount of image data is, for example, a high-speed bus of 100 MHz, a bus width of 64 bits, that is, 800 MHz / byte. High-speed transfer such as is required.

Therefore, for (1), the number of output buffers that switch simultaneously cannot be reduced, and conversely, the conventional 32 bit bus has increased to 64 buses.

Regarding (2), the output buffer switching speed cannot be slowed down.In a 100 MHz high-speed bus, one bus cycle is 10 ns, so the output buffer switching speed is 5 ns to 6 ns. And fast.

For (3), the number of power / ground pins is improved from one for eight output pins to one for four.

Regarding (4), shorten the length of the power Z ground pin on the printed circuit board.

Regarding (5), many ぃ decoupling capacitors with low inductance are mounted on the printed circuit board as before.

With regard to (6), measures are taken to reduce the load capacitance and wiring capacitance of the output pins on the printed board, taking into account the mounting of the printed board.

However, in the past, with regard to (4) above, measures were taken to reduce the length of the power supply ground pins on the printed circuit board, but the power supply / ground bins inside the package were shortened, and No measures were taken to lower the conductance. A second object of the present invention is to reduce the wiring length of the power supply / the ground in the package of the semiconductor control device and reduce the inductance so that the output buffer of the high-speed external bus whose bus clock is 100 MHz or more can be obtained. It is an object of the present invention to provide a semiconductor control device such as a microcomputer and a logic LSI that can reduce switching noise. Disclosure of the invention

(Solution)

In order to solve the above problems, the present invention provides a microcomputer control device including a microcomputer, a peripheral control semiconductor device, and a plurality of semiconductor memories, wherein a plurality of semiconductor memories are arranged between the microcomputer and the peripheral semiconductor device, The pin arrangement of the microcomputer is such that a clock signal is output from the center of the side where the microcomputer and the semiconductor memory are closest to each other, an address signal is output from the left and right sides of the clock, and a control signal is output from the outside. It is proposed that the data bus be output from the side of the next closest memory device and semiconductor memory, and the wiring length of the clock, address bus, and control signal between the microcomputer and the memory be shortened.

In addition, the semiconductor memory arranged between the microcomputer and the peripheral control semiconductor device has the address bus inside (in the direction close to the line connecting the center of the microcomputer and the center of the peripheral semiconductor device) and the data bus outside and the horizontal. It is preferable to shorten the wiring length of the address bus.

In addition, the pin arrangement of the microcomputer and the peripheral control semiconductor device should be pin-symmetrical, and the peripheral control semiconductor device should be mounted on the back of the microcomputer to reduce the length of signal lines between the microcomputer and the peripheral control semiconductor device. It is also desirable to Furthermore, the microcomputer, peripheral control semiconductor device, and semiconductor memory can be integrated into one chip. As described above, according to the present invention, in a control system to which a microcomputer is applied, by realizing pin arrangement of signal lines necessary for controlling an external bus, wiring between the microcomputer and a memory and between the microcomputer and a peripheral chip are realized. This minimizes the number of wires and enables high-speed external bus data transfer.

In one embodiment of the present invention, when a first semiconductor device having an arithmetic function and second and third semiconductor devices having a storage function are provided, and an axis passing through the first semiconductor device is assumed to be a Y axis, The second and third semiconductor devices are arranged so as to be line-symmetric with respect to the Y axis, and output a clock signal to a side of the first semiconductor device closer to the second and third semiconductor devices. A clock signal terminal is provided, and a clock signal is supplied to the second and third semiconductor devices from the clock signal terminal.

Further, when assuming an X-axis orthogonal to the Y-axis, the second and third semiconductor devices are preferably arranged along the X-axis direction. A fourth semiconductor device having an arithmetic function provided on the Y-axis; second and third semiconductor devices are arranged between the fourth semiconductor device and the first semiconductor device; It is preferable that the clock signal supplied from the semiconductor device is input to the clock input terminal on the side near the second and third semiconductor devices of the fourth semiconductor device. Further, it is desirable that the wiring for transmitting the clock signal passes between the second and third semiconductor devices. With such an arrangement, a quick signal is supplied to the device through the shortest distance, and high-speed and stable operation is possible.

Regarding the address signal, the first semiconductor device may have address signal terminals on the left and right sides of the clock terminal, and the address signal terminal may supply the address signal to the second and third semiconductor devices.

Regarding the data signal, the side where the clock signal terminal of the first semiconductor device is located is defined as the first side, and the sides on both sides of the first side are defined as the second and third sides. The ratio of the number of data signal input / output terminals to the number of terminals arranged on each side is larger in the second or third side than in the first side. It is desirable to do. That is, the data signal is connected to the second and third sides as much as possible.

The second and third semiconductor devices have long sides in a direction parallel to the X axis, and a terminal to which an address signal is input on the long side is closer to the Y axis than a data signal input / output terminal. The wiring length can be reduced.

Regarding the fourth semiconductor device, it is desirable that the fourth semiconductor device has an address signal input terminal on the same side as the side where the clock signal input terminal is located, and the address signal from the first semiconductor device is input to the address signal input terminal. Further, when a side having a clock signal input terminal of the fourth semiconductor device is defined as a first side, and sides on both sides of the first side are defined as second and third sides, a terminal arranged on each side is provided. It is desirable that the ratio of the number of the data signal input / output terminals to the number of the first side is set to be larger in the second or third side than in the first side. The purpose is the same as that of the first semiconductor device.

As described above, the configurations of the first semiconductor device (for example, a microcomputer) and the fourth semiconductor device (for example, an arithmetic device that operates in cooperation with a microcomputer) suitable for the system proposed by the present invention are, for example, rectangular. In this case, terminals for clock and address signals are arranged on one side, and input / output terminals for data signals are provided on the two sides on both sides. If the number of input / output terminals for data signals is large, some of them can be placed on the side where the terminals for clock and address signals are located.

The first and fourth semiconductor devices having such terminal arrangement are arranged such that the sides of the terminals related to clock and address signals face each other, and the clock, address, and data are connected, thereby achieving high-speed operation. The wiring length of the clock address signal, which has a large effect on Contributes to improved stem performance. On the side opposite to the side with the terminal for the clip and address signals, signal terminals that do not significantly affect high-speed performance, such as low-speed memory and external interface circuits, can be connected.

If it is desired to increase the capacity of a high-speed storage device, fifth and sixth semiconductor devices having the same configuration as the second and third semiconductor devices are further provided, and the fifth and sixth semiconductor devices are replaced by Y. The semiconductor devices are arranged so as to be line-symmetric with respect to the axis, and the fifth and sixth semiconductor devices have long sides in a direction parallel to the X-axis. Terminals can be arranged closer to the Y-axis than the data signal input / output terminals.

For example, the fifth and sixth semiconductor devices are disposed on the same substrate surface as the substrate surface on which the second and third semiconductor devices are disposed, and are disposed between the first and fourth semiconductor devices. Have been. That is, these memory devices are located between the first and fourth semiconductor devices and arranged in a matrix.

In another example, the fifth and sixth semiconductor devices are arranged on a substrate surface opposite to the substrate surface on which the second and third semiconductor devices are arranged, and the second and third semiconductor devices are arranged with respect to the substrate. It is arranged so as to be plane-symmetric with the third semiconductor device. In this example, the wiring length can be shorter than in the previous example, but the device thickness becomes thicker. In a typical example, the second, third, fifth, and sixth semiconductor devices are semiconductor memories having a 16-bit data bus, for example, synchronous DRAM.

Also, at least one of an emulator, a clock oscillator, an input / output port, a serial interface, and an interrupt circuit is provided as a peripheral module, and the first to the first semiconductor devices are provided. Terminals located on sides other than side 3 can be connected to peripheral modules. With these devices Does not require such a high speed. In addition, a semiconductor memory of a type different from the second and third semiconductor devices is provided, and terminals arranged on sides other than the first to third sides of the first semiconductor device and the semiconductor memories are provided. You can also connect.

As the fourth semiconductor device, a semiconductor device for processing moving image data and other coprocessors can be considered.

According to another aspect of the present invention, there is provided an information processing apparatus including a microcomputer and two semiconductor memories arranged on a substrate, wherein the two semiconductor memories are arranged in a direction parallel to a first side of the microcomputer. The memories are arranged side by side, and the microcomputer and the semiconductor memory are connected by a clock bus, an address bus, and a data bus, and the clock bus is connected to a terminal arranged on the first side of the microcomputer.

The proportion of the terminals connected to the data bus among the terminals arranged on the second side and the third side sandwiching the first side of the microcomputer is the data bus among the terminals arranged on the first side. It is desirable that the ratio be larger than the ratio of terminals connected to the terminal. It is also desirable that an address bus is connected to a terminal arranged on the first side of the microcomputer.

At this time, the long sides of the two semiconductor memories are parallel to the first side of the microcomputer, the address bus and the data bus are connected to the terminals arranged on the long sides, and the terminals near the opposite sides of the two semiconductor memories are connected. It is desirable that an address bus is connected to the server.

It is also desirable that a clock bus be connected to a terminal on the long side of the two semiconductor memories between the terminal connected to the address bus and the terminal connected to the data bus.

In still another aspect, the first data processing device having a rectangular parallelepiped shape,

Two data processing devices, multiple storage devices, and a board on which they are mounted. Assuming an X-axis and a Y-axis orthogonal to each other on the substrate surface, the first and second data processing devices are arranged on the Y-axis and a plurality of A storage device is arranged, a plurality of storage devices are arranged line-symmetrically with respect to the X axis, and first and second data processing devices are arranged with the plurality of storage devices interposed therebetween.

Typically, a wiring for supplying a clock signal is connected between opposing surfaces of the first data processing device and the second data processing device, and a plurality of storage devices are separately arranged on both sides of the wiring. ing.

Further, a terminal on a surface on the right side of the Y axis of the first or second data processing device and a storage device on the right side of the Y axis among the storage devices are preferably connected by a data bus, and The terminal on the left-hand side of the Y-axis of the second data processor and the storage device on the left-hand side of the Y-axis among the storage devices are connected by a data bus.

In another aspect, there is provided a first data processing device having a rectangular parallelepiped shape, a second data processing device, a plurality of storage devices, and an information processing device having a board on which the first and second data processing apparatuses are mounted. The first and second data processing devices are arranged, and the input or output terminal of the first data processing device is arranged at a position facing the output or input terminal of the second data processing device. And Further, the plurality of storage devices are disposed with the substrate surface interposed therebetween, and the clock input terminal, the address input terminal, and the data input terminal of the storage device are disposed at positions facing each other, thereby shortening the wiring length. It is especially effective.

As described above, the present invention can provide a system in which a plurality of chips or modules are arranged on a substrate and are connected to each other to operate at high speed.

In order to solve the second problem, a package with pins (solder balls) arranged in a two-dimensional array on the back of the package of the semiconductor control device has been developed. In the mounted semiconductor control device, power and ground are placed on the inner pins to minimize the distance from the bonding PAD of the chip in the package to the pins on the back of the package, and the power supply and ground in the package are connected. By reducing the inductance of the ground, the switching noise of the output buffer of the semiconductor control device is reduced.

Furthermore, in the semiconductor control device mounted on a package having pins (solder balls) arranged on a two-dimensional array on the back surface of the package of the semiconductor control device, the ground is arranged on the innermost side and two rows from the inner side. A power supply pin is placed in the eye to minimize the distance from the bonding pad of the chip in the package to the pin on the back side of the package. Output buffer switching ぇ Noise is reduced.

In a semiconductor control device in which the power supply voltage for 10 (input / output circuit) and the power supply voltage for internal logic operate at different voltages, the power supply and ground pins for 10 and the power supply and ground pins for internal logic In most cases, the output switching noise has been reduced.

As described above, according to the present invention, in a semiconductor control device such as a microcomputer or a logic LSI, by realizing a pin arrangement for reducing switching noise of an output buffer of the semiconductor control device, a high-speed output buffer using an external bus is realized. Switching noise can be reduced, and high-speed data input / output can be achieved. In a package with pins arranged on an array, power / ground bins are placed on pins inside the package in this way. Pins on the outside of the package can be placed on the signal line, and if the mounting rule allows one signal line to pass between pins when the signal line is drawn out of the package, it can be placed on the printed circuit board. Since the signal lines can be drawn out without using through holes, the resistance due to through holes can be eliminated when implementing a high-speed bus. The adjustment and routing of the impedance can be simplified, and the implementation of a high-speed external bus can be facilitated.

A typical example of the present invention is a semiconductor device having a semiconductor chip, a package containing the semiconductor chip, and a plurality of terminals arranged on the surface of the package. A plurality of terminals of a first type for supplying power or ground to the chip, and a plurality of terminals of a second type for inputting signals to or outputting signals from the semiconductor chip;

The set A of the shortest distance between the outer edge of the semiconductor chip and the outer edge of each of the first type terminals is A1 to AN (where N is the number of the first type terminals),

When the set B of the shortest distance between the outer edge of the semiconductor chip and the outer edge of each of the second type terminals is B1 to BM (where M is the number of the second type terminals), the smallest one of the set B is , Which is equal to or greater than the largest one of the set A. In this way, the pins are arranged so that the wiring lengths of the power supply and the ground potential are preferentially reduced.

At this time, the terminals are arranged in a matrix on the plane having the largest area among the planes forming the outer shape of the package, and the plane having the largest area is a rectangle, usually a square. The set AX of the shortest distance between the outer edge of this rectangular planar surface and the outer edge of each of the first type terminals is AX1 to AXN (where N is the number of the first type terminals). If the shortest distance BX between the outer edge of the plane and the outer edge of each of the above-mentioned second type terminals is BX1 to BXM (where M is the number of the second type terminals), the largest of the set BX Is greater than or equal to the smallest of the sets AX. In short, the signal pins are located closer to the outer edge of the terminal placement surface, and the power pins are located farther away.

Alternatively, a semiconductor chip, a package containing the semiconductor chip, A semiconductor device having a plurality of terminals arranged in a matrix at equal intervals on the surface of a package, wherein the outermost terminal among the terminals arranged in the matrix is a first group, and a terminal in the first group is When the terminal located at the shortest distance is defined as the second group, and the terminal located at the shortest distance from the second group and not belonging to the first group is defined as the third group, the third group is obtained. The ratio of terminals other than the signal input / output terminals in the first group is larger than that in the first group.

More desirably, the ratio of terminals other than the signal input / output terminals in the third group is larger than that in the second group. Further, when a terminal which is the shortest distance from the terminal of the third group and which does not belong to the second group is a fourth group, the ratio of terminals other than the signal input / output terminals in the fourth group is as follows. It is larger than that in the first group.

In other words, as will be described in detail later with reference to Fig. 8, etc., the power supply or ground pins are preferentially arranged for the inner two circuits that are arranged in a matrix over four circuits (either circular or rectangular). Then, the signal pins are arranged for the outer two rounds. In some cases, it is necessary to prepare a large number of signal pins, but in that case, signal pins may be appropriately set in the inner two turns.

Here, as terminals other than signal input / output terminals, first and second terminals for driving logic circuits formed in the semiconductor chip (for example, various gates and latches formed by MOS) are used. Needless to say, a terminal for supplying a potential is included. When a plurality of types of power supplies are provided, the power supply may further include a terminal for supplying third and fourth potentials for driving a logic circuit formed in the semiconductor chip. For example, separate power supplies may be used for the internal logic circuit and the peripheral input / output circuit unit.

The arrangement of the power supply pins depends on the specific logic gate formed in the semiconductor chip. It is preferable that a pair of terminals for supplying the first and second potentials for driving the gate is divided into terminals belonging to the third and fourth groups. Also, terminals for supplying second and third potentials for driving a specific logic gate formed in the semiconductor chip are arranged separately in terminals belonging to the third and fourth groups. It is also desirable that In particular, it is preferable that the pair of the power supply and the ground potential be terminals arranged adjacently in the third and fourth groups.

The package is placed on the printed circuit board, wiring is drawn out from the terminals belonging to the first and second groups along the surface of the substrate, and the circuit board is drawn from the terminals belonging to the third and fourth groups. It is preferable that the wiring be drawn out through the through hole that penetrates, because the influence of noise on the power supply can be reduced.

The input / output terminal may transmit an input signal to be processed by a logic circuit formed in the semiconductor chip or an output signal processed by a logic circuit formed in the semiconductor chip.

According to another aspect of the present invention, there is provided a semiconductor chip, a package including the semiconductor chip, and a semiconductor chip. A semiconductor device comprising: a plurality of conductor pins arranged on a surface of a package; and a lead frame for electrically connecting a pad of the semiconductor chip and the conductor pins, wherein the plurality of pins are formed on the semiconductor chip. A plurality of pins of the first kind for supplying at least two potentials for driving the active element, and a signal modulated by the active element of the semiconductor chip or modulated by the active element of the semiconductor chip Including a plurality of pins of the second type that output signals, the longest wiring between the first type of pins and the pad is the shortest of the wiring between the second type of pins and the pad It is characterized by not exceeding things. Regarding the pin arrangement, a plurality of pins of the first type are arranged so as to surround an outer edge of the semiconductor chip, and a plurality of pins of the second type are It can be arranged to surround a plurality of pins of one type.

The package is placed on a printed circuit board, with most of the pins of the second type leading out of the wiring along the board surface and most of the pins of the first type leaving the board out of the pins. It is desirable that the wiring be drawn through a through hole that penetrates. Ideally, all pins of the first type should use through-holes to reduce wiring length, but in most cases (about 80% use of through-holes is also effective).

(Effect)

As described above, according to the present invention, in a control system to which a microcomputer is applied, a pin arrangement of the microcomputer suitable for an external bus is provided to connect a logic LSI such as a microcomputer with an external memory or a peripheral chip. Necessary signal lines can be minimized, and data can be transferred via a high-speed external bus. This has a great effect when implementing amusement equipment and information equipment that require a high-speed bus.

Further, according to the present invention, the wiring between the chips is shortened, and the inductance of the wiring is reduced, so that it is effective in reducing electromagnetic interference noise.

Further, according to the present invention, a pin arrangement of a semiconductor control device such as a microcomputer logic LSI which is resistant to switching noise of an output buffer is provided, and noise due to a high-speed external bus is reduced. The effect is great when realizing a mobile device, an image processing device, and an information device. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a plan view showing a configuration of a microcomputer control device according to a first embodiment of the present invention. FIG. 2 is a plan view showing a configuration of a microcomputer control device according to a second embodiment of the present invention. FIG. 3 is a plan view showing a configuration of a microcomputer control device according to a third embodiment of the present invention. FIG. 4 shows a configuration of a microcomputer control device according to a fourth embodiment of the present invention. FIG. FIG. 5 is a plan view showing the connection between the microcomputer and the memory according to the present invention. FIG. 6 is a table showing explanations of signal names of a memory. FIG. 7 is a cross-sectional view of the mounting of the microcomputer and the peripheral chip of the present invention. FIG. 8 is a pin layout diagram of the BGA package of the present invention. FIG. 9 is a table showing the description of the pins of the BGA and QFP packages of the present invention. FIG. 10 is a table showing the pin descriptions of the BGA and QFP packages of the present invention. FIG. 11 is a plan view of the left half of the pin arrangement diagram of the QFP package according to the embodiment of the present invention. FIG. 12 is a plan view of the right half of the pin layout of the QFP package according to the embodiment of the present invention. FIG. 13 is a plan view showing a configuration of a pin arrangement of a package of the semiconductor control device of the present invention. FIG. 14 is a sectional view of the package A of FIG. 1 of the present invention. FIG. 15 is a schematic diagram showing an example of mounting inside a package of the semiconductor control device of the present invention. FIG. 16 is a plan view of another embodiment of the configuration of the pin arrangement of the package of the semiconductor control device of the present invention. FIG. 17 is a sectional view of mounting the package of the present invention on a printed circuit board. FIG. 18 is an enlarged plan view of a portion B in FIG. 1 of the present invention. FIG. 19 is a plan view showing the configuration of a foot pattern for mounting the package of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 shows a first embodiment of the present invention. The semiconductor memories 20, 21, 22, and 23 are placed between the microcomputer 10 and the peripheral chip 30. In the example of FIG. 1, when the axis extending in the direction in which the microcomputer 10 and the peripheral chip 30 are arranged and passing through the center of the microcomputer 10 and the peripheral chip is the Y axis, the Y axis Semiconductor memories 20 to 23 are arranged on both sides in line symmetry with respect to the Y axis.

Each semiconductor memory is placed horizontally with the address pins (ADR-A, ADR-B) inside and the data pins outside (D [0-15]). That is, each semiconductor memory is When the axis orthogonal to the Y axis is set to the X axis direction, the long sides are arranged in the X axis direction so that the address pins of each semiconductor memory are arranged closer to the Υ axis than the data pins. It has become so.

Here, the semiconductor memory is described as an SDRAM (synchronous dynamic RAM) capable of realizing a synchronous high-speed data transfer, but may be another type of memory, for example, a synchronous SRAM, a normal SRAM, or a DRAM.

The microcomputer 10 and the peripheral chip 30 are a 64-bit data bus. The semiconductor memories 20, 21, 22, and 23 have a 16-bit data bus, and a 64-bit bus is realized by a 4-chip semiconductor memory.

Microcontroller 10 to clock 10 4, address bus 10 5, 10 6, control signal 10 7, 10 8, 10 9, data bus 10 0, 10 1, 10 2, 10 3 To control the semiconductor memories 20, 21, 22, 23 and the peripheral chip 30.

The clock 104 is output from the center of the pin located on the lower side of the microcomputer 10 (the side closer to the memory), and the operation clock of the semiconductor memories 20, 21, 22, 23, and the peripheral chip 30 Used as That is, in the example of FIG. 1, the clock is routed from the microcomputer 10 to the peripheral chip along the Y-axis, branched right and left on the way, and supplied to the memories 20 to 23.

The address buses 105 and 106 are arranged and output on the left and right around the clock output of the microcomputer 10. 105 is the lower bit (for example, AO to A6) of the address of the semiconductor memory, and 106 is the upper bit (for example, A7 to A17) of the address of the semiconductor memory. Input to address 23 and peripheral chip 30. In FIG. 1, only the address 105 is input to the peripheral chip 30. However, if the address space mapped in the peripheral chip 30 is large, the address 106 is also input. It may be input to the peripheral chip 30.

Control signals 107 (write strobe to right memory), 108 (write strobe to left memory), 109 (chip select, read / write switching signal, RAS strobe) And the CAS strobe) are output from the outside of the address of the microcomputer 10, and the control signal 109 common to the left and right semiconductor memories is output from the semiconductor memories 20, 21, 22, 22. 3 and output to peripheral chip 30. The control signal 107 is output to the right semiconductor memories 21 and 23 and the peripheral chip 30.The control signal 108 is output to the left semiconductor memories 20 and 22 and the peripheral chip 30. Is done.

Data buses 100, 101, 102, and 103 are overnight data buses in 16-bit units.For example, 100 is DO to D15, 101 is D16 to D31, 1 02 is from D32 to D47, and 102 is from D48 to D63. Each force is output from the left and right sides of the microcomputer 10 and connected to the semiconductor memories 20, 21, 22, 23 and the peripheral chip 30.

In this way, when connecting the microcomputer 10 to the semiconductor memories 20, 21, 22, 23, and the peripheral chip 30, the load capacity of the output is heavy (when connected to four memories and one peripheral chip, The load capacitance is 25 pF to 35 pF because each chip is 5 pF to 7 pF.) The clock, address, and control signal pins are collected on the lower side of the microcomputer 10 and the semiconductor memory 20, 21, By arranging these signals horizontally so that the address buses 23 and 23 are located inside (in the direction near the line (Y axis) connecting the center of the microcomputer 10 and the center of the peripheral chip 30), these signals are The wires are routed so as to pass the shortest distance between the semiconductors 20, 21, 22, 23 and the peripheral chip 30.

In particular, the clock signal 104 has an operating frequency higher than that of other signal lines (usually twice or more), and it is necessary to take measures against wiring impedance matching and delay. Also control Regarding the signal 107 and the control signal 108, the control signal 107 connected to the semiconductor memories 21 and 23 on the right side is on the right, and the control signal 108 connected to the semiconductor memory on the left is on the left. So that the length of each wiring is short.

Since the data bus has a light load capacity (when connected to one memory and one peripheral chip, the load capacity is 5 pF to 7 pF for each chip, the load capacity is 10 pF to 14 pF). Since the delay time does not increase even if the wiring is slightly longer than the signal line, arrange them on the left and right of the microcomputer 10, connect to the semiconductor memories 20, 21, 22, 23 and reach the peripheral chip 30 So that Since the data bus is as wide as 64 bits, the data bus is divided into 32 bits and placed on the left and right sides.

Signals that do not require high-speed operation should be placed on the upper side of the microcomputer (the side farther from the memory) and connected to various interfaces and connectors. Thereby, a high-speed external bus can be realized.

FIG. 2 shows a second embodiment of the present invention. In the present invention, the semiconductor memories 20 and 21 are arranged on the back surface of a printed circuit board. The memory mounted on the back is indicated by the dotted line. Also, the wiring of the memory on the back surface is shown by a dotted line. As a result, the semiconductor memories 20 and 21 are placed on the back of the semiconductor memories 22 and 23, so that the microcomputer 10 and the semiconductor memories 20 and 21 and the peripheral chips 3 The wiring of 0 can be further shortened. Wiring to the back surface can be easily achieved by providing wiring that penetrates the printed circuit board.

FIG. 3 shows a third embodiment of the present invention. In the present invention, each of the semiconductor memories 40 and 41 is a 32-bit bus memory. 3 By using 2-bit bus memory, the load capacity of clock, address, and control signals can be reduced to 3 or less (when two memories and peripheral chip 1 are connected, Since the load capacitance can be reduced from 15 pF to 21 pF, the wiring delay on the printed board is reduced. Normally, it can send about 1 nanosecond / 10 pF, so using a 32-bit bus memory can improve wiring delay by about 0.5 nanosecond and realize a high-speed external bus system.

FIG. 4 shows a fourth embodiment of the present invention. In the present invention, the peripheral chip 30 is pin-symmetrical to the microcomputer 10 and the peripheral chip 30 is arranged on the back surface of the microcomputer 10. The peripheral chip 30 arranged on the back surface of the print substrate is indicated by a dotted line.

FIG. 7 shows a mounting example of pin symmetric mounting, which will be specifically described. The microcomputer 10 and the peripheral chip 30 are both BGA (ball grid array). The print substrate 200 is a four-layer substrate and includes a wiring layer, a ground layer, a power supply layer, and a wiring layer. The pins of the microcomputer 10 and the peripheral chip 30 are signal pins 201 on the outside and the power supply pins 202 and ground pins 203 on the inside. Since the signal pin 201 is pin-symmetrical between the microcomputer 10 and the peripheral chip 30, each signal is connected via a through-hole in the printed circuit board. The power supply pin 202 and the ground pin 203 are pin-symmetrical between the microcomputer 10 and the peripheral chip 30 so that they can be connected with through holes and at the same time can be connected to the inner power supply layer and the ground layer, respectively. Connecting.

As a result, the wiring between the microcomputer 10 and the peripheral chip 30 can be connected to the wiring layers of the printed circuit board by through holes, so that the wiring length is almost zero (the thickness of the printed circuit board). can do.

With reference to FIG. 4, a description will be given of a signal requiring a low speed operation. The peripheral module 70 connected to these signals is placed on the top side of the microcomputer (the side farthest from the memories 40 and 41). Specifically, emulator 71, clock oscillator 72, 10-port 73, serial interface 74, interrupt circuit 75, etc. These circuits are connected by control signal 110 (CTRL-D). Since the control signal 110 is a low-speed signal (about several tens of MHz), the wiring on the printed circuit board may be long, and the output buffer of the microcomputer 10 may be a low-speed buffer.

Address 111 (ADR-C) is the upper pit of the address bus (A18-A25), and is used only for connection to SRAM or ROM with a relatively slow access time of 100 nanoseconds or more. Therefore, since there is no problem even if the wiring on the printed board becomes long, it can be arranged on the upper side of the microcomputer 10.

Fig. 8 shows an example of the pin arrangement of a microcomputer of a BGA (ball grid array).

Fig. 11 and Fig. 12 show the pin layout of QFP (flat package). Fig. 11 is the left half and Fig. 12 is the right half. This flat package is mounted on a lead frame, and these are mounted on a ball grid array. The package is built-in. The pins of the flat package and ball grid array package are connected by a lead frame.

9 and 10 are explanatory diagrams of the pins of the microcomputer shown in FIGS. 11 and 12. In both BGA and QFP, the lower side is a signal line that shortens the wiring length between the semiconductor memory and the left and right sides are data buses.

Figure 5 shows an example of connection between the microcomputer 10 in a BGA package and semiconductor memory. This figure is an enlarged view of the connection between the microcomputer 10 and the memory 20 in FIG. SDRAM (synchronous dynamic RAM) is used as the memory.

FIG. 6 is a diagram for explaining the pins of the SDRAM shown in FIG. The SDRAM 20 is mounted horizontally with the address pins inside. Hereinafter, the wiring between the microcomputer 10 and the memory 20 will be described. First, the clock 104 (CKI0) is prioritized. Next, address bus 105 (A3-A6), 106 (A7-A14) Connect. Here, A13 and A14 are connected through the back of the memory 20. The control signal 1 08 has a different function depending on the memory to be connected. Connect to UDQM, LDQM of 0. The LDQM wiring passes through the back of the memory 20. As for the control signal 109, CS2 # is connected to CS # (chip select) of memory 20 and RAS # is connected to RAS # of memory 20. Since RD # / CASS # / FRAME # has different functions depending on the connected memory, in the case of SDRAM, select CASS # function and connect to CAS # of memory 20. RD / WR # is connected to WE # of memory 20.

The data bus 100 connects the 16-bit data bus between the microcomputer 10 and the memory 20 one-to-one. Here, D8 and D15 are connected to the memory 20 via a wiring layer on the surface, and DO-D7 is connected to the data pins of the memory through the back of the memory 20.

With such a connection, the wiring between the microcomputer 10 and the memory 20 can be minimized. At the same time, since most of the wiring can be done only on the top wiring layer, the number of through-holes is reduced, making it easier to adjust the wiring impedance and strengthening the power ground layer.

Similarly, the other memories 21, 22 and 23 can be similarly connected in the shortest possible manner. Although the present embodiment has been described with reference to the SDRAM, the present invention is also applicable to other high-speed memories.

If the degree of integration of the LSI further increases in the future, each module of the microcomputer 10, the semiconductor memories 20, 21, 22, 23, and the peripheral chip 30 can be integrated into one chip. Also in this case, it is possible to realize high-speed operation wiring between modules by using the arrangement of the embodiment shown here.

The present invention relates to an amusement device, an image processing device, and a portable information device. It is not limited, and can be applied to household electrical appliances, information and communication equipment, and control devices.

An embodiment of the package of the semiconductor control device of the present invention will be described with reference to FIG. FIG. 13 is a view of the package as viewed from the back. ,. An example of the package is a 256-pin BGA (ball grid array) package. ° There are 256 pins (balls) 320 on the back side of the package 310 chip. Pins 320 are arranged in 20 vertical rows and 20 horizontal rows.If all of them are mounted, they will have 400 pins. In the case of package 310, the inner 144 pins are not mounted, and the outer four rows of pins are mounted. The outermost circumference is 20 vertical and 20 horizontal, the inside is 18 vertical and 18 horizontal, and the inner is 16 vertical 16 horizontal and the innermost mounted is 14 vertical and 14 horizontal. Individual. In this embodiment, the outer shape of the package is about 27 mm square.

FIG. 14 is a cross-sectional view of the package 310 at A in FIG. 13 to explain the internal configuration of the package 310. ,. The logic LSI chip 70 and the read frame 90 are mounted inside the package 310, and the bonding PAD 71 and the read frame 90 created on the logic LSI chip 70 are Each pin is connected by a bonding wire 80.

The lead frame 90 and the pin 320 are connected by through holes for each pin. The innermost pin 340 is located very close to the point of contact between the bonding wire 80 and the lead frame 90, so there is little inductance in the lead frame 90 and the wire bonding 80 You can only see the conductance. On the other hand, since the outer pin 21 is further away from the contact point between the wire bonding 80 and the lead frame 90 to the pin 21, the influence of the inductance of the lead frame 90 appears. Therefore, the innermost pin 340 has smaller inductance than the other pins. Suitable for use as a power supply Z ground pin.

FIG. 15 shows a schematic diagram of the inside of the package 310, which will be described in more detail. Here, to simplify the figure, the number of bonding pads 71 on the logic LSI chip 70 is 40 (10 on each side), and the total number of pins 320 is 40. The inner side is composed of 5 rows, the outer side is 5 sides, and the inner side is 5 sides.

It is assumed that the logic LSI chip 70 operates with a two-power supply configuration of a power supply 51 for 10 and a power supply 50 for internal logic. Here, it is assumed that the internal logic power supply 50 has a lower voltage than the normal 10 power supply 51 in order to reduce the power consumption of the chip. In addition, there are four 10 power supply 51 pins, eight 10 ground 61 pins, four internal logic power supply 50 pins, and four internal logic ground 60 pins.

First, the internal configuration of the logic LSI chip 70 will be briefly described. The logic LSI chip 70 includes an area 73 operated by the power supply 51 and an area 74 operated by the power supply 50 for the internal logic. The 10 power supply operation area 73 mainly consists of a bonding pad 71, an input / output circuit, and a level conversion circuit 72 that converts the voltage level of the internal power supply to the voltage level of the 10 power supply. Control. However, when the power supply voltage for 10 and the power supply voltage for internal logic are the same, the level conversion circuit is not required. The internal power supply operation area 74 contains the main functions of microcomputers and logic LSIs.

Next, the configuration of the pins 320 on the package 310 and the lead frame 90 will be described. To reduce the inductance of the power and ground bins, the power and ground pins are assigned to the inner pins, and the signal lines are assigned to the outer pins. The length of the bonding wire 80 connecting the bonding PAD 71 and the lead frame 90 on the logic LSI chip 70 is almost the same for both the signal pin and the power supply / ground bin. Power / ground pin lead frame The wiring length is reduced to about 1/2 to 1733 of the wiring length of the outer signal line lead frame, and the inductance of the power / ground bin lead frame is reduced.

FIG. 16 illustrates the configuration of the pin arrangement of the 256 pins, which operates in a dual power supply configuration of 10 power supply 51 and internal logic power supply 50. Here, it is assumed that 10 power supplies are 3.3V and the internal power supply is 1.8V. The internal logic power supply 50 (shown by black pins in the figure), the internal logic ground 60 (shown by black pins in the figure), the power supply 51 for 10 and the ground 61 for 10 , Assign to the second row of pins from the inside. The internal logic power supply 50 and ground 60 have nothing to do with the noise of the output buffer, so the number of pins is determined by the power consumption of the internal logic. In general, the power consumption of an LSI chip that can be mounted on a plastic package is about 1 to 1.5 bits.

The power supply 50 and ground 60 pins need less. Here, two internal power supplies 50 and two grounds 60 are assigned to each side. The rest can be assigned to the power supply 51 for 10 and the ground 61 for 10.

FIG. 17 shows an embodiment in which the power supply / ground and the decapping capacitor 400 are mounted on the printed circuit board 110. Here, the ground pin is assigned to the innermost pin 340, and the power supply pin is assigned to the second row of pins 340 from the inside. The print substrate is a four-layer substrate, the first layer is a wiring layer, the second layer is a ground layer, the third layer is a power supply layer, and the fourth layer is a wiring layer.

No ,. The package on the back side of the package 3 10 is not mounted with the first layer 4 0 1 is the ground plane 4 0 1 on the printed circuit board 1 1 0, and the wiring length between this ground plane 4 0 1 and the ground bin Is the shortest. This makes it possible to reduce the inductance component of the ground wiring even on the print substrate 110. In addition, the decoupling capacitor 400 mounted between the power supply pin and the ground bin can be mounted on the fourth layer with a through hole near the power supply pin and the ground bin, and can be mounted with the shortest wiring. As a result, the wiring length of the power supply ground on the printed circuit board 110 can be minimized, and the chip coupling capacitor 400 can also be arranged at the shortest position. This makes it possible to suppress the switching noise of the output buffer.

Next, wiring of signal lines on a printed circuit board will be described.

FIG. 18 shows a configuration diagram of a pin arrangement in which a portion B in FIG. 13 is enlarged. The size of the pin 320 is 0.75 mm, and the distance between the pins 320 is 1.27.

Fig. 19 shows the configuration of the printed circuit board when this package is mounted. Assuming that the size of the foot pattern 102 on the printed circuit board to be connected to the pin 320 by solder is 0.95 mm, the spacing between the foot patterns 102 is 0.3 mm. The signal line 55 that can be drawn out by the above is one signal line having a wiring width of 0.1 mm and an interval between foot patterns of 0.1 mm. Since the signal lines are assigned to the outer two rows of pins, all the outermost and outermost signal lines can be pulled out of the chip. This allows the signal line to be drawn out of the package without using a through hole. The printed circuit board on the back of the package does not require through-holes for signal lines, so that the through-holes can be used to reduce the area of the inner power ground plane ground plane, and the power ground plane can be strengthened. As a result, the signal line from the package 310 can be easily connected to an external chip or connector.

FIG. 8 shows an embodiment of the pin arrangement of the microcomputer. FIG. 9 and FIG. 10 are tables for explaining the role of the signal pins of the microcomputer. An example of this package is a BGA (Ball Grid Package). Inside The pins are assigned to place the power supply in the second row from the innermost ground. The number of power supplies for 10 is 30, the number of grounds for 10 is 32, the number of power supplies for internal logic is 8, and the number of grounds for internal logic is 8. The number of power supplies / grounds for 10 is one pair for four output signal lines. Data buses (DO-D63), address buses (A2-A17), control signals (CK I0, CS2 #, CS3 #, RAS, R / CASS) required for interfacing with high-speed memory # / FRAME #, WEn # / CASn # / DQMn (n = 0-7)), etc. are always assigned to the outer two columns. If the number of signal lines is not sufficient in the two outer rows, some signal lines may be assigned to the two inner rows.

As described above, by arranging the power supply ground inside the pins of the package of the semiconductor control device such as the microcomputer and the logic LSI, it is possible to provide a semiconductor control device that is resistant to output buffer switching noise. . The present invention can be applied not only to a BGA package but also to a PGA (Pingled Array) package and a CSP (Chip Size Package) in which a ball is similarly arranged on the back surface of a chip.

In a semiconductor control device mounted on a package with two-dimensionally arranged pins on the array on the back of the package, power and ground are arranged on inner pins, and signal lines are arranged on outer pins. A semiconductor control device comprising: a ground disposed on an innermost pin; and a power supply pin disposed on a second row of pins from the inner side.

A semiconductor control device that operates on two power supplies, a power supply for 10 and a power supply for internal logic, and has more power supplies and ground bins for 10 than for internal logic.

A semiconductor device, comprising: a semiconductor chip; a package containing the semiconductor chip; and a plurality of terminals disposed on a surface of the package. The terminals include a first plurality of terminals for supplying power or ground to the semiconductor chip, and a second plurality of terminals for inputting signals to or outputting signals from the semiconductor chip. The set A of the shortest distance between the outer edge and the outer edge of each of the first type terminals is A 1 to AN (where N is the number of the first type terminals), and the outer edge of the semiconductor chip and the second type terminal When the set B of the shortest distance from each outer edge is B1 to BM (where M is the number of terminals of the second type), the smallest set B is the largest set A and the largest set A A semiconductor device characterized by being the same or more.

The plurality of terminals are arranged in a matrix on a plane having the largest area among the planes forming the outer shape of the package, the plane having the largest area is rectangular, and the outer edge of the rectangular plane and the first type of terminal are arranged. The set of the shortest distances from the outer edges AX is AX1 to AXN (where N is the number of terminals of the first type), and the shortest distance between the outer edge of the rectangular planar surface and the outer edges of the terminals of the second type is If the set of distances BX is BX1 to BXM (where M is the number of terminals of the second type), the largest of the set BX must be equal to or greater than the smallest of the set AX A semiconductor device characterized by the above-mentioned.

A semiconductor device comprising: a semiconductor chip; a package containing the semiconductor chip; and a plurality of terminals arranged in a matrix at equal intervals on the surface of the package, wherein the outermost terminal among the terminals arranged in a matrix is a first terminal. The terminal that is the shortest distance from the terminal of the first group is the second group, and the terminal that is the shortest distance from the terminal of the second group and does not belong to the first group is the third group. A semiconductor device, wherein when grouped, the proportion of terminals other than the signal input / output terminals in the third group is larger than that in the first group.

The ratio of terminals other than signal input / output terminals in the third group A semiconductor device characterized by being larger than that of the group.

When the terminals that are the shortest distance from the terminals of the third group and do not belong to the second group are the fourth group, the ratio of terminals other than the signal input / output terminals in the fourth group is the first group. A semiconductor device that is larger than that of the semiconductor device group.

A semiconductor device, characterized in that the terminals other than the signal input / output terminals include terminals for supplying first and second potentials for driving a logic circuit formed in the semiconductor chip.

A semiconductor device, characterized in that terminals other than the signal output terminal further include terminals for supplying third and fourth potentials for driving a logic circuit formed in the semiconductor chip.

Terminals for supplying first and second potentials for driving a specific logic gate formed in the semiconductor chip are divided into terminals belonging to third and fourth groups, and A semiconductor device.

Terminals for supplying the third and fourth potentials for driving specific logic gates formed in the semiconductor chip are arranged separately in terminals belonging to the third and fourth groups A semiconductor device characterized by the above-mentioned. The terminals separately arranged in the terminals belonging to the third and fourth groups are terminals arranged at the closest positions.The semiconductor package is arranged on a printed circuit board. Wiring is drawn out from the terminals belonging to the first and second groups along the board surface, and wiring is drawn out from the terminals belonging to the third and fourth groups through through holes penetrating the board. A semiconductor device characterized by the above-mentioned.

The signal input / output terminal is an input signal to be processed by a logic circuit formed in the semiconductor chip or a logic circuit formed in the semiconductor chip. A conductor device for transmitting an output signal processed by a path. A semiconductor device comprising: a semiconductor chip; a package containing the semiconductor chip; a plurality of conductor pins arranged on a surface of the package; and a lead frame for electrically connecting the semiconductor chip pad and the conductor pin. The plurality of pins receive a first type of pins for supplying at least two potentials for driving active elements formed on the semiconductor chip and a signal modulated by the active element of the semiconductor chip. Alternatively, the semiconductor device includes a plurality of pins of a second type for outputting a signal modulated by an active element of a semiconductor chip, and the longest wiring length between the first type of pins and the pad is the second type of pins. A semiconductor device characterized by not exceeding a minimum wiring length between pads. A semiconductor wherein the plurality of pins of the first type are arranged so as to surround the outer edge of the semiconductor chip, and the pins of the second type are arranged so as to surround the plurality of pins of the first type. apparatus.

The package is placed on a printed circuit board, and most of the pins of the second type lead out along the surface of the board, and most of the pins of the first type penetrate the board A semiconductor device characterized in that wiring is drawn out through a through hole.

Claims

The scope of the claims

1. A microcomputer control device comprising a microcomputer, a peripheral control semiconductor device, and a plurality of semiconductor memories, wherein a plurality of semiconductor memories are arranged between the microcomputer and the peripheral semiconductor device.

2. A clock signal is output from the center of the side of the microcomputer closest to the semiconductor memory, an address signal is output from the left and right of the clock output, and a control signal is output from outside the address output. 2. The microcomputer control device according to claim 1, wherein a data bus is output from a side of the microcomputer and the semiconductor memory next to each other.

3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device disposed between the microcomputer and the peripheral control semiconductor device is arranged horizontally with the address pins being inside, the data pins being outside, and being arranged horizontally. Microcomputer control device.

4. The microcomputer control device according to any one of claims 1 to 3, wherein the pin arrangement of the microcomputer and the peripheral control semiconductor device is axisymmetric.

5. The microcomputer has a package of two-dimensionally arranged pins arranged in an array on the back surface, with the power supply pins and ground pins arranged inside and the signal line pins arranged outside. 4. The microcomputer control device according to claim 1, wherein the microcomputer control device is arranged.

6. The microcomputer control device according to claim 5, wherein, in the microcomputer package, a ground pin is arranged on an innermost side, and a power supply pin is arranged in a second row from the inner side.

7. The microcomputer control device according to claim 1, wherein the microcomputer, the peripheral control semiconductor device, and the plurality of semiconductor memories are integrated into one chip.

8. The first semiconductor device with an arithmetic function and the second and And a third semiconductor device, wherein the axis passing through the first semiconductor device is assumed to be the Y axis, and the second and third semiconductor devices are arranged in line symmetry with respect to the Y axis. And a clock signal terminal for outputting a clock signal on a side of the first semiconductor device close to the second and third semiconductor devices. The clock signal terminal receives the clock signal from the clock signal terminal. Information processing equipment supplied to the second and third semiconductor devices.

9. The information processing apparatus according to claim 8, wherein the second and third semiconductor devices are arranged along the direction of the X axis when an X axis orthogonal to the Y axis is assumed. A fourth semiconductor device having an arithmetic function, wherein the second and third semiconductor devices are arranged between the fourth semiconductor device and the first semiconductor device; 10. The clock signal input terminal according to claim 9, wherein the clock signal supplied from the third semiconductor device is input to a clock signal input terminal of the fourth semiconductor device which is arranged on a side of the fourth semiconductor device close to the second and third semiconductor devices. Information processing device.

11. The information processing apparatus according to claim 10, wherein the wiring for transmitting the clock signal passes between the second and third semiconductor devices.

12. The device according to claim 11, further comprising an address signal terminal on the left and right of the clock terminal of the first semiconductor device, wherein an address signal is supplied to the second and third semiconductor devices from the address signal terminal. Information processing device.

13. The first semiconductor device has a package having a pin arrangement arranged two-dimensionally in an array on the back surface, wherein the pin arrangement includes a power supply pin and a ground pin arranged inside and a pin arranged outside. 13. The information processing apparatus according to claim 8, wherein pins of the signal line are arranged.

14. The package of the first semiconductor device, wherein a ground pin is arranged on the innermost side, and a power supply pin is arranged on the second column from the inner side. 13. The information processing apparatus according to claim 13.

15. When the side of the first semiconductor device where the clock signal terminal is located is the first side, and the sides on both sides of the first side are the second and third sides, the arrangement is made on each side. The ratio of the number of data signal input / output terminals to the number of terminals to be set is set so that the ratio on the second or third side is larger than the ratio on the first side. Information processing device.

16. The second and third semiconductor devices have long sides in a direction parallel to the X-axis, and the terminal to which the address signal is input is longer than the data signal input / output terminal on the long side. 16. The information processing device according to claim 15, wherein the information processing device is arranged near the Y axis.

17. An address signal input terminal is provided on the same side as a side of the fourth semiconductor device where a clock signal input terminal is provided, and an address signal from the first semiconductor device is input to the address signal input terminal. Information processing equipment described in Item 16

18. A side where the clock signal input terminal of the fourth semiconductor device is located is defined as a first side, and both sides of the first side are defined as second and third sides. The information according to claim 17, wherein the ratio of the number of data signal input / output terminals to the number of terminals to be set is set to be larger in the second or third side than in the first side. Processing equipment.

1 9. Fifth and sixth semiconductor devices having the same configuration as the second and third semiconductor devices are provided, and the fifth and sixth semiconductor devices are arranged symmetrically with respect to the Y axis. And the fifth and sixth semiconductor devices have a long side in a direction parallel to the X-axis, and a terminal to which an address signal is input on the long side is a data signal. 19. The information processing device according to claim 18, wherein the information processing device is arranged closer to a clock signal terminal of the first semiconductor device than an input / output terminal.

20. The fifth and sixth semiconductor devices are arranged on the same substrate surface as the substrate surface on which the second and third semiconductor devices are arranged, and the first and fourth semiconductor devices are arranged on the same substrate surface. The information processing apparatus according to claim 19, which is arranged between semiconductor devices.

21. The fifth and sixth semiconductor devices are arranged on a substrate surface opposite to the substrate surface on which the second and third semiconductor devices are arranged, and the second and third semiconductor devices are arranged on the second semiconductor device with respect to the substrate. 10. The information processing device according to claim 19, wherein the information processing device is arranged so as to be plane-symmetric with the third semiconductor device.

22. The information processor according to claim 20 or 21, wherein said second, third, fifth, and sixth semiconductor devices are semiconductor memories having a 16-bit data bus.

23. At least one of an Emiure, a clock oscillation circuit, an input / output port, a serial interface, and an interrupt circuit is provided as a peripheral module, and the first to the first semiconductor devices of the first semiconductor device are provided. The information processing device according to any one of claims 13 to 22, wherein a terminal arranged on a side other than the side (3) is connected to the peripheral module.

24. A semiconductor memory different from the second and third semiconductor devices is provided, and terminals arranged on sides other than the first to third sides of the first semiconductor device are connected to the semiconductor memory. 23. The information processing apparatus according to claim 23, wherein 25. The information processing device according to any one of claims 10 to 24, wherein the fourth semiconductor device is a semiconductor device for processing image data.

26. The fourth semiconductor device has a two-dimensionally arranged pin-shaped package arranged in an array on the back surface, with the power supply pin and the ground pin arranged inside and the pin arrangement outside. 26. The information processing apparatus according to claim 10, wherein pins of signal lines are arranged.

27. In the package of the fourth semiconductor device, the innermost ground 27. The information processing apparatus according to claim 26, wherein pins are arranged, and power pins are arranged in a second row from the inside.

28. An information processing apparatus comprising a microcomputer and two semiconductor memories arranged on a substrate, wherein the two semiconductor memories are arranged side by side in a direction parallel to the first side of the microcomputer. Microcomputer and semiconductor memory are connected by a clock bus, address bus, and data bus, and information processing in which the computer bus is connected to a terminal located on the first side of the microcomputer apparatus.

29. The microcomputer has a package having a pin arrangement arranged two-dimensionally in an array on the back surface, with a power supply pin and a ground pin arranged inside and a signal line outside. 29. The information processing apparatus according to claim 28, wherein the pins are arranged.

30. The information processing apparatus according to claim 29, wherein in the microcomputer package, a ground bin is arranged on the innermost side, and a power supply pin is arranged in a second row from the inner side.

31. Among the terminals arranged on the second side and the third side sandwiching the first side of the microcomputer, the ratio of the terminal connected to the data bus is equal to the ratio of the terminal connected to the first side. 29. The information processing apparatus according to claim 28, wherein the ratio of the terminals connected to the data bus is larger than the ratio of the terminals arranged.

32. The information processing apparatus according to claim 28 or 31, wherein the address bus is connected to a terminal arranged on a first side of the microcomputer. 33. The long sides of the two semiconductor memories are parallel to the first side of the microcomputer, and the address bus and the data bus are connected to terminals arranged on the long sides. 33. The information processing apparatus according to claim 28, wherein the address bus is connected to a terminal near an opposite side of the information bus.

34. The computer bus is connected to a terminal on a long side of the two semiconductor memories, between a terminal connected to the address bus and a terminal connected to the data bus. Information processing device.

35. A first data processing device having a rectangular parallelepiped shape, a second data processing device, a plurality of storage devices, and an information processing device including a board on which the first and second data processing devices are mounted. Assuming the X axis and the Y axis, the first and second data processing devices are arranged on the Y axis, the plurality of storage devices are arranged in line symmetry with the Y axis, and the X axis is An information processing apparatus, wherein the plurality of storage devices are arranged symmetrically with each other, and the first and second data processing devices are arranged with the plurality of storage devices interposed therebetween.

36. Wiring for supplying a clock signal is connected between opposing surfaces of the first data processing device and the second data processing device, and the plurality of storage devices are divided on both sides of the wiring. The information processing device according to claim 35, wherein the information processing device is arranged.

37. A terminal on a surface on the right side of the Y-axis of the first or second data processing device and a storage device on the right side of the Y-axis among the storage devices are connected by a data bus, Alternatively, a terminal on a surface on the left side of the Y-axis of the second data processing device and a storage device on the left side of the Y-axis among the storage devices are connected by a data bus. 36. Information processing device according to 6.

38. A first data processing device having a rectangular parallelepiped shape, a second data processing device, a plurality of storage devices, and an information processing device including a board on which the first and second data processing devices are mounted. First and second data processing devices are arranged, and the input or output terminal of the first data processing device is connected to the first or second data processing device.

2 is located at the position facing the output or input terminal of the data processing device. An information processing apparatus, comprising:

39. The plurality of storage devices are arranged with the substrate surface interposed therebetween, and a clock input terminal, an address input terminal, and a data input terminal of the storage device are arranged at positions facing each other. Claims 3 8 Information processing