JPS60219794A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS60219794A
JPS60219794A JP59077025A JP7702584A JPS60219794A JP S60219794 A JPS60219794 A JP S60219794A JP 59077025 A JP59077025 A JP 59077025A JP 7702584 A JP7702584 A JP 7702584A JP S60219794 A JPS60219794 A JP S60219794A
Authority
JP
Japan
Prior art keywords
substrate
integrated circuit
hybrid integrated
chip
sides
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59077025A
Other languages
Japanese (ja)
Inventor
出田 洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59077025A priority Critical patent/JPS60219794A/en
Publication of JPS60219794A publication Critical patent/JPS60219794A/en
Pending legal-status Critical Current

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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、基板の両面圧電気配線用導体を有する混成
集積回路に関するものである。
TECHNICAL FIELD OF THE INVENTION This invention relates to a hybrid integrated circuit having conductors for piezoelectric wiring on both sides of a substrate.

〔従来技術〕[Prior art]

従来の混成集積回路とシ、′″C,、第1図および第2
図に示すものがある。
Conventional hybrid integrated circuit and C, Figures 1 and 2
There is one shown in the figure.

第1図は従来の混成集積回路の一面シ示す図で、第2図
はもう一方の面ケ示す図である。
FIG. 1 is a diagram showing one side of a conventional hybrid integrated circuit, and FIG. 2 is a diagram showing the other side.

第1図、第2図において、1oはセラミック等ノ基板、
11aはチップトランジスタ、11bはチップコンデン
サ、11cはミニモールドタイプのモノリシックICで
ある半導体チップ、12は電気配線用導体、13は外部
リード層、14はこの外部リード#i!13と電気配線
用導体12とン接続する端子、15は前記基板10に直
接取り付けられた半導体チップw4Ji、Fkする樹脂
、16は#E]図に示す面と第2図に示す面の電気配線
用導体12′を接続するスルーホール、11は前記基板
10に印刷された厚膜抵抗体である。
In FIGS. 1 and 2, 1o is a ceramic substrate,
11a is a chip transistor, 11b is a chip capacitor, 11c is a semiconductor chip which is a mini-mold type monolithic IC, 12 is an electric wiring conductor, 13 is an external lead layer, and 14 is this external lead #i! 13 is a terminal connected to the electrical wiring conductor 12; 15 is a semiconductor chip w4Ji directly attached to the substrate 10; 16 is a resin for Fk; 16 is electrical wiring on the surface shown in the figure and the surface shown in FIG. The through hole 11 connecting the conductor 12' is a thick film resistor printed on the substrate 10.

両面配線の基板10を使用した混成集積回路では、第】
図、第2図に示したように、チップトランジスタ11a
、チップコンデンサ11b、ミニモールドICなどの半
導体チップ11cや樹脂15で保護されている半導体チ
ップ、基板10に印刷された厚膜抵抗体1Tが、両面に
電気配線が行われている基板100両面に塔載されてい
る。これら基板100両面に配置された各素子7必要な
回路に接続するためには、基板10の第】図に示す面と
第2図に示す面の電気配線用導体12の接続をしなけれ
ばならない。従来、第1図、第2図で示すようなスルー
ホール16と端子14ン外部リード線13ではさみ込む
ことKよる2通りの手法によって、第1図忙示す面と第
2図に示す面の間の配線の接続ケ行っていた。
In a hybrid integrated circuit using a board 10 with double-sided wiring,
As shown in FIG. 2, the chip transistor 11a
, a chip capacitor 11b, a semiconductor chip 11c such as a mini-mold IC, a semiconductor chip protected by resin 15, and a thick film resistor 1T printed on the substrate 10 are placed on both sides of the substrate 100, which has electrical wiring on both sides. It is listed on the tower. In order to connect each of the elements 7 arranged on both sides of the board 100 to the necessary circuits, it is necessary to connect the electrical wiring conductors 12 on the side shown in Figure 1 and the side shown in Figure 2 of the board 10. . Conventionally, the surface shown in FIG. 1 and the surface shown in FIG. The wiring between them was connected.

上記したように、従来の両面に電気配線用導体12欠持
つ混成集積回路ではスルーホール16が使われていた。
As mentioned above, through holes 16 have been used in conventional hybrid integrated circuits that lack electrical wiring conductors 12 on both sides.

混成集積回路用の基板10にスルーホール16を使用す
ると、基板10の製造工程数が増加し、基板両面間の各
工程の印刷位置を精密に合わせる必要があるなど、スル
ーホール16なしの基板10と比べると基板コストが著
しく上昇するという欠点があった。また、基板1.OK
セラミックケ使用した場合、基板10にスルーホール1
6Yあけることが困難であり、穴あきのセラミツフケ専
用に使用する必要があり、高価格、工期の長期化の一因
にもなっている。
If through holes 16 are used in the substrate 10 for hybrid integrated circuits, the number of manufacturing steps for the substrate 10 will increase, and the printing position of each step between both sides of the substrate must be precisely aligned. The disadvantage was that the cost of the substrate increased significantly compared to the conventional method. In addition, the substrate 1. OK
When using ceramic board, through hole 1 is made on board 10.
It is difficult to drill 6Y, and it must be used exclusively for ceramic dandruff with holes, which is one of the causes of high prices and long construction times.

〔発明の概要〕[Summary of the invention]

この発明は、上週のような欠点をなくすためになされた
もので、両面配線の混成集積回路において、スルーホー
ルを使用することなく、必要な回路結線か得られる混成
集積回路Y提供することである。以下、このyABA′
VCついて図面を用いて15!明するO 〔発明の実施例〕 第3図、第4図はこの発明の一実施例を示すもので、1
0〜1.7 ii第1a、第2図と同じなので説明を省
略する。21は前記基板10の第3図に示す面と第4図
に示す面の電気配線用導体12’&短絡させるための導
電性クリップ、22はこの導電性クリップ21と電気配
線用導体12とt接続する接続端子である。第3図、第
4図に示(、たような基板10の両面に電気配線が行わ
れている混成集積回路では、チップトランジスタ11a
、チップコンデンサ11b、半導体チップ11C1樹脂
15.厚膜抵抗体17’%’、基板100両面に塔載し
ている。この実施例では、 nil記チップトランジス
タ11a、チップコンデンサ11bや半導体チップ11
c、厚膜抵抗体1Tに接続された基板100両面にある
電気配線用導体12ケ、基板10の周囲に配置した接続
端子22と短絡用の導電性クリップ21.および外部リ
ード接続用の端子14と外部リード線13によって接続
し、必要な回路結線を得る。
This invention was made in order to eliminate the above-mentioned drawbacks, and by providing a hybrid integrated circuit Y that can obtain the necessary circuit connections without using through holes in a double-sided wiring hybrid integrated circuit. be. Below, this yABA'
15 using drawings with VC! [Example of the invention] Figures 3 and 4 show an example of this invention.
0 to 1.7 ii Since this is the same as in Figures 1a and 2, the explanation will be omitted. 21 is a conductor 12' for electrical wiring on the surface shown in FIG. 3 and the surface shown in FIG. This is the connection terminal to be connected. In the hybrid integrated circuit shown in FIGS. 3 and 4, in which electrical wiring is provided on both sides of the substrate 10, the chip transistor 11a
, chip capacitor 11b, semiconductor chip 11C1 resin 15. 17'%' of thick film resistors are mounted on both sides of the substrate 100. In this embodiment, a nil chip transistor 11a, a chip capacitor 11b, and a semiconductor chip 11 are used.
c. 12 conductors for electrical wiring on both sides of the substrate 100 connected to the thick film resistor 1T, connecting terminals 22 arranged around the substrate 10 and conductive clips 21 for shorting. The external lead connection terminal 14 is connected to the external lead wire 13 to obtain the necessary circuit connection.

なお、上記実施例では、基板10の片面にチップトラン
ジスタ11a、チップコンデンサ11b。
In the above embodiment, a chip transistor 11a and a chip capacitor 11b are provided on one side of the substrate 10.

半導体チップ11C2樹脂15を、他の片面に厚膜抵抗
体17”k塔載したものを示したが、基板10の両面に
チップトランジスタ11a、チップコンデンサ11b、
半導体チップ11c、樹脂15゜厚膜抵抗体17火混ぜ
て塔載したものでもよい。
Although the semiconductor chip 11C2 resin 15 is shown with a thick film resistor 17"k mounted on the other side, chip transistors 11a, chip capacitors 11b,
The semiconductor chip 11c, resin 15° thick film resistor 17 may be mixed and mounted on a tower.

また、基板100片面にチップトランジスタ11a、チ
ップコンデンサ11b、半導体チップ11C1樹脂15
.厚膜抵抗体177塔載し、他の面には電気配線用導体
12のみであってもよい。
Further, on one side of the substrate 100, a chip transistor 11a, a chip capacitor 11b, a semiconductor chip 11C1 and a resin 15 are provided.
.. The thick film resistor 177 may be mounted on the other surface, and only the electrical wiring conductor 12 may be provided on the other surface.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したようK、この発明は絶縁物からなる
基板と、前記基板の両面に装着された複数の部品と、前
記基板上で前記各部品に接続された各電2配線用導体と
から構成される混成集積回路において、前記基板の両面
にある前記各電気配線用導体を結合して両面間の電気的
接続を行うための導電性クリップを設けたので、スルー
ホールン使用することなく、安価で生産性の高い基板を
使用することができる利点かある。
As explained in detail above, the present invention consists of a board made of an insulating material, a plurality of parts mounted on both sides of the board, and conductors for each electric wiring connected to each part on the board. In the hybrid integrated circuit configured, a conductive clip is provided to connect the electrical wiring conductors on both sides of the substrate and make an electrical connection between the two sides. There is an advantage of being able to use a highly productive board.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は両面基板を使用した従来の混成集積回路の一方
の面を示す概略図、92図は従来の混成集積回路の他の
面を示す概略図、第3図はこの発明の一冥施装置よる混
成集積回路の一方の面を示す概略図、第4図は同じく混
成集積回路の他の面を示す概略図である。 図中、10は基板、11aはチップトランジスタ、11
bはチップコンデンサ、11eは半導体チップ、12は
電気配線用導体、13は外部リード線、14は端子、1
5は樹脂、1Tは厚膜抵抗体、21は導電性クリップ、
22は接続端子である。 なお、図中の同一符号は同一または相当部分を示す。 代理人 大 岩 増雄 (外2名) 第1図
FIG. 1 is a schematic diagram showing one side of a conventional hybrid integrated circuit using a double-sided substrate, FIG. 92 is a schematic diagram showing the other side of the conventional hybrid integrated circuit, and FIG. FIG. 4 is a schematic diagram showing one side of the hybrid integrated circuit according to the device, and FIG. 4 is a schematic diagram showing the other side of the hybrid integrated circuit. In the figure, 10 is a substrate, 11a is a chip transistor, 11
b is a chip capacitor, 11e is a semiconductor chip, 12 is an electrical wiring conductor, 13 is an external lead wire, 14 is a terminal, 1
5 is a resin, 1T is a thick film resistor, 21 is a conductive clip,
22 is a connection terminal. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1

Claims (1)

【特許請求の範囲】[Claims] 絶縁物からなる基板と、前記基板の両面に装着された複
数の部品と、前記基板上で前記各部品に接続された各電
気配線用導体とからS成される混成集積回路において、
前記基板の両面にある前記各電気配線用導体ケ結合して
両面間の電気的接続を行うための導電性クリップケ設け
たことケ特徴とする混成集積回路。
A hybrid integrated circuit consisting of a substrate made of an insulating material, a plurality of components mounted on both sides of the substrate, and electrical wiring conductors connected to each of the components on the substrate,
A hybrid integrated circuit characterized in that conductive clips are provided for coupling the electrical wiring conductors on both surfaces of the substrate to establish an electrical connection between the two surfaces.
JP59077025A 1984-04-16 1984-04-16 Hybrid integrated circuit Pending JPS60219794A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59077025A JPS60219794A (en) 1984-04-16 1984-04-16 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59077025A JPS60219794A (en) 1984-04-16 1984-04-16 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS60219794A true JPS60219794A (en) 1985-11-02

Family

ID=13622205

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59077025A Pending JPS60219794A (en) 1984-04-16 1984-04-16 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS60219794A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62186459U (en) * 1986-05-20 1987-11-27

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4992960U (en) * 1972-12-04 1974-08-12
JPS5039763U (en) * 1973-08-10 1975-04-23
JPS5067962A (en) * 1973-10-20 1975-06-06

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4992960U (en) * 1972-12-04 1974-08-12
JPS5039763U (en) * 1973-08-10 1975-04-23
JPS5067962A (en) * 1973-10-20 1975-06-06

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62186459U (en) * 1986-05-20 1987-11-27

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