JPH06140508A - Ic for analog and digital to coexist in - Google Patents

Abstract

PURPOSE:To realize an IC in which analog and digital coexist with such a structure as to be able to reduce a useless empty region. CONSTITUTION:A region 31 for supply voltage, regions 32, 33, 34 for analog circuits and a region 35 for grounding are almost arranged in a line between the one side of an IC chip 100 and region 200 for digital. In a region formed of the replacement, wiring lines 310b, 310c, 350a, 350b for power supply are arranged in a line from the region 31 for supply voltage or the region 35 for grounding to the regions 32, 33 34 for analog circuits. Thereby, a bundle of analog circuits can be thickly arranged within a square region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital coexistence IC, and more particularly to an analog / digital coexistence IC in which an analog circuit and a digital circuit coexist on the same chip.

[0002]

2. Description of the Related Art For example, a so-called standard cell type A
In SIC and the like, it is often necessary that a digital circuit such as a microcomputer and an analog circuit that controls the I / O function coexist in one IC. In such a case, since a large part of the area of the IC chip is occupied by the digital circuit and the design of the digital circuit has priority, the analog circuit is often arranged in the peripheral portion of the IC chip. Further, the fact that the input / output pads of the IC are usually arranged in the peripheral portion of the IC chip and the I / O related circuits perform input / output through these input / output pads further strengthens this tendency. .

FIG. 2 shows a conventional analog / digital coexistence I.
An example of C is shown. Here, 10 is an IC chip, 20 is an MP
Reference numeral 30 is a digital area in which digital circuits such as U and memory are arranged, and numeral 30 is an analog circuit area in which analog circuits such as A / D conversion circuits that handle analog signals are arranged. In this example, the analog circuit area 30 is arranged so as to surround three sides of the digital area 20 in the peripheral portion of the IC chip 10. Reference numeral 31 is a power supply voltage region including an external connection IC pad that receives supply of power supply voltage, and 32, 33, 34.
Is an analog circuit area assigned to each I / O function, and 35 is a ground area including a pad to be grounded.

In such IC layout design, normally,
The design in the digital domain 20 precedes because the focus is on the design of the digital circuit that carries the main function. In the design of a digital circuit, a region is divided into blocks for each library cell, and a required function is appropriately embodied as a circuit and assigned to each block. Then, in the next stage, the design in the analog circuit area 30 is performed. Even at this stage, the analog circuit areas, which are block-shaped in a line and have substantially the same quadrilateral shape, are used for I / O.
An analog circuit having a corresponding function is embodied for each analog circuit area.

Further, the analog circuit area 32,
In order to supply power to the circuits of 33 and 34, a power supply voltage region 31 and a ground region 35 are arranged on both sides of these analog circuit regions 32, 33 and 34, respectively. Then, separate power supply lines 31a, 31b, 31c
Via the power supply voltage through the analog circuit region 32,
33, 34, also separate ground lines 35
a, 35b, 35c through the analog circuit area 32,
33 and 34 will be grounded respectively. As described above, by using the power supply wiring lines such as the power supply line or the ground line for each analog circuit area, the avoidance measure against the inconvenience that the analog circuits influence each other through the common power supply wiring line Is taken.

[0006]

As described above, in the conventional analog / digital coexistence IC, the power supply voltage region, the plurality of analog circuit regions and the ground region are located between the digital circuit and the cut side of the IC chip. In the same manner as the digital circuit, they are arranged in a line. Then, the power supply voltage / grounding region and each analog circuit region are partially connected by separate power supply wiring lines that run in parallel. The width of the power supply wiring line for such an analog circuit is sufficiently wide from the viewpoint of measures against noise and the like. Therefore, in a place where a plurality of power supply wiring lines are parallel to each other near the power supply voltage / grounding area, the width required for all the power supply wiring lines is considerably wide. On the other hand, the wiring line for power supply is not arranged in the analog circuit area farthest from the power supply voltage / ground area (see 30a and 30b in FIG. 2).

Therefore, the width of the entire analog circuit area is required to be considerably wider than the width of each block of the analog circuit area, and a free area is formed in a part thereof. However, the empty area formed in the corner of the analog circuit area has a distorted shape, and it is difficult to arrange an existing library cell. In addition, since the adverse effect of noise or the like on the analog circuit is too great to connect the digital signal line across the analog circuit, even a small-scale digital circuit should be arranged in such a manner. Is not desirable.

Therefore, it is extremely difficult to effectively use the empty area formed in the analog circuit area. In this case, the size of the IC chip is correspondingly increased due to the useless empty area,
This is inconvenient because the yield of the product decreases. An object of the present invention is to solve such a problem of the prior art, and to realize an analog / digital coexistence IC having a structure capable of reducing a wasteful empty area.

[0009]

The structure of the analog / digital coexistence IC of the present invention which achieves the above object is the same as the analog / digital coexistence IC in which an analog circuit and a digital circuit coexist on the same chip. The circuit includes a first reference potential region placed at one reference potential of the power supply voltage, a second reference potential region placed at the other reference potential of the power supply voltage, and the first reference potential region. From one of the reference potentials via the first power supply wiring line and from the second reference voltage region via the second power supply wiring line to the other reference potential. A first analog circuit region which is supplied with a voltage and which is formed of a substantially quadrilateral region, and a third power supply region which has substantially the same width as the second power supply wiring line from the first reference potential region. The one reference potential is transmitted through a line and the other reference potential is transmitted from the second reference potential region through a fourth power supply wiring line to receive the supply of the power supply voltage. A second analog circuit region formed of a substantially quadrilateral region having substantially the same shape as the quadrangle, the first reference potential region, the first analog circuit region, and the second analog circuit. Region and the second reference potential region are sequentially arranged along one side of the chip in a staggered manner around the periphery, and the second and third power supply wirings are arranged in correspondence with the displaced region. The lines are wired in a straight line, and the digital circuit is provided inside the chip.

Specifically, the above analog circuit is provided,
The digital circuit is provided inside the chip, and the first reference potential region, the first analog circuit region, the second analog circuit region, and the second reference potential region, Between one side of the chip and a region including the digital circuit are sequentially arranged along the one side around the periphery,
The third power supply wiring line is disposed between the first analog circuit region and the digital circuit, and the second power supply wiring line is the first analog circuit region and the one side of the chip. Is disposed between the second analog circuit region and the second analog circuit region by a distance substantially corresponding to the width of the second power source wiring line or the third power source wiring line. The first analog circuit region is arranged on the one side of the chip in a shifted manner,
(Or, the third power supply wiring line is disposed between the first analog circuit area and the one side of the chip, and the second power supply wiring line is the first analog circuit area. The chip is disposed between the second analog circuit area and the digital circuit, and the chip is disposed with respect to the second analog circuit area by a distance substantially corresponding to the width of the second power supply wiring line or the third power supply wiring line. The first analog circuit region is displaced from the one side to the digital circuit side, and the third power supply wiring line and the second power supply wiring line are substantially linear. .

[0011]

In the analog / digital coexistence IC of the present invention having such a structure, the plurality of analog circuit regions are displaced from each other by a distance substantially corresponding to the width of the power supply wiring line such as the power supply line or the ground line. It is arranged in a staircase.
As a result, a linear region substantially corresponding to the width of the power supply wiring line remains on the shifted and vacant side of the analog circuit region before the power supply wiring line is arranged. When the number of analog circuit areas is large, a stepwise area remains. Therefore,
Power supply wiring lines can be arranged linearly in this region. Even when the number of analog circuit regions is large, the individual power supply wiring lines can be arranged linearly by arranging them in parallel so as to form a staircase as a whole. This makes the first
The area for the reference potential, the area for the plurality of analog circuits, the area for the second reference potential, and the area for adding the wiring line for the power supply, that is, the area for the group of analog circuits is set in a substantially quadrilateral area. Can be arranged closely.
Therefore, even in the case of coexistence with a digital circuit based on a quadrilateral block-shaped region arrangement, the analog circuit can be arranged without waste.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a layout of an embodiment of an analog / digital coexistence IC of the present invention. Here, 100 is an IC chip, 200 is a digital area in which digital circuits such as MPU and memory are arranged, and 300 is an area for analog circuits in which analog circuits such as A / D conversion circuits that handle analog signals are arranged. In this example, the analog circuit area 300 is arranged so as to surround three sides of the digital area 200 in the peripheral portion of the IC chip 100. Also,
Reference numeral 31 is a power supply voltage region including pads to which power supply voltage is supplied (corresponding to a first potential region), and 32 is an analog circuit region (first analog circuit region) allocated to one I / O function. 33 corresponds to another I / O.
Analog circuit area assigned to the function (second
Corresponding to the analog circuit area), and 34 is another I /
An analog circuit area assigned to the O function (illustration in the case of a large number of analog circuit areas), 35 is a ground area including a pad to be grounded (corresponding to a second potential area)
Is.

In the layout design of this IC, the digital area 2 in which the area is blocked for each library cell is used.
Following the design in 00, the analog circuit area 300
Has been designed, for example in the digital domain 200 and I
Areas 31, 32, ..., 3 between the lower side of the C chip 100
5 are arranged. Of these, the analog circuit area 32
Receives the power supply voltage from the power supply voltage region 31 via the power supply line 310a and is grounded to the grounding region 35 via the ground line 350a. As a result, the power is supplied to operate as, for example, an A / D conversion circuit. Further, the shape is a block and has a rectangular shape.

The analog circuit area 33 receives a power supply voltage from the power supply voltage area 31 via the power supply line 310b and is grounded to the ground area 35 via the ground line 350b. As a result, power is supplied to the D / A
Operates as a conversion circuit. Further, the shape thereof is made into a block and has a rectangular shape almost the same as the analog circuit area 32. Further, the analog circuit area 34 receives the power supply voltage from the power supply voltage area 31 via the power supply line 310c, and is grounded to the ground area 35 via the ground line 350c. As a result, it receives power supply and operates as, for example, a speaker drive circuit. Further, the shape thereof is formed into a block and has a rectangle almost the same as the analog circuit regions 32 and 33.

Then, these analog circuit regions 3 are provided.
A power supply voltage region 31 and a grounding region 35 are arranged on the left and right sides of 2, 33, 34, and between the digital region 200 and the lower side of the IC chip 100, along the lower side, the power supply voltage region 31, the analog region. The circuit area 32, the analog circuit area 33, the analog circuit area 34, and the ground area 35 are
They are arranged in order. At this time, the power supply lines 310b, 31
0c is analog circuit areas 32 and 33 and digital area 2
And the ground lines 350b and 350c.
Are arranged between the analog circuit regions 33 and 34 and the lower side of the IC chip 100. Further, in accordance with this, the distance I corresponding to the width of the power supply line 310b or the like from the digital circuit 200 side with respect to the analog circuit area 33 is I.
The analog circuit area 32 is arranged on the lower side of the C chip 100 with a shift. Similarly, the ICs from the digital circuit 200 side with respect to the analog circuit area 34 are almost the same distance apart.
The analog circuit region 33 is arranged on the lower side of the chip 100 with a shift.

By arranging the analog circuit regions 32, 33, 34 in this order in correspondence with the width of the power supply line in this manner, the power supply voltage region 31, the analog circuit regions 32, 33, 34, and the digital circuits are arranged. The area surrounded by the area 200 is a stepwise area having a step corresponding to the width of the power supply line. Moreover, the analog circuit regions 32, 33, and 34 are arranged in order on the stepped portion, and the power supply voltage region 31 is located at the opposite position. Therefore, the power supply line 310b
Can linearly connect the power supply voltage region 31 and the analog circuit region 33 in the stepwise region. Further, the power supply line 310c can also linearly connect the power supply voltage region 31 and the analog circuit region 34 in this stepwise region. In addition, as a result, the staircase-shaped region is provided with the power supply lines 310b and 310c.
Uses all the area.

Similarly, analog circuit areas 32, 33, 3
By arranging 4 in order, the grounding area 35
And analog circuit areas 32, 33, 34 and IC chip 1
The area surrounded by the lower side of 00 is also a stepwise area having a step corresponding to the width of the ground line. Moreover, similarly, the analog circuit regions 32, 33,
34 are arranged, and the power supply voltage region 35 is located at the opposite position.
Therefore, the ground line 350b can linearly connect the grounding region 35 and the analog circuit region 33 in the stepped region. Further, the ground line 350
Also in a, the ground region 35 and the analog circuit region 32 can be linearly connected in this stepwise region. Moreover, as a result, this stepwise region is entirely used by the ground lines 310b and 310a.

As described above, the analog circuit regions 32 and 3 are provided.
3 and 34 are offset from each other and the power line 3 is provided in the empty area.
By arranging 10b, 310c and the ground lines 350a, 350b, the power supply voltage region 31, the analog circuit regions 32, 33, 34, the grounding region 35, and the power supply lines 310a, 310b, 310c, the ground line 35.
A region including 0a, 350b, and 350c, that is, a region for a group of analog circuits can be densely arranged in a substantially quadrilateral region. Therefore, even when the analog circuit coexists with the digital circuit based on the quadrilateral block-shaped region arrangement,
It is possible to arrange the analog circuit without waste.

As described above, the power supply lines 310b and 310c are arranged between the analog circuit areas 32 and 33 and the digital area 200, and the ground lines 350a and 350b are connected between the analog circuit areas 33 and 34 and the lower side of the IC chip 100. Although an example in which the power supply lines 310b and 310c are arranged between the analog circuit region 3 and the analog circuit region 3 has been described in detail.
2 and 33 and the lower side of the IC chip 100 and ground lines 350a and 350b between the analog circuit regions 33 and 34 and the digital region 200, the analog circuit regions 32 and 33 are provided. , 34 are only opposite to each other in the direction in which they are displaced from each other, and the effect thereof is exactly the same as that of the above-described example.

[0020]

As can be understood from the above description, according to the present invention, the analog circuit area is arranged in a line between the power supply voltage area and the ground area between one side of the IC chip and the digital area. Are arranged to be offset from each other corresponding to the width of the power supply wiring line. Then, in the area formed by this deviation, the power supply wiring line extending from the power supply voltage area or the ground area to the analog circuit area is linearly arranged. As a result, even when an analog circuit coexists with a digital circuit based on a quadrilateral block area arrangement, a group of analog circuits can be densely arranged in the quadrilateral area. it can. Moreover, the requirement peculiar to the analog circuit that the power supply lines are arranged separately for the respective analog circuit regions to eliminate the influence of noise will not be impaired. Therefore, the difficult-to-use area that was conventionally present in the corner of the analog circuit area is eliminated, and the useless empty area is reduced. As a result, as long as the functions are the same, the area for analog circuits can be reduced, and the size of the IC chip can be reduced accordingly, so that the yield of ICs can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing an analog / digital coexistence I of the present invention.
It is a layout explanatory drawing about one Example of C.

FIG. 2 is a layout explanatory diagram of a conventional analog / digital coexistence IC.

[Explanation of symbols]

 10 IC chip 20 Digital area 30 Analog circuit area 30a, 30b Free area 31 Power supply voltage area 31a, 31b, 31c Power supply line 32, 33, 34 Analog circuit area 35 Grounding area 35a, 35b, 35c Ground line 100 IC Chip 200 Digital area 300 Analog circuit area 310a, 310b, 310c Power supply line 350a, 350b, 350c Ground line

Claims (1)

[Claims] 1. An analog / digital coexistence IC in which an analog circuit and a digital circuit coexist on the same chip, wherein the analog circuit includes a first reference potential region placed at one reference potential of a power supply voltage, and The second reference potential region placed at the other reference potential of the power supply voltage, and the one reference potential transmitted from the first reference potential region via the first power supply wiring line. The first analog circuit region, which is formed of a substantially quadrilateral region, is supplied with the power supply voltage by transmitting the other reference potential from the reference voltage region through the second power supply wiring line, and the first analog circuit region. One of the reference potentials is transmitted from the first reference potential region through the third power supply wiring line having substantially the same width as the second power supply wiring line, and the second reference potential region is changed to the fourth reference potential. Power distribution A second quadrangular region that is supplied with the power supply voltage by transmitting the other reference potential through a line and has a substantially quadrilateral shape that is substantially the same shape as the quadrilateral.
An analog circuit area, the first reference potential area, the first analog circuit area, the second analog circuit area, and the second reference potential area are the chips. Are arranged in a staggered manner in the periphery along one side, and the second and third power supply wiring lines are arranged in a straight line in correspondence with the displaced area.
An analog / digital coexistence IC, wherein the digital circuit is provided inside the chip.