JPH04303961A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To achieve timing matching between signals caused by the capacitance of the wiring connecting between a RAM portion and a RAM connection logic circuit portion which operate with the same clock easily. CONSTITUTION:RAM portions 3a-3b, RAM logic circuit portion one-piece blocks 3-7 including these RAM portions and RAM connection logic circuit portions 3b-7b which operate with the same clock, a clock driver portion 8, a logic circuit portion 9 forming a block region including the logic circuit portion only, and a wiring region 10 which connects between these block regions are provided on a semiconductor chip 1.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to semiconductor integrated circuits.
In particular, it relates to standard cell type semiconductor integrated circuits.

0002

2. Description of the Related Art In conventional semiconductor integrated circuits of this type, a RAM section and a logic circuit section are generally arranged as separate blocks. For example, as shown in FIG. 3, a conventional semiconductor chip 11 has a plurality of external pads 1.
2, RAM sections 13 to 17, and clock driver section 1
8, a logic circuit section 19, and an inter-block wiring region 20 that connects each of these block regions, RAM sections 13 to 17, and a clock driver section 18.
and the logic circuit section 19 are individually arranged as separate blocks. Therefore, a RAM connection logic circuit section (not shown), which operates with the same clock as the RAM sections 13 to 17 and functions to input its output to the RAM sections 13 to 17, is located within the logic circuit section 19. The signals output from the RAM connection logic circuit are connected to the RAM sections 13 to 17 via signal wiring laid in the inter-block wiring area 20.

0003

[Problems to be Solved by the Invention] In the above-mentioned conventional semiconductor integrated circuit, since the RAM section and the logic circuit section are arranged as separate blocks, there is a gap between the RAM section and the RAM connection logic circuit section in the logic circuit section. The connections are made by a plurality of signal wirings, but variations occur in the lengths of these signal wirings. Therefore, there is a drawback that the amount of delay in each signal varies greatly due to the wiring capacitance, and it becomes difficult to match the timing between the signals.

0004

Means for Solving the Problems The semiconductor integrated circuit of the present invention is a standard semiconductor integrated circuit formed on a semiconductor chip and including at least a RAM section and a logic circuit section. at least one or more block areas formed by integrating a RAM connection logic circuit section and a RAM connection logic circuit section operating at the same clock; a block area formed only by the logic circuit section; and a block area between the block areas. A wiring area for connecting wires is provided on a semiconductor chip.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a semiconductor chip layout diagram showing one embodiment of the present invention. As shown in FIG. 1, the semiconductor chip 1 of this embodiment includes a plurality of external pads 2, RAM sections 3a to 7a, and a RAM connection logic circuit section 3b.
7b, a clock driver section 8, a logic circuit section 9, and an inter-block wiring section 10.

That is, as shown in FIG.
The connection logic circuit units 3b to 7b each have a corresponding RAM.
It is included inside the integrated blocks 3 to 7 and is arranged in close contact with the corresponding RAM sections 3a to 7a. FIG. 2 shows, as an example, R in FIG.
It is an explanatory diagram showing the wiring relationship inside the AM/logic circuit integrated block 3, and shows the RAM section 3a and the RAM connection that sends its output to the RAM section 3a via the RAM/RAM connection logic circuit wiring 3c. A mutual connection diagram between the logic circuit section 3b and the logic circuit section 3b is shown.

As shown in FIG. 2, the RAM section 3a and R
Mutual connection with AM connection logic circuit section 3b is RAM/RA
This is done with an extremely short wiring length, which is the minimum necessary, via the M-connection logic circuit wiring 3c, and variations in the amount of delay in each signal due to wiring capacitance are completely suppressed. This is exactly the same for the other RAM/logic circuit paired blocks 4 to 7. Therefore, the problem of matching the timing between each signal that occurs due to the connection between the RAM sections 3a to 7a operating with the same clock and the corresponding RAM connection logic circuit sections 3b to 7b is eliminated. .

[0009]

Effects of the Invention As explained above, in the present invention, a RAM section that operates with the same clock and a RAM connection logic circuit section are configured as an integrated block, and are arranged within the same rectangular area on a semiconductor chip. By arranging the wiring between the RAM section and the RAM connection logic circuit section, it is possible to set the wiring length between the plurality of RAMs and RAM connection logic circuits to the necessary minimum length. This has the advantage that it is possible to eliminate the resulting variation in the amount of delay in each signal, making it easier to adjust the timing between the signals.

[Brief explanation of drawings]

FIG. 1 is a layout diagram of a semiconductor chip showing an embodiment of the present invention.

FIG. 2 is a diagram showing internal connections of a RAM/logic circuit integrated block in this embodiment.

FIG. 3 is a layout diagram of a semiconductor chip showing a conventional example.

[Explanation of symbols]

1, 11 Semiconductor chips 2, 12 External pads 3-7 RAM/logic circuit integrated block 3a-
7a, 13-17 RAM section 3b-7b
RAM connection logic circuit section 3c RAM/RAM connection logic circuit wiring 8, 18 Clock driver section 9
, 19 Logic circuit section 10 Inter-block wiring section 20 Inter-block wiring area

Claims (1)

[Claims] Claim 1: At least a RAM on a semiconductor chip.
In a standard semiconductor integrated circuit formed including a section and a logic circuit section, at least A semiconductor integrated circuit comprising, on a semiconductor chip, one or more block regions, a block region formed only by the logic circuit section, and a wiring region connecting the block regions.