JPH01152744A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To allow high speed access by classifying logic circuits which exchange signals with a centering memory circuit in accordance with the kinds of signals and arranging the logic circuits so that each signal transmitting path may be shortest. CONSTITUTION:Signals from address signal terminals fitted to the upper section of an LSI are transmitted over a RAM1A, a RAM1B and a RAM2A, a RAM2B through input circuits INC1-INC3 and selectors SEL1, SEL2. Reading signals from the RAM1A and the RAM1B are sent from an output terminal OUT1 disposed on the left side of the LSI, and reading signals from the RAM2A and the RAM2B are sent from an output terminal OUT2 arranged on the right side of the LSI. A write signal path is shaped through an input circuit INC4 set up on the lower side in the LSI. Accordingly, the signal transmission paths of each signal can be optimized at the shortest distance, thus allowing the increase of the working speed of a RAM access.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, such as a fully custom semiconductor device consisting of a RAM (Random Access Memory) and a logic circuit that controls it. The present invention relates to techniques effective for use in integrated circuit devices.

[Conventional technology]

As a semiconductor integrated circuit device with a built-in RAM in a gate array, for example, Nikkei McGraw-Hill, June 3, 1985, r Nikkei Electronics, Na370, pp.
There is 151-1.77.

[Problem that the invention seeks to solve]

In the semiconductor integrated circuit device in which the gate array has a built-in RAM, the logic section consisting of the gate array is placed in the center of the chip for the versatility of the gate array, and the R
AM is placed.

The central processing unit (CPU) in a general-purpose large computer
) Ultra-high-speed memory (buffer storage, control storage) used in the periphery of computers, vector registers in supercomputers, etc., have high-speed access, which has great significance in improving system performance. In conventional ultra-high-speed memories, the RAM and the logic circuit that controls it are constructed from separate semiconductor integrated circuit devices. There is a limit to speeding up due to delays. Therefore, it is conceivable to use a semiconductor integrated circuit device consisting of a logic circuit consisting of a gate array and a RAM as described above. However, in the above-mentioned semiconductor integrated circuit device, no consideration has been given to increasing the speed.
The RAM section and the logic section are simply arranged separately for the sake of versatility and high integration. In such a configuration, as a result of the relatively long wiring path between the RAM section and the logic section, high speed cannot be achieved due to signal propagation delay time within the semiconductor integrated circuit.

An object of the present invention is to provide a semiconductor integrated circuit device that achieves high-speed RAM access.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, a logic circuit that sends and receives signals to and from a memory circuit with a storage capacity of multiple bits is divided into sections according to the type of signal, and the logic circuits are arranged so that the signal transmission path is the shortest distance. .

[For production]

According to the above-mentioned means, the signal transmission path can be minimized and the signal propagation delay time therein can be reduced, so that high-speed access to the RAM is possible.

[Embodiment 1] FIG. 1 shows a block diagram of an embodiment in which the present invention is applied to a vector register used in a supercomputer or the like.

In the figure, a portion surrounded by a broken line constitutes one semiconductor integrated circuit device LSI, and is formed on a single semiconductor substrate such as single crystal silicon by known semiconductor integrated circuit manufacturing technology, but is not particularly limited. is formed in Each circuit block in the figure is drawn in accordance with the actual geometric arrangement in a semiconductor integrated circuit device.

In this embodiment, the function as a register is realized by RAM. RAM is RAMIA, RAMIB and RAM
It is composed of a total of four RAMs, consisting of two sets of RAM 2A and RAM 2B. RAMIA and R constituting one set above
RAM2A and RAM2B forming AMIB and other groups
are arranged symmetrically. RAM of each set
IA and RAMIB and RAM2A and RAM2B are arranged side by side in the vertical direction. Therefore, RAMIA and IB are
An address input terminal is placed on the right side of the block, and R
AM2A and RAM2B, on the contrary, have address input terminals arranged on the left side of the block. Therefore, the address signal lines are arranged to extend vertically in the central portion between the two sets of RAMs. An address signal is commonly supplied to the RAMIA and RAMIB from the selector SRL L to the address signal line corresponding to the one set of RAMIA and RAMIB.

The address signal lines corresponding to the other set of RAM2A and RAM2B are connected to the address signal lines from the selector 5EL2 to the RAM2A and RAM2B.
An address signal is commonly supplied to RAM 2A and RAM 2B. Therefore, Seletaku 5ELL and 5EL2 have the above R
It is placed symmetrically above AMIA and 2A.

The selector SEL 1 has 2 arranged above it.
Address signals are supplied from two input circuits lNC1 and lNC2. The selector 5EL2 is supplied with address signals from two input circuits lNC2 and lNC5 arranged in the same manner as described above. Therefore, the above two selectors SEL
An input circuit TNC2 that commonly supplies an address signal to 1 and 5EL2 is arranged between input circuits 1NC1 and 1NC5, and input circuits 1NC1 and 1NC5 are arranged between input circuits 1NC1 and 5EL2.
The selectors SEL 2 and 5EL2 are arranged symmetrically with respect to the arrangement of the selectors SEL 1 and 5EL2.

The input circuit INCl receives an input signal INI from an external terminal of the semiconductor integrated circuit device LSI provided above.
An address signal A1 is supplied. This address signal A1 is used as an address signal RAD for reading RAMIA and RAMIB. The input circuit lNC2 receives an address signal A2 as an input signal IN2 from an external terminal of the semiconductor integrated circuit device LSI provided above.
is supplied. This address signal A2 is used as an address signal WAD for writing into RAMIA, RAMIB, RAM2A, and RAM2B. The input circuit 1NCl receives an address signal A as an input signal IN3 from an external terminal of the semiconductor integrated circuit device LSI provided above.
3 is supplied.

This address signal A3 is used as an address signal RAD for reading from RAM2A and RAM2B.

An output selector 5ELO1 is provided on the left side of the RAMIA and RAMIB arranged on the left side of the semiconductor integrated circuit device LSI as described above. Output selector 5ELOI
is RAMIA or RAM by a control signal (not shown).
The IB read signal is sent to an external terminal 0UTI provided on the left side of the semiconductor integrated circuit device LSI. The above-mentioned R is arranged on the right side of the semiconductor integrated circuit device LSI as described above.
On the right side of AM2A and RAM2B is the output selector 5EL.
O2 is provided. Output selector 5ELO2 sends out a read signal from RAM2A or RAM2B to external terminal 0UT2 provided on the right side of semiconductor integrated circuit device LSI in response to a control signal (not shown).

An input circuit 1NC4 is arranged below the semiconductor integrated circuit device LSI below the RAMIB and RAM2B. This input circuit lNC4 receives a write input signal IN4 provided below the semiconductor integrated circuit device LSI, and sends the write signal to the RAMI.
B, RAMIA, RAM2B, and RAM2A.

As mentioned above, the write address signal is sent to the selector 5.
EL1 and 5EL2 supply RAMIA, RAMIB or RAM2A, RAM2B, so the write operation is performed by two sets of RAMIA, RAMIB or RAM2A.
, is selectively performed for RAM2B. On the other hand, the address signal for reading is
, RAMIB, or RAM2A and RAM2B, it is possible to read the two sets of RAMs as described above selectively or simultaneously.

Also, two RAMIA and RAM in each group
The read signals of IB and RAM2A and RAM2B are selectively outputted by output selectors 5ELOI and 5ELO2. By accessing a total of four RAMs in this way, vector calculations and the like can be performed at high speed. The operating mode itself for vector calculation is not directly related to the present invention, and the function of the vector register itself is
Since it is well known in supercomputers and the like, detailed explanation thereof will be omitted.

In the semiconductor integrated circuit device LSI of this embodiment, the logic circuit is divided as described above, centering on the RAM, depending on the type of signal supplied thereto.

Among the above-mentioned signals, the logic circuit that propagates the address signal transmits the output signals of the input circuits lNC1 to lNC5 that receive the read address signal and the write address signal, and the input circuits lNCl to IN'C3. selector 5ELI, 5 which receives the message and transmits it to the above two sets of RAMs;
It is divided into EL2 and arranged so that the signal propagation path including the external terminals INI to IN3 corresponding to each signal and reaching the two sets of RAMs is the shortest. That is, signals from address signal terminals provided at the top of the semiconductor integrated circuit device LSI are transmitted from top to bottom to input circuits lNCl to lNC5 and selectors 5EL1.5EL.
2 via RAMIA, , RAMIB and RAM2A,
It is transmitted to RAM2B.

In this case, two sets of RAMIA, RAMIB and RAM2A
, RAM2B are arranged symmetrically, so the address signal line is arranged so as to run through the center of the two sets of RAMs.

As a result, the read signal terminal of 2Mi RAM is
RAMIA and RAM I placed on the left side as shown above
RAM2A and RAM2 are placed on the left side of B and on the right side.
Output selectors 5EL01 and 5ELO are on the right side of B, respectively.
2 is placed. Therefore, RAMIA and RAMIB
The read signal from the RA is sent out from the output terminal 0UTI arranged on the left side of the semiconductor integrated circuit device LsT.
The read signals from M2A and RAM2B are sent to the output terminal 0UT located on the right side of the semiconductor integrated circuit device LSI.
Sent from 2. Therefore, the read signal path from the RAM can also be made the shortest.

Further, since the write signal path to the RAM can be made via the input circuit lNC4 provided under the semiconductor integrated circuit bag WLSI, the write signal path to the RAM can be made as short as possible in the same manner as described above. can.

As described above, by dividing the logic circuit that accesses the RAM according to the type of signal to be transmitted, and optimizing the arrangement so that the signal propagation path of each signal is the shortest, centering on the RAM. , it is possible to speed up RAM access.

[Embodiment 2] FIG. 2 shows a block diagram of an embodiment in which the present invention is applied to a pamphlet storage used in a general-purpose large-sized computer or the like.

In the same figure, the part surrounded by the broken line constitutes one semiconductor integrated circuit device LSI as described above, and is made of one piece of material such as single crystal silicon, although it is not particularly limited by known semiconductor integrated circuit manufacturing technology. Formed on a semiconductor substrate. Each circuit block in the figure is drawn in accordance with the actual geometric arrangement in a semiconductor integrated circuit device.

Logic circuits LOGA and LOGB are semiconductor integrated circuit device L.
They are arranged vertically in the center of the SI. logic circuit L
The OGA receives write data D and the like from an input terminal INI provided at the top of the semiconductor integrated circuit device LSI, and supplies write data and control signals to the RAMI and RAM3 arranged on the left and right sides of the OGA. The control signals include a selection signal CS for selecting RAM1 or RAM3, a control signal WE for instructing write/read operations, and the like. A substantial address signal for instructing selection of the RAMI or RAM3 is supplied together with the control signal. The logic circuit LOGB is supplied with write data and control signals similar to those described above through the logic circuit LOGA. RAM2 and RAM4 are arranged on the left and right sides of the logic circuit LOGB, and are supplied with write data and control signals in the same manner as described above. As mentioned above, the logic circuit LOGA
The address signal line that supplies address signals to RAM3 and RAM4 is divided into the logic circuit LOGB and the logic circuit LOGB.
This is because the center of the semiconductor integrated circuit device is arranged to extend in the lateral direction.

Although the address signal AD is not particularly limited, the address signal is supplied via an external terminal arranged at the center left side of the semiconductor integrated circuit device LSI.

For this reason, although not shown, an address buffer is provided if necessary. If it is difficult to create a space for arranging an address buffer on the semiconductor chip on the left side because the number of bits of the address signal is relatively large, the address signal may be divided into two and the semiconductor integrated circuit device LSI It is very good to place the address terminals and address signal lines in the center of both the left and right sides. The address input terminals of the RAM, which are distributed vertically around the wiring area where the address signal line is provided, are arranged vertically symmetrically. In other words, RAMI and RAM3 located on the upper side
In this case, address input terminals are arranged below the circuit block, and address signal lines arranged laterally in the lower area extend upward and are respectively connected to the corresponding address input terminals. Conversely, RAM2 and RAM4 arranged on the lower side have address input terminals arranged on the upper side of the circuit block, and address signal lines arranged upward in the upper area extend downward, respectively. Connected to the corresponding address input terminal.

In the above configuration in which RAMI, RAM3, RAM2, and RAM4 are arranged on the left and right with the logic circuits LOGA and LOCB as the center, the signal terminals of the corresponding RAMI and RAM3 and RAM2 and RAM4 are arranged symmetrically. .

That is, for RAMI and RAM2 on the left side, the data input terminal and the above-mentioned control input terminal are placed on the right side of the circuit block, 1 is placed on RAM3 and RAM4 on the right side, and 1 is placed on the left side of the circuit block, contrary to the above case. A data input terminal and the control input terminal are arranged. Also, RAMI and RAM2 on the left side have data output terminals placed on the left side of their circuit blocks, and RAM3 and RAM4 on the right side have data output terminals placed on the right side of their circuit blocks, contrary to the above case. Ru.

In the left RAMI and RAM2, a data output terminal is arranged on the left side of the circuit block, and correspondingly output logic circuits LOGC1 and LOGC2 are provided. On the left side of the output logic circuits LOGC1 and LOGC2, in other words, on the left side of the semiconductor integrated circuit device LsI, there are data output terminals 0U divided into upper and lower parts and corresponding to each other.
TI (DI) and 0UT2 (D2) are provided. Contrary to the above case, RAM3 and RAM4 on the right side have data output terminals arranged on the right side of their circuit blocks, and output logic circuits LOGC3 and LOGC4 are provided correspondingly. On the right side of the output logic circuit, 0GC3 and LOGG4, in other words, on the right side of the semiconductor integrated circuit device LSI, there are data output terminals 0UT3 (D3) and 01JT4 which are divided into upper and lower parts and correspond to each other.
(D5) is provided.

In this pamphlet storage, logic circuits LOGA and L
OGB generates a selection signal (block select) for selecting each RAM using input signal INI, and one R
AM is selected and an instruction is given to write or read data supplied from the input signal INI to the address specified by the address signal AD.

Output logic circuits LOGC1 to LOGC1 to 1,0GC4 provided corresponding to RAMI to RAM4 output data read from a specified address of the corresponding RAMI to RAM4 or the input signal I, although this is not particularly limited.
Selectively outputs any of the write data supplied from NI. In order to provide such a function, the write data output from the logic circuits LOGA and LOGB is passed through the signal line running through each RAMI or RAM4 or the wiring area where the address signal in the central part is formed, and then sent to each output logic. It is transmitted to circuits LOGCI to LOGC4.

In the buffer storage of this embodiment as well, the logic circuits are divided as described above, centering on the RAM, depending on the type of signal supplied thereto.

Among the above signals, the address signal is propagated by an address signal line running horizontally through the center of the semiconductor integrated circuit device, and the RAMs are distributed above and below this line. Further, the control signal and the write data are supplied from the upper center of the semiconductor integrated circuit device LSI, and corresponding logic circuits LOGA and LOGB are arranged vertically and divided. And the respective logic circuits LOGA and LOGB
By arranging the RAM on the left and right sides with
Write data and control signals from NI are sent to each logic circuit LO.
It is transmitted to RAM4 without RAMI via GA and LOGB with the shortest distance.

As mentioned above, the readout signal terminals of the RAM are arranged on the left side of RAMI and RAM2 arranged on the left side, and on the right side of RAM3 and RAM4 arranged on the right side, respectively, so the readout signal terminals of the RAM are The signal path can also be minimized.

As described above, by dividing the logic circuit that accesses the RAM according to the type of signal to be transmitted, and optimizing the arrangement so that the signal propagation path of each signal is the shortest, centering on the RAM. , it is possible to speed up RAM access.

[Embodiment 3] FIG. 3 is a block diagram of an embodiment generally showing the optimum arrangement of logic circuits with respect to a RAM built in a semiconductor integrated circuit device.

For example, on the left side of the circuit block that makes up the RAM, there is an address input terminal (terminal should be understood to mean an address input signal line, not a geometric terminal provided on a semiconductor chip; the same applies hereafter). ) is placed, a logic circuit LOG that supplies an address signal there
1 is correspondingly arranged as one independent circuit block. If the data input terminal DI is arranged below the circuit block constituting the RAM, the logic circuit LOG2 that generates the write data will correspond to 1
arranged as two independent circuit blocks. Further, if the data output terminal DO is arranged on the right side of the circuit block constituting the RAM, the logic circuit LOG3 for outputting read data is correspondingly arranged as one independent circuit block. In this way, each circuit block is divided according to the signal line serving as the terminal of the RAM, and each circuit block is arranged with the shortest distance therebetween. This makes it possible to minimize the signal propagation distance required for RAM access, thereby realizing high-speed RAM access.

[Embodiment 4] FIG. 4 shows a circuit diagram of an embodiment of a logic circuit constituting a logic circuit. FIG. 5 shows the equivalent logic circuit diagram. In this embodiment, a series gate based on an ECL gate circuit is used to achieve high integration and high speed of the logic section. That is, three reference voltages, such as Vbbl to Vbb3, whose levels are shifted by one reference voltage Vbb1 and the forward voltage VIE (VF) of a diode-type transistor or diode, are used to create a logic circuit in series. The transistors constituting the section are differential type transistors Ql, Q2, Q9 . QIO
1 differential type transistors Q3 to Q8 and Qll corresponding to reference voltage Vbb2, and differential type transistors Q12 . It is connected in multiple stages like Q13 and uses wired logic in the output section. In this configuration, the composite logic gate circuit consisting of the logic gate circuits Gl and G4 can be constructed with a small number of elements by using the series gate circuit as described above, and the operating current for performing the logic operation is supplied by the transistor Q14. Since only a constant current is generated, power consumption can also be reduced. Also, like a gate array, an OR (OR) that has only one reference voltage Vbb1L
Compared to the case where the circuit is composed of a combination of gate circuits and NOR gate circuits, the signal transmission path between the respective gates can be shortened, thereby increasing the speed.

[Embodiment 5] FIG. 6 shows a circuit diagram of an embodiment of the above RAM.

Although not particularly limited, the memory cell of this embodiment has a read current I set to a relatively large current value for speeding up.
In order to reduce the decrease in the holding voltage with respect to R, for example, as shown in the specific circuit of one memory cell MC00 as a representative, a driving NPN transistor Ql, whose base and collector are cross-connected to each other, is used. Q2 and a P-channel type load MO3FETM2. Ml and these loads MO3FE
A flip-flop circuit is used that includes clamping Schottky diodes SDI and SD2 provided in parallel with TMI and M2.

In order to cause the load MOSFETs MI and M2 to act as variable resistance elements, their substrate gates, in other words channel (back gate) regions, are coupled to the collectors of the other transistors Ql and Q2.

That is, the load corresponding to transistor Q1 is the load MO3FETM2 coupled to its collector, and its substrate gate is coupled to the collector of transistor Q2. Similarly, the load corresponding to transistor Q2 is a load MO3FETMI coupled to its collector, and its substrate gate is coupled to the collector of transistor Q1. In addition, the above P channel MO3FET MI
M2 is made to operate substantially in a depletion mode by selectively doping P-type impurities, which are of a conductivity type opposite to that of the substrate, in its channel region.

The driving NPN l-transistors Ql and Q2 have a multi-emitter structure, although not particularly limited thereto.

The emitters of one of these transistors Ql and Q2 are shared and connected to a constant current source (not shown) that forms a holding current Ist, which will be described later. The above transistors Ql, Q
The other emitter of 2 is used as the input/output terminal of the memory cell,
They are respectively connected to a pair of complementary data lines (bit lines or digit lines) Do, shown as a representative.

Note that the drive NPN transistors Q1 and Q2 may each be configured by two transistors whose bases and collectors are commonly connected.

Load MOS FET M1 constituting the above memory cell,
M2 gate source and Schottky diode SDI
, SD2 are commonly connected to a word line WO, which is shown as a representative. Centering on the memory cell shown as a representative above, similar n+1 memory cells are arranged in horizontal rows (in the figure, only one memory cell MC0n is shown in the black box). , connected to the word line WO. A holding current line corresponding to the word line WO is provided in this horizontal row, and drive transistors (Ql, Ql,
Q2, etc.) are commonly connected.

Other rows (word lines W m ) similarly shown as representatives
Similarly to the above, memory cells MCm0 to MCm
n is connected. Also, in the vertical column, m+1 similar to the above
memory cells are arranged, and their input/output terminals are commonly connected to complementary data lines Do, DO. A memory array M-ARY is formed by arranging (n+1)×(m+1) memory cells in a matrix in one row and one column.

In the information retention state of the memory cell configured as described above, the memory cell has a small retention current 1st. For example, if transistor Q1 is on and transistor Q2 is off, the collector retention voltage vC1 of transistor Q1 is at a low level, and the collector retention voltage vC1 of transistor Q2 is at a low level. Collector holding voltage VC of
2 is a high level. By supplying the high level of the holding voltage VC2 to the back gate as a back bias voltage, in other words, the potential of the source to the back gate becomes VQ, so that the MO3F
ETM2 is turned off and has a relatively large resistance value. As a result, the low level of the holding voltage vC1 at the collector of the transistor Q1 is determined by the voltage drop caused by the minute current Ist flowing through the transistor Q1 in the MOSFET M2, which has a relatively large resistance value. Note that when this voltage drop becomes larger than the forward voltage of the Schottky diode SDI, the Schottky diode SDI is turned on and its level is clamped. On the other hand, MOSFETMI is
It is turned on by supplying a low-level back bias voltage to the source, and transmits a high level according to the potential Vx of the word line to the collector of the transistor Q1.

This is the same when a relatively large read current IR is applied, and even if a relatively large base current corresponding to the read current IR flows through the MOSFET MI, its resistance value is made relatively small. As a result, the drop in the high level of the holding voltage VC2 can be reduced. As a result, the holding voltage of the memory cell ■C1
The DC characteristics of and vC2 make it possible to suppress a drop in the holding voltage VC2 on the high level side to a small level even if the read current IR is increased.

As a result, the read current I with respect to the holding current Ist
Since the ratio of R can be set to a large value of about 3 to 4 digits, it is possible to increase the speed of read and write operations while ensuring low power consumption in the holding state and a desired operating margin. .

The word lines WO and Wm shown as representatives include, although not particularly limited to, emitter follower drive transistors Q5. The selection/non-selection level is determined by Q6. Note that in order to increase the drive capability, these transistors Q5, Q6, etc. are
It may also be composed of two transistors.

Address signals AXO to AXk supplied from appropriate logic circuits (circuit blocks) not shown are transmitted to an X address decoder XDCR. That is, R in this example
In AM, the address buffer is omitted and the address signal is directly supplied from the logic circuit as described above, so high speed is possible. X address decoder XDC
R forms a selection signal for one word line and selects the word line.

The representative complementary data lines DO, DO are connected to transistors Q12 . It is connected via Q13 to a constant current source for reading/writing provided in common to other complementary data lines (not shown). This constant current source includes, but is not particularly limited to, a transistor Q14. Consists of Q15.

Transistor Q12゜Q1 as the above column switch
3 has a Y address decoder YDCR, which will be described later.
output signal is provided. Y address decoder YDCR
The output signal turns on a plurality of sets of transistors as column switches corresponding to the number of read or write bits.

Address signals AYO to AXj supplied from an appropriate logic circuit (circuit block) not shown are transmitted to a Y address decoder YDCR. That is, the RAM of this embodiment
In this case, similarly to the above, the address buffer is omitted and the address signal is directly supplied from the logic circuit as described above, so that high speed operation is possible. As described above, the Y address decoder YDCR turns on a transistor serving as a switch to select a plurality of sets of data lines.

In this embodiment, although not particularly limited, the following bias circuit is provided in order to apply a predetermined bias voltage to the data line when not selected. That is, NPN transistor Q
The collector of ll is coupled to the circuit ground potential. A diode D and a resistor R3 connected in series are provided between the base and collector of the transistor Qll. This series diode D and resistor R3 are connected to a constant current source (Q16.R6) similar to the above through a transistor Q14 similar to the column switch transistor. Although not particularly limited, the transistor Qll has a multi-emitter structure, and a pair of emitters are connected to complementary data lines Do and Do, respectively. In addition, complementary data lines DO, D
O are each coupled to a minute constant current source. That is, a constant voltage VBI is supplied to the base thereof, and the emitters are provided with resistors R1 and R2, respectively. Q8 constantly draws a small constant current to the complementary data lines DO, DO.

As a result, in the unselected complementary data line, the column switch transistor Q14 etc. are in the off state.
Its potential is biased to approximately the sum of the forward voltage of the diode D and the voltage between the base and emitter of the transistor Qll. Note that the complementary data lines Do, D
When o is selected, the transistor Q14 is turned on, so a relatively large current generated by the constant current source flows through the transistor Q14 and into the resistor R3. As a result, the transistor Qll is turned off, so that the complementary data lines DO and DO are set to a potential according to the information stored in the selected memory cell.

For writing/reading of the memory cells in the row shown as a representative, complementary data lines Do, Do have current switching switch transistors Q9 . QI
O is provided. These transistors Q9. The collector output of QIO is transmitted to a pair of inputs of sense amplifier SA. The sense amplifier SA performs its amplification operation, and also outputs its output signal level to the data output sofa DOB.
performs a level conversion operation that matches the input level. The data output circuit DO amplifies the output signal from the sense amplifier SA and sends a read signal to a logic circuit (circuit block) not shown.

The output voltages Vl and V2 of the write circuit WA are applied to the base of the current switching transistor Q9°QIO. Write data formed by a logic circuit (circuit block) not shown is supplied to an input of a data input circuit DI.

This data input circuit DI forms a complementary data signal according to the write data signal and transmits it to the write circuit WA.

A control signal W formed by an appropriate logic circuit (not shown)
E and C3 are supplied to the control circuit C0NT. This control circuit C0NT determines the operation mode from each of the control signals, and according to the operation mode, the data output circuit Do,
Forms internal control signals for write circuit WA.

For example, the data output circuit Do is activated when the signal WE is set to a high level and the signal C8 is set to a low level. At this time, the write circuit WA forms a read reference voltage Vrefc (V 1 , V2) set to an intermediate level of the holding voltage of the selected memory cell, and the write circuit WA forms the read reference voltage Vrefc (V 1 , V2) set to the intermediate level of the holding voltage of the selected memory cell, and the write circuit WA forms the read reference voltage Vrefc (V 1 , V2) set to the intermediate level of the holding voltage of the selected memory cell, and the write circuit WA generates the read reference voltage Vrefc (V 1 , V2) set to the intermediate level of the holding voltage of the selected memory cell. Tell the QIO base. In this operation mode, data output circuit Do receives an amplified signal from sense amplifier SA and forms an output signal.

When the signal C8 is set to low level and the signal WE is set to low level, the write circuit WA writes high level and low level according to the write data signal supplied from the terminal Din through the data input circuit DI which is activated at this time. Forming a signal, the transistor Q9. Tell the QIO base.

The write high level and low level signals (Vl, V2) formed by the write circuit WA are, although not particularly limited, set higher than the high level of the holding voltage of the memory cell in the selected state and lower than the low level of the holding voltage, respectively. Ru. Thereby, the drive transistor of the selected memory cell is switched on/off according to the write signal.

Further, in the RAM non-selection state where the signal C8 is set to high level, the control circuit C0NT sets the selection signal cs to a higher level than the selection signal of the Y address decoder YDCR. This selection signal B is used to inhibit the constant current for writing/reading flowing through the memory cells of the memory array M-ARY when the RAM is in the non-selected state.

That is, although not particularly limited, it is supplied to the bases of transistors Q17 to Q19 that bypass a constant current generated by a constant current source commonly provided for each complementary data line. These transistors Q17 to Q19 are
Its collector is coupled to circuit ground potential. The emitters of these transistors Q17-Q19 are connected to the collectors of transistors Q14-Q16, respectively, which constitute the constant current source. As a result, these transistors Q17 to Q19 become column switch transistors Q
12 to Q14, etc., and the current of the constant current source is made to flow selectively according to the level of the selection signal cs. In the write/read mode in which the signal CS is set to low level, the selection signal τ1 is set to a lower level than the selection signal formed by the Y address decoder YDCR. In the RAM selection state, the level of the selection signal ττ is determined by the Y address decoder YD.
Since the level is set to be lower than the selection signal formed by CR, the transistors Q17 to Q19 are turned off.

The effects obtained from the above examples are as follows. In other words, (1) The logic circuit that sends and receives signals to and from a RAM with a storage capacity of multiple bits (7 bits) is divided into logic circuits according to the type of signal, and the signal transmission path is the shortest distance. By arranging them in this manner, the signal transmission path can be minimized and the signal propagation delay time therein can be reduced, resulting in the effect that high-speed access to the RAM is possible.

(2) By configuring the logic circuit that forms the signal for accessing the RAM in the same semi-wing integrated circuit,
Since there is no need for an input/output cover sofa for the RAM, and the signal propagation delay time that occurs therein is substantially eliminated, in combination with the effect (1) above, it is possible to achieve the effect that even higher speeds can be realized.

(3) The logic circuit that sends and receives signals to and from the RAM, which has a storage capacity of multiple bits, is divided into sections according to the type of signal, and the logic circuits are arranged so that the signal transmission path is the shortest distance. By changing the layout, it is possible to easily increase the speed of the RAM.

(4) By using series gates as the logic section, it is possible to achieve higher speed and higher integration.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples.1. It goes without saying that various changes can be made without departing from the gist of the invention. For example, the division of RAM and the logic circuit arranged around it is
The arrangement is determined depending on how the information is accessed, and various modifications can be made to the arrangement provided that the signal propagation distance is minimized as described above.

Further, the specific configuration of each logic circuit and RAM is other than the one using the ECL configuration as described above.

It may be constructed using a 0M03 circuit or a combination thereof.

The present invention can be widely used in various semiconductor integrated circuit devices including a RAM and a logic circuit for accessing the RAM.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, the logic circuits that send and receive signals to and from the RAM, which has a storage capacity of multiple bits, are divided into sections according to the type of signal, and the logic circuits are arranged so that the signal transmission paths are the shortest distances. As a result, the signal transmission path can be minimized and the signal propagation delay time therein can be reduced, thereby enabling high-speed access to the RAM.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the invention applied to a vector register, FIG. 2 is a block diagram showing an embodiment of the invention applied to buffer storage, and FIG. 3 is a block diagram showing an embodiment of the invention applied to a vector register. , a block diagram for explaining the general arrangement of RAM and its corresponding logic circuit, FIG.
FIG. 5 is a specific circuit diagram showing an embodiment of a logic circuit. FIG. 5 is an equivalent logic circuit diagram thereof. FIG. 6 is a specific circuit diagram showing an embodiment of a RAM. LSI...Semiconductor integrated circuit device, RAMIA. RAMIB, RAM2A, RAM2B, RAM
I~RAM4...Random access memory, lN
Cl~lNC4...Input circuit, 5ELL, 5EL2...
Selector, SEL, 01,5ELO2...Output selector, LOGA, LOGB...Input logic circuit, LOGCI~
LOGC4...Output logic circuit, LOG1~LOG3...
Logic circuit, MCOO~MCmn ・-Memory cell, XD
CR...X address decoder, YDCR...Y address decoder, SA...sense amplifier, WA...write circuit, DO...data output circuit, DI...data input circuit,
C0NT...control circuit

Claims (1)

[Claims] 1. A memory circuit having a storage capacity of multiple bits and a logic circuit that controls the memory circuit, the logic circuit being divided according to the type of signal to be transmitted centering on the memory circuit, and A semiconductor integrated circuit device characterized in that each logic circuit is optimally arranged so that each signal transmission path has the shortest distance. 2. The semiconductor integrated circuit device according to claim 1, wherein the types of signals to be transmitted include address signals, write data, read data, and control signals. 3. The scope of claims characterized in that, among the logic circuits arranged in a divided manner, those that exchange data with external terminals are provided with external terminals close to each other in accordance with the arrangement thereof. A semiconductor integrated circuit device according to item 1 or 2. 4. The semiconductor integrated circuit device according to claim 1, 2, or 3, wherein the semiconductor integrated circuit device is a fully custom semiconductor integrated circuit device.