JPS63312655A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent wiring property from deteriorating, a logic function from decreasing and power consumption from increasing by providing a plurality of unit load capacities in a wiring region adjacent to a logic cell region in which logic cells for forming a logic are arrayed so as not to enhance logic cell available rate. CONSTITUTION:Logic cell regions 2, 3 in which a plurality of logic cells 4 made of two cell transistors 11, 12 are arrayed, wiring regions 6, 7, 8 provided adjacent to the regions 2, 3 distinctly from the logic cell regions, and a unit load capacity 10 formed in parallel with the cells 4 in the regions 6, 7, 8 are contained on a semiconductor substrate 1. With the thus configuration, when a delay time is required for a logic signal in a logic circuit design, the unit load capacities in number required for logic cells 4a to be delayed are connected by a load capacity line 13 to form a predetermined signal delay time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit designed using a gate array method.

[Conventional technology]

In a semiconductor integrated circuit using a conventional gate array method, as shown in FIG. And then #J! Area 5a, 6. ．． 7. This wiring area 5. ．． 6. ．．
7. A signal line 8.9 is formed to connect between the logic cells.

[Problem that the invention seeks to solve]

In the conventional semiconductor integrated circuits mentioned above, logic circuits are constructed by connecting logic cells with signal lines, so if a specific signal requires a delay time due to the logic structure, a special Since it does not have a delay function, the required number of logic cells are inserted and each delay time is used to create a delay time. Therefore, there is a drawback that the usage rate of logic cells is increased, resulting in poor wiring, a decrease in logic function, and an increase in power consumption.

[Means for solving problems]

The semiconductor integrated circuit of the present invention includes a logic cell region in which a plurality of logic cells each composed of a plurality of cell transistors are arranged on a semiconductor substrate, and a wiring region provided adjacent to the logic cell region and separated from the logic cell region. A semiconductor integrated circuit comprising a plurality of unit load capacitances arranged within the wiring region.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a plan view of one embodiment of the present invention.

As shown in FIG. 1, a logic cell area 2.3 in which a plurality of logic cells 4 each consisting of two cell transistors 11.12 are arranged on a semiconductor substrate 1;
3, and unit load capacitances 10 formed in the wiring areas 6 and 7.8 in line with the respective logic cells 4. .

With this configuration, when a logic signal requires a delay time due to the logic circuit design, the load capacitance line 13 can provide the necessary number of unit load capacitances for the logic cells 4a to be delayed.
can be connected to create the required signal delay time.

Therefore, it is not necessary to use other logic cells to delay logic signals.

〔Effect of the invention〕

As explained above, the present invention can provide a delay time to a logic signal by having a plurality of unit load capacitances in a wiring area adjacent to a logic cell area where logic cells constituting the logic are arranged. Therefore, since the logic cell usage rate is not increased, there is an effect that deterioration of wiring performance, deterioration of logic function, and increase in power consumption can be prevented.

[Brief explanation of drawings]

FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a plan view of an example of a conventional semiconductor integrated circuit. 1.1. . . . Semiconductor substrate, 2, 3 . . . Logic cell area, 4, 4. ...Logic cell. 5.5. ．． 6,6. . 7.7. ... Wiring area, 8, 9... Signal line, 10.
...Unit load capacitance, 11.12...Cell transistor, 13...Load capacitance line, 14.15...Signal line.

Claims (1)

[Claims] A semiconductor integrated circuit comprising a logic cell area in which a plurality of logic cells each composed of a plurality of cell transistors are arranged on a semiconductor substrate, and a wiring area provided adjacent to the logic cell area and separated from the logic cell area, A semiconductor integrated circuit comprising a plurality of unit load capacitances arranged within the wiring area.