JPH02244755A - Lsi - Google Patents
LsiInfo
- Publication number
- JPH02244755A JPH02244755A JP6366289A JP6366289A JPH02244755A JP H02244755 A JPH02244755 A JP H02244755A JP 6366289 A JP6366289 A JP 6366289A JP 6366289 A JP6366289 A JP 6366289A JP H02244755 A JPH02244755 A JP H02244755A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- buffers
- wiring
- output buffers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000872 buffer Substances 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 abstract description 4
- 238000012986 modification Methods 0.000 abstract description 3
- 230000004048 modification Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 241000345998 Calamus manan Species 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 235000012950 rattan cane Nutrition 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＬＳＩ、特に論理規模に比して入出力信号の数
が多いＬＳＩに関し、それを論理規模に見合うチップサ
イズに小型化し、高集積化し得るよう企図したものであ
る。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to LSIs, especially LSIs that have a large number of input/output signals compared to the logic scale, and the present invention relates to LSIs, which can be miniaturized to a chip size commensurate with the logic scale, and can be highly integrated. It is designed so that it can be transformed into a
従来のＬＳＩの外部回路には、入出力バッファ及び入出
力パッドの組をチップ周辺部に１列並びに配置していた
。In the external circuit of a conventional LSI, sets of input/output buffers and input/output pads are arranged in a row around the chip.
このため論理規模に比して入出力信号の数が多い論理回
路をＬＳＩとして実装する際は、周囲の入出力端子の数
に見合った、必要以上に広い内部領域が与えられ、そこ
には空き領域が多く存在することになり、実装密度の低
下、及びチップサイズの肥大化が避けられなかった。For this reason, when implementing a logic circuit with a large number of input/output signals compared to the logic scale as an LSI, a larger internal area than necessary is provided, commensurate with the number of surrounding input/output terminals, and there is no empty space. This results in a large number of areas, which inevitably leads to a decrease in packaging density and an increase in chip size.
なお、従来のＬＳＩ多端子化の公知例は１例えば、特開
昭６２−１１４２５９号公報に見られる。A known example of conventional multi-terminal LSI is found in, for example, Japanese Unexamined Patent Publication No. 114259/1983.
これはチップ辺コーナ一部分を入出力回路のために有効
利用するという主旨のもので、入出力バンファセルを回
路機能単位にいくつかに分割し、チップ辺のコーナ一部
分に配置した入出力バッファの機能の一部をチップ辺中
央部に置き換えてはいるが、入出力バッファとしての機
能が入出力方向に多重構造を有している訊けではない。The purpose of this is to effectively utilize a part of the corner of the chip side for input/output circuits.The input/output buffer cell is divided into several circuit function units, and the function of the input/output buffer placed in a part of the corner of the chip side is divided into several parts. Although a part of the buffer is replaced with the central part of the chip side, the function as an input/output buffer does not necessarily have a multiple structure in the input/output direction.
上記の如き論理規模に比して入出力端子の数が多い論理
回路をＬＳＩとして実装する際には、内部領域に空き領
域が多くなり、実装密度が低くなリ、チップサイズが入
出力端子の数に見合った大きさに肥大化してしまうとい
う問題点があった。When implementing a logic circuit with a large number of input/output terminals compared to the logic scale as described above as an LSI, there will be a large amount of free space inside, resulting in a low packaging density, and the chip size will be limited by the number of input/output terminals. The problem was that they grew to a size commensurate with their number.
本発明は上記の問題点を解決し、論理規模に比して入出
力端子数の多いＬＳＩをその論理規模に見合ったチップ
サイズに小型化２高集積化することを目的とする。An object of the present invention is to solve the above-mentioned problems and to miniaturize an LSI, which has a large number of input/output terminals compared to its logic scale, to a chip size commensurate with its logic scale, and to achieve high integration.
上記目的を達成する本発明は、あらかじめ外部領域に入
出力バッファを入出力方向に２重構造にし得るように、
下地を２列分配置しておき、また、内部回路と入出力バ
ッファの配線領域及び入出力バッファと入出力パッドの
配線領域も確保しておく。The present invention achieves the above object, so that the input/output buffer in the external area can be made double-layered in the input/output direction in advance.
The base is arranged in two columns, and wiring areas for internal circuits and input/output buffers, and wiring areas for input/output buffers and input/output pads are also secured.
一方、内部回路の外部回路への接続端子も外部回路の人
出カバソファに接続するに適する間隔に設置する。On the other hand, the connection terminals of the internal circuit to the external circuit are also installed at intervals suitable for connection to the external circuit's covered sofa.
そして回路論理が決まり次第、内部回路にメタル配線を
施し、外部回路との接続端子を形成し。Once the circuit logic is determined, metal wiring is applied to the internal circuit and connection terminals for external circuits are formed.
外部回路には入出力バッファを形成し、それぞれ内部回
路端子と入出力バッファ間及び入出力バッファと入出力
パッド間をメタル配線により接続する。An input/output buffer is formed in the external circuit, and metal wiring is used to connect the internal circuit terminal and the input/output buffer, and the input/output buffer and the input/output pad, respectively.
外部領域に入出力バッファの下地を２列分配置し、その
Ｌ下または左右の入出力方向に内部回路と入出力バッフ
ァ及び入出力バッファと入出力パッドの配線領域を空け
ておくことにより、ＬＳＩの入出力バッファの入出力方
向の２重構造及びその内部回路及びポンディングパッド
との配線を可能にする。LSI This enables a dual structure of the input/output buffer in the input/output direction and wiring with its internal circuit and bonding pad.
また、内部回路の外部回路への接続端子を外部回路の人
出カバソファの間隔に合わせることで、両回路間での配
線を効率良くできるようにする。Furthermore, by matching the connection terminals of the internal circuit to the external circuit with the spacing between the cover sofas of the external circuit, wiring between both circuits can be done efficiently.
さらに、内部回路にメタル配線を施し、外部回路の入出
力バッファを形成し、内部回路の端子と入出力バッファ
および人出カバソファと入出力パッドをメタル配線によ
り接続することで完了する。Furthermore, metal wiring is applied to the internal circuit to form an input/output buffer for the external circuit, and the process is completed by connecting the terminals of the internal circuit to the input/output buffer, the turnout cover sofa, and the input/output pad using metal wiring.
以下１本発明の実施例を第１図及び第２図により説明す
る。An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.
第１図は入出力バッファを入出力方向に２列とし、入出
力パッドは外側に１列に配置したものである。ここで内
側の入出力バッファと人出カパッドはメタル配線により
接続する。この配線は内部回路の入出力端子から外側の
人出カバソファへの配線と同様に、若干の仕様の変更を
した、従来どうりのプロセス技術で可能である。In FIG. 1, input/output buffers are arranged in two rows in the input/output direction, and input/output pads are arranged in one row on the outside. Here, the inner input/output buffer and the output pad are connected by metal wiring. This wiring, like the wiring from the input/output terminals of the internal circuit to the outside cover sofa, can be done using the same conventional process technology with some modifications to the specifications.
ここで、仕様の変更とは外部回路における、入出力バッ
フ７の下地を入出力方向に２列に並べ。Here, the change in specifications means arranging the bases of the input/output buffers 7 in two rows in the input/output direction in the external circuit.
同時に内部回路の人出カ端子と人出カバソファ間および
入出力バッファと入出力パッド間の配線′を実現すべく
おこなう。At the same time, wiring between the internal circuit's output terminal and the output cover sofa, and between the input/output buffer and the input/output pad will be realized.
第２図は入出力バッファを入出力方向に２列にし、同様
に入出力パッドをも２列にした構造である。すなわち入
出力バッファとポンディングパッドの組の２列に並べた
ものである。この場合もプロセス技術は上の例と同様な
もので可能であり、内側の入出力パッドから基板への接
続に用いられるボンディングワイヤは外側の１列の上空
を通す。FIG. 2 shows a structure in which input/output buffers are arranged in two rows in the input/output direction, and input/output pads are also arranged in two rows. In other words, the input/output buffers and the bonding pads are arranged in two rows. In this case as well, the process technology can be the same as in the above example, and the bonding wires used to connect the inner input/output pads to the substrate are passed over the outer one row.
まｆｌｙ、、 ？’ｄ、Ｎ−石−トの２列をさらに応用
し１人出カバソファを入出力方向に３＠以にの多重構造
とすることも可能である。Mafly...? It is also possible to further apply the two rows of 'd and N-stone to create a single-person cover sofa with a multiplex structure of three or more in the input/output direction.
以ｌ−′、のように本発明を応用すれば、論理規模に比
して入出力端！−の多いＬＳｉ、例えばデータ転送用論
理ＬＳＩ等では高集積化をもたらし、チップサイズを大
幅に小型化することが可能である。If the present invention is applied as shown below, the number of input/output terminals compared to the logical scale! In LSis with a large number of -, such as logic LSIs for data transfer, it is possible to achieve high integration and to significantly reduce the chip size.
また内部回路では空き領域を減らし、配線を圧縮できる
ため、各ネットの配線長に伴う信号の遅延が緩和される
ため、高速化も同時に実現できる。In addition, since the internal circuitry can reduce free space and compress wiring, signal delays associated with the wiring length of each net can be alleviated, making it possible to achieve higher speeds at the same time.
第１図は本発明の一実施例の構成図、 第２図は他の実施例の構成図である。 １・・・入出力バッファ、 ２・・・入出力パッド、 ３・・・メタル配線、 ４・・内部領域、 ５・・外部領域。 第 ｆ 図 ｆ−一一一入出力バ′１．，７７ ２−一一一人巳カパーｙＦ ３−−−−メタル胃籐漿 ４−一一一内舒傾Ａ゛ ５−−一タト１印し今づ（域 FIG. 1 is a configuration diagram of an embodiment of the present invention, FIG. 2 is a block diagram of another embodiment. 1...I/O buffer, 2...I/O pad, 3...Metal wiring, 4. Internal area, 5. External area. No. f figure f-111 input/output bar'1. ,77 2-11 Snake Copper yF 3----Metal stomach rattan 4-111 Inward tilt A゛ 5--1 Tato 1 mark Shimazu (area)
Claims (1)
に内部回路及び入出力パッドと接続可能な配置を施し、
それぞれとメタル配線で接続することにより、論理規模
に比して入出力信号の数が多いＬＳＩをその論理規模に
見合うチップサイズに小型化、高集積化することを可能
にする、外部回路構造を特徴とするＬＳＩ。1. The input/output buffer has a double structure in the input/output direction, and is arranged so that it can be connected to the internal circuit and input/output pads.
By connecting each with metal wiring, we have created an external circuit structure that allows LSIs with a large number of input/output signals compared to their logic scale to be miniaturized and highly integrated to a chip size commensurate with their logic scale. Characteristic LSI.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6366289A JPH02244755A (en) | 1989-03-17 | 1989-03-17 | Lsi |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6366289A JPH02244755A (en) | 1989-03-17 | 1989-03-17 | Lsi |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02244755A true JPH02244755A (en) | 1990-09-28 |
Family
ID=13235780
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6366289A Pending JPH02244755A (en) | 1989-03-17 | 1989-03-17 | Lsi |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02244755A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03214658A (en) * | 1990-01-18 | 1991-09-19 | Sharp Corp | Multiple-structure buffer cell |
| JPH04171756A (en) * | 1990-11-02 | 1992-06-18 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| US5946477A (en) * | 1995-08-30 | 1999-08-31 | Nec Corporation | Positioning/wiring method for flip-chip semiconductor device |
| US6130484A (en) * | 1997-07-17 | 2000-10-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| US6727596B2 (en) | 2001-03-19 | 2004-04-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit |
| JP2010283386A (en) * | 2010-09-08 | 2010-12-16 | Renesas Electronics Corp | Semiconductor integrated circuit, and i/o block disposing method |
| JP2011003923A (en) * | 2010-09-08 | 2011-01-06 | Renesas Electronics Corp | Semiconductor integrated circuit and arrangement method of i/o block |
| US8680691B2 (en) | 2000-06-08 | 2014-03-25 | Renesas Electronics Corporation | Semiconductor device having semiconductor member and mounting member |
-
1989
- 1989-03-17 JP JP6366289A patent/JPH02244755A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03214658A (en) * | 1990-01-18 | 1991-09-19 | Sharp Corp | Multiple-structure buffer cell |
| JPH04171756A (en) * | 1990-11-02 | 1992-06-18 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| US5946477A (en) * | 1995-08-30 | 1999-08-31 | Nec Corporation | Positioning/wiring method for flip-chip semiconductor device |
| US6130484A (en) * | 1997-07-17 | 2000-10-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| US8680691B2 (en) | 2000-06-08 | 2014-03-25 | Renesas Electronics Corporation | Semiconductor device having semiconductor member and mounting member |
| US6727596B2 (en) | 2001-03-19 | 2004-04-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit |
| JP2010283386A (en) * | 2010-09-08 | 2010-12-16 | Renesas Electronics Corp | Semiconductor integrated circuit, and i/o block disposing method |
| JP2011003923A (en) * | 2010-09-08 | 2011-01-06 | Renesas Electronics Corp | Semiconductor integrated circuit and arrangement method of i/o block |
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