JP2010283386A - Semiconductor integrated circuit, and i/o block disposing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit wherein its pad pitch can be selected according to its desired I/O number, and can be achieved by its I/O block of its I/O pitch of one kind, and to provide its I/O block disposing method. <P>SOLUTION: In the disposing region portion of the I/O block that can cope with multi-pin, the size of each I/O block, a pad pitch, and the size of each I/O wiring have regularity, the I/O blocks are shifted by a desired pad pitch in the X direction while being stacked vertically, an inner region is provided in its center, and further, the I/O block disposing regions are provided in a periphery of the semiconductor integrated circuit, and the pads are disposed in more outside than the I/O-block disposing region. In such a configuration, the size of each I/O block is made equal to the integer times of the desired pad pitch, and the sizes of the wiring group and the wiring are made equal to the size capable of being disposed in the desired minimum pad pitch. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an I / O block arrangement technique applicable to a semiconductor integrated circuit corresponding to an increase in the number of pins. In particular, a pad pitch can be selected according to a desired number of I / Os and according to a desired number of I / Os. The present invention relates to a semiconductor integrated circuit and an I / O block arrangement method realized by an I / O block having one type of I / O pitch when an I / O block arrangement area changes without waste.

  Conventionally, the I / O block arrangement method is used in the field of semiconductor integrated circuits corresponding to the increase in the number of pins, particularly in an ASIC (from tiny pins to a very large number of pins such as flip chip). Application Specific Integrated Circuit (LSI for specific application) etc. (first prior art).

  In the conventional I / O block arrangement method (first prior art), I / O blocks having different I / O pitches are generally prepared for each desired pad pitch, or I / O blocks having one type of I / O pitch are prepared. All of the O blocks are implemented, and only the same number of I / O blocks as the number of pads realized at a desired pad pitch are used.

  However, due to high integration in recent years, it is desired to prepare I / O buffers with different I / O pitches for each desired pad pitch in order to eliminate useless areas, which requires a lot of development man-hours. was there.

  Examples of conventional techniques for solving such problems are described in, for example, JP-A-9-8227 (second conventional technique) and JP-A-5-267302 (third conventional technique). There is something.

  In the second prior art and the third prior art, I / O cells are arranged vertically and I / O blocks arranged in the periphery of the chip for the purpose of adapting to a flip chip (Flip Chip) and I / O arranged in an internal region. A technique for devising the shape with an O block is disclosed.

JP-A-9-8227 Japanese Patent Laid-Open No. 5-267302

  However, the second prior art and the third prior art have an I / O block arranged in the inner area and an I / O block arranged around the chip for the purpose of stacking I / O cells or adapting to a flip chip (Flip Chip). Although the shape of the I / O block to be arranged is devised, the I / O block area does not change in accordance with the number of necessary I / O blocks while being shifted by a desired pad pitch.

  For this reason, the second prior art has a problem that it is difficult to cope with a standard such as a different pad size for each pad pitch that affects the cost.

  Similarly, when the third prior art is applied to a package other than a flip chip, the problem of the first prior art cannot be solved in an I / O block arranged around the chip. there were.

  The present invention has been made in view of such a problem, and an object of the present invention is to select a pad pitch according to a desired number of I / Os and without waste according to a desired number of I / Os. The object is to provide a semiconductor integrated circuit and an I / O block arrangement method for realizing an I / O block having one type of I / O pitch when the O block arrangement area changes.

According to the first aspect of the present invention, the I / O block dimensions, the pad pitch, and the dimensions of the wiring to the I / O in the portion of the I / O block arrangement area that can accommodate a large number of pins. Is provided with regularity, a plurality of pad pitches are set, an inner area is provided in the center, the I / O block arrangement area is provided in the periphery, and the pad is further outside the I / O block arrangement area. Is provided with an I / O block arrangement configuration in which the dimension in the X direction of the I / O block is an integral multiple of the plurality of pad pitches, and is an integral multiple of the plurality of pad pitches. When the value is larger than a preset constraint value, the dimension in the X direction of the I / O block is within the constraint value and is an integral multiple of the pad pitch excluding a part of the plurality of pad pitches. Setting A first pad pitch in which an integral multiple of the pad pitch corresponds to a dimension in the X direction of the I / O block, and a second in which an integral multiple of the pad pitch does not correspond to a dimension in the X direction of the I / O block. A pad pitch is generated, and an I / O block provided corresponding to the second pad pitch is spaced from another I / O block adjacent in the X direction. It exists in a semiconductor integrated circuit. According to the sixth aspect of the present invention, the I / O block dimensions, the pad pitch, and the I / O in the I / O block arrangement region of the semiconductor integrated circuit that can handle multiple pins. A step of providing regularity to each dimension of the wiring to the substrate, a step of setting a plurality of pad pitches, a step of providing an internal region in the center of the semiconductor integrated circuit, and the I / O block around the semiconductor integrated circuit A step of providing an arrangement region, a step of providing a pad further outside the I / O block arrangement region, and a step of setting the dimensions of the I / O block to a multiple of the pad pitch. In the step of setting the dimension of the O block, when a value that is an integral multiple of the plurality of pad pitches is larger than a preset constraint value, the dimension of the I / O block in the X direction is within the constraint value. In The pad pitch is set to an integral multiple of the pad pitch excluding a part of the pad pitch, and the integral multiple of the pad pitch corresponds to the dimension in the X direction of the I / O block, and the pad pitch A second pad pitch whose integer multiple does not correspond to the dimension in the X direction of the I / O block, and an I / O block provided corresponding to the second pad pitch is adjacent to the X direction. The I / O block arrangement method is characterized in that the I / O block is arranged with an interval between other I / O blocks.

  Since the present invention is configured as described above, the pad pitch can be selected according to the desired number of I / Os, and 1 when the I / O block arrangement area changes without waste according to the desired number of I / Os. There is an effect that it can be realized by an I / O block of various I / O pitches.

1 is a layout diagram of an I / O block of a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 3 is a layout diagram of I / O blocks corresponding to a plurality of pad pitches in the semiconductor integrated circuit according to the first embodiment. FIG. 6 is a layout diagram of an I / O block of a semiconductor integrated circuit according to a second embodiment of the present invention. FIG. 7 is a layout diagram of an I / O block of a semiconductor integrated circuit according to a third embodiment of the present invention.

  The present invention relates to an I / O block dimension (I / O pitch), a pad pitch, and an I / O (Input (input terminal)) in a portion of an I / O block arrangement region in a semiconductor integrated circuit that requires many pins. ) / Output (abbreviation of output terminal)) In addition to providing regularity to each dimension of wiring to I), I / O blocks are shifted in the X direction (left and right direction on the paper) by a desired pad pitch and arranged vertically. It is characterized by having an / O block arrangement configuration. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  (First Embodiment) Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a layout diagram of an I / O block 4 of a semiconductor integrated circuit 1 according to the first embodiment of the present invention. In FIG. 1, 1 is a semiconductor integrated circuit of the present embodiment, 2 is an I / O block arrangement area, 3 is an internal area, 4 is an I / O block, 5 is a pad, 6 is a wiring group, and 7 is a wiring. ing.

  The I / O block arrangement configuration (I / O block arrangement method) of the present embodiment can support a desired pad pitch with I / O of one type of I / O pitch, that is, according to the desired number of I / Os. The I / O block arrangement area 2 is changed without waste.

  That is, as shown in FIG. 1, in the I / O block arrangement configuration (I / O block arrangement method) of the present embodiment, an internal region 3 is provided in the center of the semiconductor integrated circuit 1 and around the internal region 3. In contrast to the configuration in which the I / O block arrangement area 2 is provided and the pad 5 is provided further outside the I / O block arrangement area 2, the dimensions (I / O pitch) of the I / O block 4 (120 μm in the figure) Is an integral multiple of the desired pad pitch (30 μm in the figure) (4 times in the example in the figure), and the dimension of the wiring group 6 connecting the internal circuit (not shown) and the I / O block 4 is the desired minimum pad pitch. The size of the wiring 7 that connects the I / O block 4 and the pad 5 is set to a size that can be arranged at a desired minimum pad pitch, and the X direction (right and left of the page) of those wirings (the wiring group 6 and the wiring 7) Direction) The center position of the I / O block 4 is matched, the I / O block 4 is shifted in the X direction (left and right direction on the paper) by the desired pad pitch, and the dimension of the I / O block 4 (I / O pitch) is divided by the pad pitch. They are arranged vertically.

  In this way, the I / O block arrangement configuration having dimensional regularity is equivalently changed in I / O height according to the pad pitch.

  As a result, compared to the case where a plurality of pad pitches (for example, 30 μm, 40 μm, 60 μm, and 120 μm) are supported by one type of I / O pitch, there is no useless I / O block arrangement area 2 and the manufacturing cost is reduced. There is an effect that you can do it. Also, as compared to the case where a plurality of types of I / O blocks 4 having the same I / O pitch as the pad pitch are prepared for each pad pitch, only one type of I / O pitch needs to be prepared. The effect of reducing is also obtained.

  FIG. 2 is a layout diagram of the I / O block 4 corresponding to a plurality of pad pitches (equivalent pitches, for example, 30 μm, 40 μm, 60 μm, and 120 μm) in the semiconductor integrated circuit 1 of the first embodiment.

  As shown in FIG. 2, for example, when corresponding to four types of pad pitches (equivalent pitch) of 30 μm, 40 μm, 60 μm, and 120 μm, the size (unit pitch) of the I / O block 4 in the X direction (left and right direction on the paper surface) Satisfies the condition that 120 μm is an integral multiple of these, and the wiring connecting the internal circuit (not shown) and the I / O block 4 and the I / O block 4 and the pad 5 respectively has a desired minimum pad pitch (equivalent pitch). ) Which can be arranged at 30 μm, and the center positions of those wirings in the X direction (left and right direction on the paper) are made to coincide, and the I / O block 4 has a desired pad pitch of 30 μm, 40 μm, 60 μm and 120 μm (equivalent) The unit pitch (I / O pitch) of the I / O block 4 is changed to the pad pitch (equivalent pitch) by shifting the pitch in the X direction (left and right direction on the paper). It has a configuration which is arranged in the divided by number only vertically stacked with.

  As described above, the I / O block arrangement configuration of the first embodiment requires only a plurality of pad pitches (for example, 30 μm, 40 μm, etc.) by preparing the I / O block 4 having one type of I / O pitch. 60 μm, 120 μm), and the following effects are brought about.

  First, when the first effect corresponds to the four types of I / O pitches shown in the embodiment (for example, four types of I / O pitches of 120 μm, 60 μm, 40 μm, and 30 μm), one I / O is used. If this is the case, the useless area is eliminated (for example, the useless area of the I / O block arrangement area 2 is changed from 3/4 to 0), so that the manufacturing cost can be reduced.

  Conventionally, when dealing with four types of pad pitches (for example, four types of pad pitches of 120 μm, 60 μm, 40 μm, and 30 μm) with one I / O pitch, four types of pad pitches (for example, with one I / O pitch) , 120 μm, 60 μm, 40 μm, and 30 μm), the minimum pitch of 30 μm (that is, the highest I / O pitch) is used for all pad pitches. There is only. In other words, when dealing with a 120 μm pad pitch, four I / Os with a 30 μm pitch are used, and only one is used, so three I / Os (in other words, 3/4) are wasted. It was a real territory.

  The second effect is that when the I / O for the pad pitch is used, it is not necessary to prepare I / O pitches for the corresponding pitch types, and only one type of I / O pitch can be used. As a result, the development man-hours can be reduced.

  Conventionally, for four types of pad pitches (for example, four types of pad pitches of 120 μm, 60 μm, 40 μm, and 30 μm), the same I / O pitch (for example, four types of I / Os of 120 μm, 60 μm, 40 μm, and 30 μm). When the I / O block 4 of O pitch) is developed and handled, it is necessary to develop four types of I / O blocks 4. However, according to the I / O block arrangement configuration of the present embodiment, all can be handled by one type. As a result, the development man-hour becomes 1/4.

  (Second Embodiment) Hereinafter, a second embodiment of the present invention will be described in detail with reference to the drawings. Note that the same parts as those already described in the first embodiment are denoted by the same reference numerals, and redundant description is omitted. FIG. 3 is a layout diagram of the I / O block 4 of the semiconductor integrated circuit 1 according to the second embodiment of the present invention.

  The basic configuration of the semiconductor integrated circuit 1 of the present embodiment is the same as that of the first embodiment, but the relationship between the dimensions of the I / O block 4 (I / O pitch) and the desired pad pitch. Further devised.

  The configuration is shown in FIG. That is, as shown in FIG. 3, the I / O block 4 size (120 μm in the figure) has an I / O block arrangement configuration that does not make it an integral multiple of the desired pad pitch (80 μm in the figure). have.

  For example, when there are five types of desired pad pitches of 30 μm, 40 μm, 60 μm, 80 μm, and 120 μm, the size of the I / O block 4 in the X direction (left and right direction on the paper surface) is 240 μm which is an integral multiple of these. If the condition is satisfied but 240 μm cannot be realized due to other restrictions on the construction of the I / O block 4, the 120 μm I / O block 4 is realized with two stages of 80 μm pitch as shown in FIG.

  As described above, according to the second embodiment, the pad pitch can be selected according to the desired number of I / Os, and the I / O block arrangement area 2 changes without waste according to the desired number of I / Os. In such a case, there is an effect that it can be realized by the I / O block 4 having one kind of I / O pitch.

  (Third Embodiment) Hereinafter, a third embodiment of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol is attached | subjected about the part same as what was already described in the said 1st Embodiment or 2nd Embodiment, and the overlapping description is abbreviate | omitted. FIG. 4 is a layout diagram of the I / O block 4 of the semiconductor integrated circuit 1 according to the third embodiment of the present invention.

  The basic structure of the semiconductor integrated circuit 1 of the present embodiment is the same as that of the first embodiment, but an I / O block arrangement configuration that can be applied when the pad pitch is not constant is provided. It is characterized by a point. The configuration is shown in FIG. That is, as shown in FIG. 4, the I / O block 4 is arranged so as to be able to cope with both 30 μm and 60 μm pad pitches.

  As described above, according to the third embodiment, the pad pitch can be selected according to the desired number of I / Os, and the I / O block arrangement area 2 changes without waste according to the desired number of I / Os. In such a case, there is an effect that it can be realized by the I / O block 4 having one kind of I / O pitch.

  Note that the present invention is not limited to the above-described embodiments, and it is obvious that the above-described embodiments can be appropriately changed within the scope of the technical idea of the present invention. In addition, the number, position, shape, and the like of the constituent members are not limited to the above embodiments, and can be set to a number, position, shape, and the like that are suitable for carrying out the present invention. Moreover, in each figure, the same code | symbol is attached | subjected to the same component.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit 2 ... I / O block arrangement | positioning area | region 3 ... Internal area | region 4 ... I / O block 5 ... Pad 6 ... Wiring group 7 ... Wiring

Claims (4)

In the portion of the I / O block arrangement area that can accommodate multiple pins, the I / O block dimensions, the pad pitch, and the wiring dimensions to the I / O have regularity, and a plurality of the pad pitches are set. In contrast to the configuration in which an internal area is provided in the center, the I / O block arrangement area is provided in the periphery, and a pad is provided further outside the I / O block arrangement area, An I / O block arrangement configuration in which the dimension in the X direction is an integer multiple of the plurality of pad pitches,
When a value that is an integral multiple of the plurality of pad pitches is larger than a preset constraint value, the dimension of the I / O block in the X direction is within the constraint value, and is a plurality of pad pitches. A first pad pitch that is set to an integral multiple of the pad pitch excluding a part, the integral multiple of the pad pitch corresponds to the dimension in the X direction of the I / O block, and an integral multiple of the pad pitch is the I / O block And a second pad pitch not corresponding to the dimension in the X direction is generated, and an I / O block provided corresponding to the second pad pitch is different from other I / O blocks adjacent in the X direction. A semiconductor integrated circuit having a space between   The semiconductor integrated circuit according to claim 1, wherein the number of the first pad pitches is larger than the number of the second pad pitches. A step of providing regularity to the dimensions of the I / O block, the pad pitch, and the wiring to the I / O in the portion of the I / O block arrangement region of the semiconductor integrated circuit that can accommodate multiple pins, A step of setting the pad pitch of the semiconductor integrated circuit, a step of providing an inner region in the center of the semiconductor integrated circuit, a step of providing the I / O block arrangement region around the semiconductor integrated circuit, and a further step of the I / O block arrangement region. A step of providing pads on the outside, and a step of setting the dimensions of the I / O block to be an integer multiple of the plurality of pad pitches,
In the step of setting the dimension of the I / O block, when a value that is an integral multiple of the plurality of pad pitches is larger than a preset constraint value, the dimension of the I / O block in the X direction is A first pad pitch that is within a constraint value and is set to an integral multiple of the pad pitch excluding a part of the plurality of pad pitches, and the integral multiple of the pad pitch corresponds to the dimension in the X direction of the I / O block. A second pad pitch in which an integral multiple of the pad pitch does not correspond to a dimension in the X direction of the I / O block, and an I / O block provided in correspondence with the second pad pitch, A method of arranging an I / O block, characterized in that the I / O block is arranged with a space between other I / O blocks adjacent in the X direction.   4. The I / O block arrangement method according to claim 3, further comprising the step of setting the number of the first pad pitches to be larger than the number of the second pad pitches.

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