JPS6366059B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to an improvement in mask layout.

In recent years, the density of semiconductor integrated circuit devices has been increasing, and in particular, the number of memory elements in semiconductor memory circuit devices has been rapidly increasing. This also applies to static semiconductor memory circuit devices with a CMOS structure. However, despite the increase in the number of memory elements, the chip size cannot be increased, and the current status is maintained or even reduced in size.
Therefore, it is necessary to suppress the increase in chip size as much as possible not only in the future but also now.

The present invention is one of the above-mentioned suppression measures, and aims to reduce the area occupied by a plurality of timing wiring groups in the peripheral circuit, thereby preventing an increase in chip size as much as possible.

According to the present invention, the chip size can be reduced simply by reviewing the mask layout of a wiring group that occupies a relatively large area on a chip, such as a timing signal line group, and the signal generation circuit related thereto.

Examples of the present invention will be described below while comparing them with conventional ones.

FIG. 1 is a layout diagram of timing wiring that has conventionally been generally used. Here, the timing signal generation circuit 1a is a circuit having only one output terminal, and the timing signal generation circuit 2a is a circuit that receives signals from the output terminal of the generation circuit 1a and generates five output signals. Peripheral circuits 3a, 4
Reference numeral a denotes a peripheral circuit which uses the output signal of the timing signal generation circuit as a common input. Further, the bus line 5a commonly connects the output signals of the timing signal generation circuits to the input terminals of the peripheral circuits. According to this figure, bus lines from the timing signal generation circuit 2a to the peripheral circuits 3a and 4a are each required for exclusive use, which increases the area required for wiring, and in particular, the chip size is increased due to bonding pads, etc. However, if it is restricted only by such a bus line, it will be a considerable disadvantage. In addition, in chips with few peripheral circuits, such as CMOS static circuit devices, even though there are blank areas where no circuit exists, the chip size often has to be increased to accommodate bus line wiring. be.

In the present invention, in order to reduce the area occupied by the bus line wiring, which is a problem, the timing signal generation circuit that generates a plurality of timing signals is divided into two parts and placed close to a specific peripheral circuit whose output is input. This is what I did.

An embodiment of the present invention will be explained with reference to FIG. The timing signal generation circuit 1b drives two divided timing signal generation circuits 2b and 2c each having five output signal lines. Here, the load capacitance Cb increases more than the load capacitance Ca in Figure 1 of the conventional method due to the longer wiring.
Although it is necessary to increase the driving capability of the timing signal generating circuit 1b, the increase in pattern area required for this purpose is not enough to justify the increase in chip size.

Next, the divided timing signal generation circuit 2b
and 2c are placed close to each circuit device in order to minimize the wiring length with the peripheral circuits 3a and 4a. Regarding the load driving ability, the timing signal generation circuits 2b and 2c drive the peripheral circuits 3a and 4a, respectively, but when compared with the conventional method, the driving ability is reduced by the length of the bus line. ability will be an advantage. Incidentally, the increase in pattern area due to the two-division is insignificant compared to the reduction in bus line area according to the present invention.

As mentioned above, by dividing circuits with multiple outputs and a smaller number of input signal lines and placing them close to each dedicated circuit, the area occupied by the bus line can be reduced. . The present invention is more effective as the number of output signals increases with a small number of input signals. Furthermore, the division of the signal generating circuit is not limited to two; if the peripheral circuits to be supplied are arranged separately on the chip, the division may be done accordingly.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a layout configuration in which a plurality of timing signals are commonly supplied to peripheral circuits separated and arranged according to a conventional method, and FIG. 2 is a diagram showing a layout configuration method according to the present invention. 1a, 1b...timing signal generation circuit device that generates only one output signal, 2a, 2b, 2c...
...A timing signal generation circuit device having one input signal and five output signals, 3a, 4a...A peripheral circuit device having five timing signals as a common input,
Ca, Cb...timing signal generation circuits 1a and 1
Load capacity viewed from the output signal terminal of b, 5a, 5
b, 5c...Bus lines that supply timing signals.

Claims (1)

[Claims] 1 a first signal generating circuit device and a first signal generating circuit device receiving only the same input signal;
An integrated circuit device characterized in that second signal generating circuit devices having the same logical function are separated from each other and arranged on the same chip.