JPS6127654A - Master slice type integrated circuit device - Google Patents

Abstract

PURPOSE:To build a required circuit block into a compact construction without an increase in cell areas by a method wherein a plurality of elements, to be put into use as necessary, in a junction region between an internal circuit region and a buffer circuit region. CONSTITUTION:The device of this design is composed of an internal circuit region 1 constituting a logic circuit, a buffer circuit region 2 driving an external load, and a framework region 4 provided with bonding pads 3, and has a plurality of elements 6 installed in a junction region 5 positioned between the internal circuit region 1 and the buffer circuit region 2. In a 3-state control circuit of an output buffer, a transistor Q in the junction region 5 divides the current flowing from the output buffer to an output transistor Q0 in the internal circuit, thereby preventing the transistor Q0 from saturation. Only one internal cell is used for the control circuit, and the transistor Q in this circuit design may be smaller in size than a transistor in a different circuit design wherein a buffer zone transistor is made use of to construct a control circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a master slice integrated circuit device (particularly a connection area between an internal circuit area and a buffer circuit area).
2. The present invention relates to a semiconductor integrated circuit device provided with an element that can be used as part of an internal circuit or part of a buffer circuit.

[Prior art]

FIG. 2 is a schematic top view showing the configuration of a master slice type integrated circuit device according to a conventional example, and shows an internal circuit area 1 configuring a logic circuit. Buffer circuit area 2 that drives external loads
and an assembly area 4 having a bonding pad 6. Of these, in the internal circuit area 1, circuit units (hereinafter referred to as cells) consisting of a plurality of elements are arranged in a matrix.
A circuit block is composed of a plurality of these cells. Note that 5 is a region for connecting the internal circuit element and the buffer circuit. The configuration of the logic circuit is performed by arranging the circuit blocks based on the circuit connection information C2 and then connecting the input and output terminals of each block. The arrangement of circuit blocks and the connections between circuit blocks are usually automatically processed using a computer.

However, in a master slice type integrated circuit, there are two restrictions on the type and number of elements in an internal circuit cell, so when these elements are used to configure a circuit block, there is a problem that the block configuration generally becomes redundant. This situation will be explained with reference to the example of Fig. 6. Fig. 6(a) shows an eight cell circuit, and TTL (Tran@1stor -T
ransistor Logic)'s three-person NAND
It has a function. 11, I2! Is input,
δUT is the output, and the dotted line represents the cell boundary, where one cell is a multi-emitter transistor Qm + output transistor (with Schottky diode clamp) Qo.

It consists of a total of five elements: a diode D and resistors R1+R2+R1. If you try to create a 3-person AND using such a basic cell, it will not be possible to create it with just one cell.
Two cells are required as shown in FIG. 6(b).

If extra elements for Rx = Q6 are prepared in advance in the internal basic cell, a 3-man AND can be configured with one cell, which has the advantage of substantially increasing the number of circuit blocks that can be installed in a 1f tube. However, the area of the unit cell is increased by the increase in the number of elements, which is undesirable as it results in an increase in the chip area.

On the other hand, in actual master slice type integrated circuits, it is extremely rare that all cells in the internal circuit area are used due to the need to efficiently arrange circuit blocks and wire between circuit blocks, and in many cases a considerable number of cells are used. There are unused cells. It is desirable to use the elements of these unused cells as part of the buffer circuit from the standpoint of efficient use of the elements within the chip, and as a result, it is possible to reduce the chip area. However, while the area of elements in internal circuits has become smaller and smaller due to recent advances in high integration, elements in buffer circuits are required to have large driving capabilities in order to charge and discharge external loads at a sufficient speed. Therefore, a larger area is required than the internal circuit elements, and it is becoming increasingly difficult to use the internal circuit elements as part of a buffer circuit.

[Purpose of the invention]

The present invention has been proposed in view of the problems of the conventional example described above, and an object of the present invention is to provide a master slice type integrated circuit device that enables a predetermined circuit block to be configured compactly without increasing the cell area. shall be.

[Structure of the invention]

The present invention provides a master slice integrated circuit comprising an internal circuit area that constitutes a logic circuit in a semiconductor chip and a buffer circuit area that drives an external load, in which a plurality of connection areas between the internal circuit area and the buffer circuit area are provided. The present invention is characterized in that a plurality of elements are provided, and the plurality of elements can be used as part of an internal circuit or a part of a buffer circuit depending on necessity.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic top view showing the configuration of a master slice type integrated circuit device according to an embodiment of the present invention.

The difference from the conventional configuration shown in FIG. 2 is that an element 6 is provided in a connection area 5 between the internal circuit area 1 and the buffer circuit area 2.

FIG. 4 shows an example in which the present invention is applied to a TTL circuit having the same cell structure as FIG. 6(a). The one-dot chain line in FIG. 4 indicates the boundary between the internal circuit area and the connection area (area for connecting the internal circuit and the buffer circuit) (
)) or represents the boundary between the connection area and the buffer area (other symbols are the same as in Figure 6 o) a connection area C-
A transistor Q and a resistor R are installed (S4 Figure 0). Figure 4(a) shows a circuit block with a three-person power A N D <sy2 capability, and whereas the conventional example (Figure 3(b)) was composed of two internal cells, the elements in the connection area were By using this, one cell can have the same function. By using elements in the connection area as part of internal circuit blocks in this way, the number of cells required per block can be reduced, which is particularly advantageous for designing logic circuits that use a large number of blocks.

On the other hand, FIG. 4(b) shows an example in which the present invention is applied to a three-state control circuit for an output buffer. First, consider the case where there is no transistor Q in the connection region 5. When the output OUT of the output buffer circuit is in a high impedance state regardless of the level of input 14 from the internal circuit,
That is, when the output transistor Qo of the control circuit is in the ON state, current flows from the output buffer to Qo. The magnitude of this current is quite large because the output sofa is required to have a large driving capacity for the external load C2, and the resistor R4 in Fig. 4(b) is designed with a relatively small resistance value. . Therefore, unless the output transistor Qo that receives this current is increased to some extent to lower the collector resistance and the Schottky clamp capacity is increased, in the worst case, the transistor Qo will be driven to saturation and cut off (which will take a very long time). However, the area of internal cells is becoming smaller and smaller as integration becomes higher, and in order to prevent saturation of the transistors mentioned above (secondly, it is no longer possible to construct a control circuit with one internal cell). .

In this case, for example, a control circuit is configured with multiple internal cells, and multiple output transistors of the internal cells are connected in parallel.
Next, a method of preventing the saturation of the above transistor can be considered. However, this method results in a substantial decrease in the number of usable blocks in designing the internal logic circuit, and is not an essential solution.

Therefore, it is necessary to give up on forming the control circuit using internal circuit elements, and it becomes necessary to form it in the buffer circuit area. However, this method has the disadvantage that the chip area increases by the area of the control circuit. The transistor Q in the connection region shown in FIG. 4(b) compensates for the above drawbacks.

This transistor plays the role of diverting the current from the output buffer to the output transistor Qo of the internal circuit and preventing Qo from becoming saturated.

As can be seen from Fig. 4(b), the control circuit in this case uses only one internal cell; The size is also small.

next'? Another application example of the present invention is shown in FIG.

In general, the speed of signals between internal circuit blocks is: - Output impedance RO, wiring capacitance Cw, and input capacitance C of the next stage input! The product of the sum of the capacitance and the capacitance t Ro×(Cm + CI)
Since it is determined by
reference). When designing a logic circuit, it is necessary to estimate the (BOX (Cw + Ct) value for each circuit block output, but especially when using a computer to connect circuit blocks, it is necessary to estimate the wiring capacity ffi in advance.
It is generally difficult to estimate Cw. Therefore, in order to reduce variations in speed for each circuit block output due to differences in wiring capacity, the wiring capacity New
A method is adopted in which the output impedance is switched according to the fan-out number (input valley it Ct of the next stage input). Changes in output impedance can be seen, for example, in Figure 5 (b).
) is used as the output resistance. In FIG. 5(b), 8 and 9 represent resistance layers,
Normally, 7 wiring metal patterns are used as a series resistor for resistance layers 8 and 9, but when Cw + CB becomes large, 10 wiring metal patterns are added and used as a resistor for only resistance layer 8 (see Fig. 5 (b). ), 11 is a high concentration impurity layer for making ohmic contact with the wiring metal;
12 represents an opening in the chip surface insulating film. ). In order to suppress variations in speed due to wiring capacitance for each circuit block output, it is desirable to prepare a large number of resistors for output impedance switching. However, this leads to an increase in the cell area, which is undesirable. Therefore, Figure 5 (C)
As shown in , an excessive resistance is placed in the connection area 5, and the output OU
By connecting or disconnecting the wiring 16 according to the wiring capacitance and fan-out, it is possible to reduce the variation in speed for each output without increasing the cell area, and also to reduce the increase in the cell area. It can be prevented.

〔Effect of the invention〕

As explained above, according to the present invention, a plurality of elements are provided in advance in the connection area between the internal circuit area and the buffer circuit area, and are used as part of the internal circuit as necessary, or as part of the buffer circuit. Since it can be used as a part of the circuit, the circuit elements can be used effectively without increasing the internal cell area or the area occupied by the buffer circuit.Therefore, the chip area can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a schematic top view showing the configuration of a master slice type integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a partial schematic top view showing the configuration of a master slice type integrated circuit device according to a conventional example. be. FIG. 6 is a diagram for explaining the problems of the conventional example, in which (a) is a TTL 3-man-powered NAND basic cell, and (b) is a 3-man-powered AND configured by the basic cell.
It is a circuit block of a circuit. FIG. 4 and FIG. 5 show a three-state control circuit and a three-manpower NAND circuit, respectively, which are constructed using a master slice type integrated circuit device according to an embodiment of the present invention. 1... Internal circuit area, 2... Buffer circuit area, 6
...Pounding pad, 4...Asadate area, 5...
・Connection area between internal circuit and buffer circuit, 6... element,
7゜10... Wiring metal button, 8,9... D resistance layer,
11... High concentration impurity layer, 12... Opening in chip surface insulating film, 16... Wiring, Qm... Multi-emitter transistor, Qo... Output transistor, Q...
Transistor, D...diode, Rs + Rt
*Rs r R4+ Ro + R'''Resistance, RO・
・・Output impedance, 11 + It + is+
I4...Input terminal, OUT...Output terminal, VCC
...power supply, GND...grounding, CW...wiring storage,
CI: Input capacity of next stage input. Patent applicant NEC Corporation Figure 1 Figure 2 - (a) (b) Figure 3 (a) (b) Figure 4 (a) (b) (C) Figure 5

Claims (1)

[Claims] In a master slice integrated circuit comprising an internal circuit area that constitutes a logic circuit in a semiconductor chip and a buffer circuit area that drives an external load, a plurality of elements are provided in a connection area between the internal circuit area and the buffer circuit area. A master slice type integrated circuit device, characterized in that the plurality of elements can be used as part of an internal circuit or a part of a buffer circuit as required.