JPH05299598A - Semiconductor device - Google Patents

Abstract

PURPOSE:To decrease electrostatic protective elements in number required between power supply systems and to lessen image memories provided with power supply systems in chip size and cost. CONSTITUTION:Electrostatic protection circuits of image memories provided with power supply systems are composed of electrostatic protecting elements formed of the opposed diffusion layers L11 to L14 and L71 to L72, where ones of the layers are connected to substantially correspondent power supply voltage feed terminal VCC1 to VCC6 or ground potential feed terminal VSS1 to VSS7 and the others of the layers are connected in common through the intermediary of an electrostatic protection element connecting wiring ESB. By this setup, only a single electrostatic protection element is provided corresponding to a power supply voltage feed terminal or a ground potential feed terminal, whereby an electrostatic protection circuit capable of coping with all the combinations of power supply systems can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
For example, the present invention relates to an image memory having a plurality of power supply systems and a technique that is particularly effective when used for electrostatic protection thereof.

[0002]

2. Description of the Related Art A RAM (random access memory) port for randomly inputting or outputting stored data in units of 16 bits, and a SAM (serial access memory) port for similarly inputting or outputting stored data in units of 16 bits. There is a multi-port type image memory provided with. These image memories have a total of 32 output buffers provided corresponding to each bit of the stored data.

Regarding the multi-port type image memory,
For example, “Multiport CMOS Video RAM HM531” published by Hitachi, Ltd. on March 15, 1991.
6123 series data sheet ”.

[0004]

In the above-mentioned image memory and the like, 16 output buffers provided in the RAM port and the SAM port are simultaneously operated for each port, and the power supply noise accompanying this causes the output buffers of the image memory to operate. Other peripheral circuits are affected. For this reason, the inventors of the present application separated the power supply system of the image memory in correspondence with the output buffer and other peripheral circuits, and further separated the power supply system of the output buffer in units of a predetermined number to reduce power supply noise. I thought to suppress the influence. At this time, the image memory package is provided with a power supply voltage supply terminal and a ground potential supply terminal corresponding to each power supply system, and between the power supply voltage supply terminal or the ground potential supply terminal corresponding to these supply terminals. It is necessary to take electrostatic protection measures to secure electrostatic breakdown voltage.

In a conventional image memory or the like, an electrostatic protection measure for ensuring the electrostatic breakdown withstanding voltage between the respective power supply voltage supply terminals or the ground potential supply terminals is to protect each power supply voltage supply terminal or the ground potential supply terminal from other terminals. It has been realized by providing an electrostatic protection element between each of the power supply voltage supply terminals or the ground potential supply terminals. Therefore, when the image memory or the like is provided with m power supply voltage supply terminals or ground potential supply terminals, the number n of electrostatic protection elements required for electrostatic protection measures is n = _m C ₂ . However, if the power supply system such as the image memory is made plural and the number of the power supply voltage supply terminals and the ground potential supply terminals reaches 13 as in the image memory described above, it is necessary for the electrostatic protection measures. The number n of electrostatic protection elements reaches n = ₁₃ C _2, that is, 78. This increases the layout area of the electrostatic protection element itself and also increases the layout area of the power supply wiring for transmitting each power supply voltage or ground potential to the corresponding plurality of electrostatic protection elements. As a result, the chip area of the image memory or the like increases, which hinders cost reduction.

An object of the present invention is to reduce the number of electrostatic protection elements required between a plurality of power supply systems. Another object of the present invention is to reduce the chip size of an image memory or the like having a plurality of power supply systems and promote cost reduction thereof.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, an electrostatic protection circuit such as an image memory having a plurality of power supply systems is connected to a corresponding power supply voltage supply terminal or a ground potential supply terminal, one of which is a predetermined connection wiring which is made of a metal wiring layer. Basically, a plurality of electrostatic protection elements that are commonly coupled to each other are configured.

[0009]

According to the above means, an electrostatic protection circuit capable of supporting all combinations of power supply systems can be realized by providing only one electrostatic protection element corresponding to the power supply voltage supply terminal or the ground potential supply terminal. it can. As a result, it is possible to reduce the chip size of an image memory or the like having a plurality of power supply systems and promote cost reduction.

[0010]

FIG. 1 is a block diagram showing an embodiment of an image memory VRAM to which the present invention is applied. First, an outline of the image memory of this embodiment will be described with reference to FIG. The circuit elements forming each block in FIG. 1 are formed on one semiconductor substrate such as P-type single crystal silicon, although not particularly limited thereto. Further, the following description will be focused on the part related to the electrostatic protection circuit, and the description regarding the memory mats MAT1 and MAT2 and the like which are not directly related to the present invention will be omitted.

In FIG. 1, the image memory V of this embodiment is shown.
The RAM is not particularly limited, but is a so-called multi-port type image memory, and 16 data input / output terminals IO0 to IO15 provided corresponding to the RAM port.
And 16 data input / output terminals SIO0 to SIO15 provided corresponding to the SAM port, and further, nine address input terminals A0 to A8 and a predetermined number of control signal input terminals RASB to QSF. Prepare

Here, the eight RAM port data input / output terminals IO0-IO7 are coupled to the RAM port data input / output circuit IOR1, and the remaining eight RAM port data input / output terminals IO8-IO15 are RAM. It is coupled to the port data input / output circuit IOR2. Needless to say, the RAM port data input / output circuit IOR1 is
The RAM port data input / output circuit IOR2 includes eight input buffers and eight output buffers provided corresponding to the M port data input / output terminals IO0 to IO7.
Eight input buffers and output buffers provided corresponding to the data input / output terminals IO8 to IO15 for the M port are provided.

RAM port data input / output circuit IOR1
And 16 input buffers forming IOR2 are simultaneously operated when the image memory VRAM is selected in the random write mode, and are input via the RAM port data input / output terminals IO0 to IO15. The bit write data is fetched and written into the selected 16 memory cells of the memory mat MAT1 or MAT2 (not shown). On the other hand, the 16 output buffers constituting the RAM port data input / output circuits IOR1 and IOR2 are simultaneously operated when the image memory VRAM is selected in the random read mode, and the memory mats MAT1 or MAT2 are selected. The read signals output from the 16 memory cells are amplified and sent from the RAM port data input / output terminals IO0 to IO15.

Next, the five SAM port data input / output terminals SIO0-SIO4 are coupled to the SAM port data input / output circuit IOS1, and the five SAM port data input / output terminals SIO5-SIO9 are connected to the SAM port. For data input / output circuit IOS2. In addition, the remaining six SAM port data input / output terminals SIO10 to SIO
Reference numeral 15 is coupled to the SAM port data input / output circuit IOS3. Data input / output circuit IOS1 for SAM port
Are data input / output terminals SIO0 to SIO for the SAM port.
The data input / output circuit IOS for the SAM port is provided with five input buffers and output buffers provided corresponding to four.
2 and IOS3 are SAM port data input / output terminals S
It has five or eight input buffers and eight output buffers provided corresponding to IO5 to SIO9 and SIO10 to SIO15, respectively.

SAM port data input / output circuit IOS1
Up to 16 input buffers constituting IOS3 are simultaneously operated when the image memory VRAM is selected in the serial write mode, and are serially input via the SAM port data input / output terminals SIO0 to SIO15. The 16-bit write data is sequentially fetched and written in the selected memory cell of the memory mat MAT1 or MAT2 (not shown). On the other hand, a total of 16 output buffers constituting the data input / output circuits IOS1 to IOS3 for the SAM port are simultaneously operated when the image memory VRAM is selected in the serial read mode, and the memory mats MAT1 or MAT2. Amplifies the read signal output from the selected memory cell,
SAM port data input / output terminals SIO0 to S15 are sequentially transmitted serially.

Further, the address input terminals A0 to A8 are
Control signal input terminal R coupled to address buffer AB
ASB to QSF are coupled to the timing generation circuit TG. The address buffer AB has an address input terminal A
Equipped with nine unit circuits provided corresponding to 0 to A8,
A memory mat MAT1 (not shown) receives an address signal input through the address input terminals A0 to A8.
And MAT2 address decoder. Further, the timing generation circuit TG has a row address strobe signal RASB input via the control signal input terminals RASB to QSF (here, for a so-called inverted signal which is selectively brought to a low level when it is enabled, It is represented by adding B to the end of the name. The same applies hereinafter), various internal control signals for controlling the operation of the image memory VRAM are selectively formed based on the special function signal QSF, etc. Supply to.

In this embodiment, the image memory VRAM
Further includes six power supply voltage supply terminals VCC1 to VCC
6 and 7 ground potential supply terminals VSS1 to VSS7. Of these, the power supply voltage supply terminals VCC1 to VCC
6 is commonly coupled outside the package of the image memory VRAM and commonly receives a predetermined power supply voltage VCC from a power supply device (not shown). Similarly, the ground potential supply terminal VS
S1 to VSS7 are commonly coupled outside the package of the image memory VRAM, and are connected to the ground potential V from the power supply device.
Receive SS in common. The power supply voltage VCC is a positive power supply voltage such as + 5V, although not particularly limited.

The power supply voltage VCC supplied via the power supply voltage supply terminal VCC1 and the ground potential supply terminal VSS1
The ground potential VSS supplied through is supplied as an operating power supply of the RAM port data input / output circuit IOR1.
The power supply voltage VCC supplied via the power supply voltage supply terminal VCC2 and the ground potential VSS supplied via the ground potential supply terminal VSS2 are supplied as operating power supplies of the RAM port data input / output circuit IOR2. In addition, the power supply voltage VC supplied via the power supply voltage supply terminal VCC3
The ground potential VSS supplied through C and the ground potential supply terminal VSS3 is supplied as an operating power supply for the SAM port data input / output circuit IOS1 and is supplied through the power supply voltage supply terminal VCC4. Ground potential V supplied via supply terminal VSS4
SS is supplied as an operating power supply for the SAM port data input / output circuit IOS3.

On the other hand, the power supply voltage VCC supplied via the power supply voltage supply terminal VCC5 and the ground potential supply terminal V
The ground potential VSS supplied via SS5 is supplied as an operating power supply for the SAM port data input / output circuit IOS3, and is supplied via the power supply voltage supply terminal VCC6 and the ground potential supply terminals VSS6 and V6.
The ground potential VSS supplied via SS7 is supplied to the other peripheral circuits PERF including the address buffer AB and the timing generation circuit TG. As a result, the power supply system of the image memory VRAM of this embodiment is divided into six systems, whereby 16 output buffers forming the RAM port data input / output circuits IOR1 and IOR2 or SAM port data input / output. Circuit IOS
This makes it possible to suppress the influence of power supply noise that accompanies the 16 output buffers constituting the 1 to IOS 3 being simultaneously operated.

FIG. 2 is a partial board layout diagram of one embodiment of the image memory VRAM shown in FIG. Further, FIG. 3 shows an AB cross-sectional structural view of an embodiment of the electrostatic protection element included in the image memory VRAM of FIG. 2, and FIG. 4 shows a static protection element included in the image memory VRAM of FIG. An equivalent circuit diagram of one embodiment of the electrical protection circuit is shown. Based on these figures, the specific configuration and operation of the electrostatic protection circuit of the image memory of this embodiment and its features will be described. It should be noted that FIG. 2 is created focusing on the portion related to the electrostatic protection circuit of the image memory VRAM, and the bonding pads, peripheral circuits and the like not directly related to the present invention are omitted. Hereinafter, the positional relationship on the surface of the semiconductor substrate PSUB will be represented by the positional relationship of FIG. 2 and FIG.

In FIG. 2, the image memory V of this embodiment is shown.
The RAM is not particularly limited, but the so-called LOC (Le
Ad On Chip) package form, 13 bonding pads VCC1 to VCC6 and VS
All the bonding pads including S1 to VSS7 are arranged in a line at the center of the semiconductor substrate PSUB. Bonding pads VCC1 to VCC6 and V
SS1 to VSS7 are corresponding power supply voltage supply terminals VCC1 to VCC6 via bonding wires (not shown).
And ground potential supply terminals VSS1 to VSS7, respectively, and further connected to a corresponding circuit of the image memory VRAM via a power supply wiring (not shown). The memory mat MAT1 is arranged on the left side of the semiconductor substrate PSUB with a relatively large layout area, and the memory mat MAT2 is arranged on the right side of the semiconductor substrate PSUB with a relatively large layout area.

In this embodiment, an N type diffusion layer L71 (first diffusion layer) is formed at a position close to the bonding pad VSS7, and an N type diffusion layer L72 (first diffusion layer L72) is formed so as to face the diffusion layer. 2 diffusion layers) are formed. Also,
N-type diffusion layers L11 and L12 (first diffusion layers) are formed at positions close to the bonding pads VCC1 and VSS1, respectively, and N-type diffusion layers L13 and L14 (first diffusion layers) are formed so as to face these diffusion layers. 2 diffusion layers) are respectively formed. Similarly, the bonding pad VCC2
And N-type diffusion layers L21 and L22 to L61 and L62 (first diffusion layers) are formed at positions close to VSS2 to VCC6 and VSS6, respectively, and the N-type diffusion layers are arranged to face these diffusion layers. L23 and L24 to L63 and L64 (second diffusion layers) are formed, respectively. The first diffusion layer including the diffusion layer L71 is coupled to the corresponding bonding pad VSS6 or the like via a contact, as represented by the diffusion layer L62 in FIG. The second diffusion layer is commonly coupled to the electrostatic protection element coupling wiring ESB made of the aluminum wiring layer AL via a contact.

Here, a total of 13 pairs of diffusion layers formed so as to face each other, as shown by the diffusion layers L62 and L64 in FIG. The electrical protection element DS13 is formed. That is, the diffusion layer L62 is formed on the semiconductor substrate PSUB together with P
The N-junction type parasitic diode D62 is formed, and the diffusion layer L6 is formed.
4 forms a similar parasitic diode D64. These parasitic diodes D62 and D64 are further coupled in series via the semiconductor substrate PSUB to form an electrostatic protection device DS13 having a predetermined breakdown voltage. Needless to say, such an electrostatic protection element is similarly formed in all the diffusion layer pairs facing each other, thereby forming an electrostatic protection circuit as shown in FIG.

That is, the image memory VRA of this embodiment
As shown in FIG. 4, the electrostatic protection circuit M includes a total of 13 electrostatic protection elements DS1 to DS13 each having a pair of diffusion layers facing each other. One of these electrostatic protection elements is coupled to the corresponding bonding pad, that is, the corresponding power supply voltage supply terminals VCC1 to VCC6 and ground potential supply terminals VSS1 to VSS7, and the other one is connected to the electrostatic protection element coupling wiring ESB. Are commonly connected through. As a result, the power supply voltage supply terminals VCC1 to VC
C6 and the ground potential supply terminals VSS1 to VSS7 are
Corresponding two of the electrostatic protection elements DS1 to DS13 and all the combinations are connected via the electrostatic protection element coupling wiring ESB, and a corresponding static electricity is provided between each power supply voltage supply terminal and the ground potential supply terminal. A predetermined electrostatic breakdown withstand voltage corresponding to about twice the breakdown voltage of the electrical protection elements DS1 to DS13 is secured.

As is clear from the above description, the number of electrostatic protection elements required for the electrostatic protection circuit is the same as the number of power supply voltage supply terminals and ground potential supply terminals, that is, 13 and is the same as the conventional one. Compared with the case where the electrostatic protection element is provided between each power supply voltage supply terminal and the ground potential supply terminal as in the image memory, it is 1/6. In addition, the electrostatic protection element coupling wiring ES for commonly coupling 13 electrostatic protection elements
B has a single linear shape when the image memory adopts the LOC package form, and its layout area is also the smallest. As a result, the chip size of the image memory is reduced while ensuring a predetermined electrostatic breakdown voltage in all combinations of the power supply voltage supply terminal and the ground potential supply terminal.
The cost reduction can be promoted.

By the way, the image memory VRA of this embodiment
In M, as is clear from FIG. 4, the electrostatic protection element DS1
The electrostatic protection element coupling wiring ESB for commonly coupling the other of DS13 to DS13 is in a floating state, and in some cases, the charge accumulated in the electrostatic protection element coupling wiring may affect the operation of the image memory. .. To deal with this, as illustrated in FIG. 5, the electrostatic protection element coupling wiring ESB is connected to the bonding pad VSS6, that is, the ground potential supply terminal VS via a predetermined resistor R1 (resistor means).
It is effective to couple to S6 etc. and leak the electric charge accumulated in the electrostatic protection element coupling wiring ESB. In this case, the resistance value R1 of the resistor R1 is equal to the electrostatic protection element coupling wiring E.
An essential condition is that R1> re be satisfied with respect to the distributed resistance re of SB.

By applying the present invention to a semiconductor device such as an image memory having a plurality of power supply systems as shown in some of the above embodiments, the following operational effects can be obtained. That is, (1) a static electricity protection circuit such as an image memory having a plurality of power supply systems, one of which is substantially connected to a corresponding power supply voltage supply terminal or a ground potential supply terminal, and the other is a predetermined metal wiring layer. By basically configuring a plurality of electrostatic protection elements that are commonly coupled via the coupling wiring of, all that is required is to provide one electrostatic protection element corresponding to the power supply voltage supply terminal or the ground potential supply terminal. It is possible to obtain an effect that an electrostatic protection circuit that can cope with the combination of the power supply systems can be realized. (2) In the above item (1), a coupling wiring for commonly coupling the other of the electrostatic protection elements is connected to a predetermined power supply voltage supply terminal or a ground potential supply terminal via a resistance means having a relatively large resistance value. By coupling, it is possible to prevent the coupling wiring from being in a floating state, leak the accumulated charge, and prevent the accumulated charge from affecting other circuits of the image memory. (3) According to the above items (1) and (2), while stabilizing the operation, it is possible to reduce the chip size of an image memory having a plurality of power supply systems and promote cost reduction. Is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the number of power supply voltage supply terminals and ground potential supply terminals provided in the image memory VRAM can be set arbitrarily. Further, the power supply voltage supply terminals VCC1 to VCC6
Can be supplied with power supply voltages having different potentials, and their polarities are also arbitrary. Power supply voltage supply terminals VCC1 to VC
C6 and the ground potential supply terminals VSS1 to VSS7 are
It is also possible to partially jointly bond some of them. In FIG. 2, the diffusion layer and the electrostatic protection element coupling wiring ESB may have various shapes and arrangement positions, and the image memory VRAM does not necessarily have to have the LOC package form. In FIG. 3, the electrostatic protection element is
For example, an N-type buried layer formed in advance under the diffusion layers L62 and L64 may be included. Further, as the material of the bonding pad and the electrostatic protection element coupling wiring ESB, a metal wiring layer other than the aluminum wiring layer can be used. In FIG. 5, the electrostatic protection element coupling wiring ESB can be coupled to another power supply voltage supply terminal or a ground potential supply terminal via the resistor R1.

In the above description, the case where the invention made by the present inventor is applied to the image memory which is the field of application which is the background of the invention has been mainly described, but the invention is not limited thereto and the dynamic RAM or the like is used. It is also applicable to various memory integrated circuits and digital integrated circuits including such memory integrated circuits. The present invention can be widely applied to semiconductor devices having at least a plurality of power supply systems.

[0030]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, an electrostatic protection circuit such as an image memory having a plurality of power supply systems is connected to a corresponding power supply voltage supply terminal or a ground potential supply terminal, one of which is a predetermined connection wiring which is made of a metal wiring layer. By basically configuring a plurality of electrostatic protection elements that are commonly coupled via, it is only necessary to provide one electrostatic protection element corresponding to the power supply voltage supply terminal or the ground potential supply terminal, and all power supply systems It is possible to realize an electrostatic protection circuit that can handle the combination of As a result, it is possible to reduce the chip size of an image memory or the like having a plurality of power supply systems and promote cost reduction.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an image memory to which the present invention is applied.

FIG. 2 is a board layout diagram showing an embodiment of the image memory of FIG.

FIG. 3 is a cross-sectional structural view taken along line AB of an example of the electrostatic protection element included in the image memory of FIG.

FIG. 4 is an equivalent circuit diagram showing an embodiment of an electrostatic protection circuit of the image memory of FIG.

FIG. 5 is an equivalent circuit diagram showing another embodiment of the electrostatic protection circuit of the image memory to which the invention is applied.

[Explanation of Codes] VRAM ... Image memory, IOR1 to IOR2 ...
RAM port data input / output circuit, IOS1 to IOS3
... SAM port data input / output circuit, AB ... address buffer, TG ... timing generation circuit. IO
0 to IO15 ... Data input / output terminals for RAM port,
SIO0 to SIO15 ... SAM port data input / output terminals, A0 to A8 ... Address input terminals, RASB
~ QSF ... Control signal input terminals, VCC1 to VCC6
... Power supply voltage supply terminals or bonding pads, VS
S1 to VSS7 ... Ground potential supply terminals or bonding pads. PSUB ... P-type semiconductor substrate, MAT1 to
MAT2 ... Memory mat, ESB ... Electrostatic protection element coupling wiring, L11 to L72 ... Diffusion layer. N ⁺ ...
N type diffusion layer, AL ... Aluminum wiring layer, SiO ₂
... Silicon oxide film, LOCOS ... Locos, DS
1 to DS13 ... Electrostatic protection element, D62, D64 ...
-Parasitic diode, R1 ... Resistance.

Claims (4)

[Claims] 1. A plurality of power supply voltage supply terminals and / or ground potential supply terminals, one of which is substantially connected to the corresponding power supply voltage supply terminal or ground potential supply terminal, and the other is connected via a predetermined connection wiring. And a plurality of electrostatic protection elements that are commonly coupled to each other. 2. The coupling wiring is formed of a predetermined metal wiring layer, and each of the electrostatic protection elements is substantially coupled to the corresponding power supply voltage supply terminal or ground potential supply terminal. 2. The semiconductor device according to claim 1, further comprising a first diffusion layer and a second diffusion layer formed so as to face the first diffusion layer and coupled to the coupling wiring. 3. The coupling wiring is substantially coupled to a predetermined power supply voltage supply terminal or ground potential supply terminal through a resistance means having a resistance value sufficiently larger than its distributed resistance. The semiconductor device according to claim 1 or 2, which is characterized. 4. The semiconductor device according to claim 1, wherein the semiconductor device has a LOC package form.