JPS5850698A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To decrease the level of current consumption, by using a control means which contains the decoders, memory cells, sense amplifiers and output buffers and drives selectively the output buffer with an address data. CONSTITUTION:The memory cell groups 4 storing data in corresponding to prescribed bit, plural sense amplifiers 5 which detect the data given from the memory cells, and the output buffer groups 6 that detect the detection data are provided at both sides of a line decoder 1 and a row decoder 2 that receive the address data and designate the prescribed address. The buffer group 6 is selectively driven with the address data and delivers the data given from a memory cell designated by the decoder through the group 6 which is selectively driven. Thus the current flowing to a load circuit 7 is limited to a right or left half. As a result, the level of current consumption is greatly decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory having a weight of 41 kg, and particularly to a semiconductor memory with reduced current consumption.

FIG. 81 shows nine circuit configurations of a conventional RAM. This RAM
In this case, the row decoder 1 to which these addresses are inputted selects one row line WL depending on the combination of address datums, m, . Further, the column decoder 2 selects the output line DOL of the address column decoder, and depending on 11"@P of this column decoder output line DOL, the column selection circuit 3 selects one of the pair of column lines Q, ,
Select Qゎ. Then, selected in this way, the output bits Oo to 0 are output by the ninth row line WL and columns 111Qn and Qn.
The sense amplifier 5 detects the data of one memory cell MC from the memory cell array 4 corresponding to 1. It is sent as 0 to 01.

Details of the above-mentioned memory cell MC are shown in FIG. 2. The portion surrounded by broken lines corresponds to each memory cell MC, and this memory cell group is a well-known static type RAM cell consisting of nine cross-coupled flip-frogs. That is,
A resistor R1 and an enhancement lever (
E type) MOB) Rannostar Q1 is connected in series between the above power supply V and V, and nine resistors R2 and En@
The gates of these transistors Q1 and sQI are connected to the connection point of transistor Q1 and resistor R1, respectively.
1 and the connection point B of the resistor R2. In addition, these connection points M and B are respectively enhanced
8) Column lines Qn, Qn via transistor QsmQa
The gates of the transistors Q@IQ4 are connected to the row lines WLIfC@, respectively.

In the memory cell MC configured in this way, when the connection point M is at @1'' level (for example, tf5V), the transistor Qm is turned on, and when the connection point Bd is at the O'' level (for example, OV), the transistor Qm is turned on. Since Q1 is off,
Point B and point B are stably held at @l# and @Q'' levels, respectively.

Now, if this memory cell MC is selected and is OK, the row line WL becomes "1" and the transistor Qs.

When Q4 is turned on and the data at points M and B are transmitted to the column line QnsQ, and the column selection circuit 3 selects the pair of columns -Qneζ, the data on the column lines Q, , Q become senseless! 5 and sent out by the output buffer circuit 6.

Note that, as shown in FIG. 1, a load circuit 1 is connected to each of the column lines Qn and Qn. This means that if the memory is of a type that precharges the column lines Qn, Q, a precharge circuit is connected as a load circuit, and when a precharge signal is applied, all column lines Qn, ζ are uniformly charged to a predetermined value. Precharge to potential level. In addition, simply as shown in FIG. 2, load transistor Q1 is connected to voltage #v8 and column I Qn,
Q: There is also one that connects between the stoppers and connects this to the load circuit. In these load circuits 1, the potential level of the column line Qnm% is too low or too low, and when the memory cell MC is selected and data is read out, the -1" level of the memory cell MC is @Om
At level 9, there is a risk of writing errors, so
It serves to maintain the 10 lvl of column lines Qn, Qn at a certain intermediate potential level. In addition, the memory cell MC
If the resistance values of resistors RJ and RJ in the memory cell MC are reduced, the current consumed by the memory cell MC increases, so these resistance values are made as large as possible. For this reason, it takes a very long time to charge the column lines Qn and the column lines only with the resistors R1 and R2, so a load circuit is used to compensate for this.

However, the load circuit 1 described above has all column lines Q,Q.

KI! For example, transistors Q1 . Since Q4 is turned on, the load circuits 7 connected to all columns it Q, , Q, are activated. Therefore, the current supplied by this load circuit 1 is very large, and the load circuit wr1 also supplies current to the non-selected column lines, resulting in a wasteful current flowing. The memory circuit shown in FIG. 3 was conventionally considered to reduce the current flowing through the load circuit 1 as much as possible.

In the circuit shown in FIG. 1 described above, nine peak recell arrays 4 are arranged on each side of the row decoder 1 for 4 bits corresponding to the 8 bits of output, but in the circuit shown in FIG.
Memory cell arrays 4 corresponding to bits and bits are arranged on both sides of the row decoder J for each 8 bits. For example, this address data A is 11 by the address datum.
When the address datum is @01, the right 8 bits of row decoder 1 are selected, and when the address datum is @01, the left 8 bits of row decoder 1 are selected.
Bits are selected and outputted individually.

Then, when this address data A or 11" is selected, the right row line WL of the next row decoder 1 becomes @1m, and all the left row lines WL become "O". Therefore, ;Morisel MC's For example, the transistor QIIQ4 in FIG.
``Since it is charged to the left level, there is no current flowing from the load circuit 7 on the left. Therefore, compared to the circuit in Figure #I1, the third
In the circuit shown in the figure, the current flowing out of the load circuit 1 is halved, and the current consumption can be significantly reduced.

In FIG. 3 mentioned above, the transistor Q to which address data A is dart input and the address data shoulder ir
When the address datum 1 is @lI', the transistor Q1 is turned on, and the data in the memory cell array 4 on the right side of the row decoder 1 is transmitted to the sense amplifier 6. At this time, the transistor Q1 is turned off to prevent the data in the memory cell array 4 on the right side from flowing out to the left side, thereby reducing the load capacitance up to the sense amplifier 5. When address datum 1 is 10m, transistor Q1 is off, transistor Q1 is on, and row decoder 1
The data in the memory cell array 4 on the left side of the sense amplifier 5
transmitted to. However, in the circuit configuration shown in FIG. 3, it is necessary to connect the memory cell arrays 4 on the right and left sides of the row decoder 1, that is, to connect the corresponding drains of the transistors Q and Ql corresponding to the output bits. There is. If such a circuit is fabricated on a 5s square IC chip, the inventors' experience shows that the wiring for these transistors alone requires a length t. Furthermore, two wires are required for each of the column lines Qn and Q to transmit data to the sense amplifier 5, and these wires alone occupy the surface area of the chip. This means that in a circuit configuration like the one shown in Figure 3,
This means that the load capacitance between the sense amplifier f5 and the column selection circuit 3 becomes extremely large. Further, the dimensions of the transistors constituting the memory cell MC must be extremely small in consideration of the chip size, and the driving ability is correspondingly small, resulting in a slow reading speed of the memory.

Furthermore, there is a drawback that the chip size becomes large due to the above-mentioned wiring connections.

The present invention has been made to overcome the above-mentioned drawbacks, and
Sense amplifiers, output covers, and buffers are arranged on the left and right sides of the decoder corresponding to nine predetermined bits of memory cell arrays, and the corresponding output pins of the left and right output buffers of this decoder are connected to each other by wiring. The current consumption flowing in the load circuit connected to the column line can be reduced by using a circuit configuration that selects and controls the left and right outputs/four buffers based on the address data input to the column line and sends the data from the memory cell array to the outside. It is an object of the present invention to provide a semiconductor memory that can significantly reduce read speed and prevent read speed from decreasing due to wiring capacitance.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In the memory circuit shown in FIG. 4, the same reference numerals are used for the same parts as described above, and a brief description thereof will be given. That is, in the circuit of FIG. 4, the row decoder 1 is
The memory cell arrays 4 on the right and left sides of the memory cell arrays 4 are the same in that they are selected by the address datum 1, for example.

Therefore, the current flowing through the load circuit 1 is halved compared to the conventional circuit shown in FIG. However, this circuit,
Before inputting to the sense amplifier 5 as in the circuit shown in FIG.
The number of sense amplifiers 5 and outputs 6 is doubled, with the center amplifier f6, output cover, and amplifier circuit 6 connected corresponding to the 8 bits on the right side and the 8 bits on the left side. The outputs of the eight paddles 6 arranged on the right and left sides of the decoder 1 are connected to each other to connect the outputs corresponding to the outputs 0 to 07 to be sent to the outside.

Usually, a large capacitor of about 1509 F is connected to the output of the IC as an external load capacitor. Therefore, as described above, the load capacitance caused by the wiring connecting the output cover and the Noah 6 is small enough to fall within the range of the external load capacity 1509F, and this output cover,
There is no delay in the read speed for reading data from the memory cell next time due to the load capacitance caused by the connection between the NORs 6.

Further, in the circuit shown in FIG. 4, the address datum 1
．． By controlling ``Yoshi Output 7A6'', it is determined whether the data is from the memory cell array 4 on the right side of the row decoder 1 or the data from the memory cell array 4 on the left side, and the data is output. There is.

In this way, the output buffer 6 is connected to the address data A, , A.
, the current flowing through the load circuit 1 flows only through the right half of the load circuit 7 or the left half, resulting in a significant reduction in current consumption.

An example of the output cover 77 circuit controlled and driven by the above-mentioned nine address data A, , A is shown in FIG. 61 indicates the exit cover 7a located on the left side. In this circuit 61, an enhancement certificate ([
ilJ) MOB) Transistor QC, Dart is connected to the source. Depres, thin type (D type) MOB) Transistor Q*, r) is supplied with data from sense amplifier 5. KfiMO8) Transistor Q1@ is connected in series. It is connected to the. This transistor QI.

E臘MO8) Lannostar Qts whose gate was connected to the common connection point of Qi, and whose source was connected to the power supply V Km, and its source gate was connected to the drain of this transistor Qsm, and its drain was connected to the power supply V. IlltM
O8)9 sensor Qtt is provided. In addition, transistors Qll-Q14 are connected in series between the power supplies V and 7, address data A is input to the dart of the E-type MO8) lannostar Qss, and the dart of the E-type MO&) transistor Q14 is input from the output enable circuit. The output signal E of is input. This output enable circuit is used when the outputs of multiple memories are connected to one pass line, and operates the output buffer of the selected memory to output the data, and outputs the output of the non-selective memory. This is a circuit that creates a high impedance state to eliminate interference with the pass line, and is normally included in normal semiconductor memories.

Further, the gate of the D-type M08 transistor Qli is connected to the transistors Q■, Q11 constituting the second inverter.
is connected to the interconnection point of E type MO8)2 transistor Q1
The gate of - is connected to the interconnection point of the transistors Q* and Qs· constituting the first inverter 1. The transistor (hs+Q1) constitutes a first buffer B=. Between the interconnection point of this tone transistor Q*i*Ql@ and the power supply V, an inverted signal address data Ai of the address datum amount and an inverted signal address data Ai of the signal E are connected. When the inverted signal E is input (f-), gmMost>ynostarQ
typQxs is provided. Similarly, transistors 91 to Q■ are connected in series between the power supplies v and v, and
08 transistor Q1-'s r-) is inputted with h address data-tum 1, and IWMO8's transistor Q's f-)
The signal E is input to 2. Also, 0mMO8) r-) of Ranno Ruri Qss is 1Mr transistor Qs*
At the interconnection point of Qt.
are connected to the interconnection points of #I2 and Bs at these transistors Qmt * Qss.
&Configure.・, this transistor Qs* a Qns
As described above, between the mutual connection point of 2. Two transistors Q14 and Qss are connected in parallel to which data and the signal E are input. Furthermore, the power supply V.

Between 71 and 71, E temperature MO8, which constitutes the third nogtufa
) If transistor Qsi * Qms is connected,
The gate of the transistor (hI is connected to the output terminal of the first buffer B1, and the gate of the transistor Qss is connected to the output terminal of the second buffer B), this third
Similar to the buffer circuit 61 in which the outputs of the output buffer Bs are located on the right side of the decoder 1, the output buffer 6j located on the left side of the decoder 1 is composed of transistors Ql-Qs4 similar to the output buffer 61 described above. ing.

However, in the case of this output file i1, the address datum is input to the gate of the transistor Qx4 e Qsa, and the address data is input to the gate of the transistor Qj e
Qtj m It is designed to be input to the dart of Qms. It is connected to both sides of the buffer circuit '1s4tm and outputs data corresponding to the output pin (0≦≦7).

In the above-described circuit, the output buffer 61 is not in operation when the address data A and U are "0", and the output buffer 61 is in an operating state when the address data A and U are "0". 6 Snow becomes inactive. At this time,
#! If a sense amplifier as shown in FIG. 6 is used, the current flowing through the sense amplifier 5 and output buffer 63 on the non-selective side can be reduced to approximately zero. When the above-mentioned address datum is 11", the data from the sense amplifier 5 is outputted through the output/paddle 7A 61, and in this case, the data from the sense amplifier 5 is outputted through the output/paddle 7A61, and the data from the sense amplifier 5 is outputted through the output/paddle 7A61. e' and qm'j are turned off and do not affect the output. Also, conversely, address data A1 is @0'', that is, address data A1 is 1.
The data from the sense 7 knob 5 is output through the line output buffer 61 of 1''.

For example, when the address data is also @11, if the data of the input address 5 is 11'', the transistor Q+4 is turned on, and the drain of the transistor Q1J is at the 0'' level. At this time, transistor Qt4Qs4 is off,
The drain of the terminal Qx4 is charged by the transistor Qt/ and reaches the 11m level. Then, the common connection point of the transistors Qsj and QIJ becomes @1'' level, so the transistor Q1 turns on.Furthermore, the transistor Qs4 turns on, so the transistors Qsl and Q
The common connection point of s is set to 10", thereby turning off the transistor Qsj, so that the output is set to 11".

For sense 7 nopu! 01' is coming. On the other hand, if the -signal E is 10'' and the signal E is wl, s, then if, ) Lannostar Qgs #
Q1.

Qs≦+Qm (f−) is all ν at @θ″, and the output becomes a high impedance state. This output enable signal E
, E are shown in FIG. 7, which will be described later.

The sense amplifier shown in FIG. 6 is a known differential i# type sense amplifier, which receives the r-ta from a pair of column lines -, differentially amplifies it, and then transmits its output signal to the output buffer 6Vc. In the sense amplifier 6 connected to the above-mentioned output parallel 7761, an address signal is inputted to the terminals of the E-M0B transistors Qsy to Qss, and the output buffer circuit 6m1
In sense Anne f6 connected to IC, II! MOB) An address datum is input to the darts of registers Qmv to Q■. In this way, since either one of the address datums 11 and the cores 1 becomes @lo'', the current flowing to the unselected seventh amplifier 5 becomes zero.

Figure 7 shows the circuit for output energy signals B and E. This circuit is composed of transistors Qs.about.94m, and an enable signal OE supplied from the outside is applied to the dart of the transistor Qll, and a chip operation signal CI is applied to the dart of the transistor QI4. If this chip operation signal CE is 11 levels, the chip will be in the operating state, but if the signal CE is at @Om level, the chip will be in the non-operating state, and at this time the enable signal gFi
@o”, signal E is 11”, output buffer 61e6
The output of m goes into a high impedance state. i.e. 7
Applying the above-mentioned output variation circuit #l*#m, which is controlled and driven by the address data of FIG. 5, to the circuit shown in FIG. A semiconductor memory with an unchanged read speed can be obtained without using the selective buffer circuit 61 or 61K.

#! FIG. 8 shows another configuration circuit of the output puff 7 circuit 6 shown in FIG. In the output buffer 61, the transistor in the circuit of FIG. 5 is used. ■.

Qst * Q * s Qsa is omitted, and the drain is connected to the common connection point of the transistor QhQII,
- A transistor Qas is provided, and a transistor Q
* No. 46 E1 is connected to the gate of Qs, and transistor Q1
・The circuit configuration is such that the inverted signal E1 of the signal E1 is supplied to the -5Qss dart, and in the output capacitor 7a 61, the transistor Qs4*QtjQaJ is omitted and the transistor Qa4 is provided,
fiQxl s Qst(Dl”-)K signal.
The circuit configuration is such that an inverted signal E2 of the signal E2 is supplied to the gate of the transistor Q1j e Chj.

Other circuits are #! Figure 5 and Mr. fWJ.

The above signals El, El, E2. E2td, signal EJ when you want the buffer output to be high impedance.

When E2 is set to 10 levels and signals El and E2 are set to 111'' level to send data to the outside, for example, when the address datum is @l'' and the data is sent from the memory cell array 4 on the right side of the row decoder 1 in FIG. In the case of output, the output cover and the output circuit 61 are not in the operating state, and the signal E1 becomes 11.
", signal 1 completed or 10", signal E2 becomes @0', and signal E2 becomes "1". At this time as well, the current flowing through the non-selected output buffer circuit gstct& is zero.

The signals gJ, El, E, ? shown in FIG. 8 mentioned above. .

An example of a circuit for generating the address datum 1j and the address datum 11 is shown in FIG. #I9 The circuit in Figure (b) inputs nine address data a from the outside and sends it to transistors Q44 to Qs.
s, and generates a signal A having the same phase as this address data a and a signal 4M r having the opposite phase.
It's a fufu circuit. In this circuit, No. 46 CI is the chip operation signal, and when the chip is in non-operation state, the signal CEFi''''
0'' at this time, the current flowing through the address spacer and amplifier circuits is zero.

Furthermore, if the chip is in an inoperable state and the signal CE is IIP, the address datum and T are both @0'', and the circuit is configured such that the current flowing through the output buffer circuit 61e6m also becomes zero. , ) receives the enable signal OE from the outside and creates signals EJ and EJ, and the ninth
The lower part of Figure (1) shows the signal E2.
This is a circuit for creating E2. These circuits are composed of transistors Q■ to Qyx, ) transistors Qts -Q, respectively.
A bifurcated transistor Qss consisting of sa
The address data A is in the dirt of the transistor Q.
The address data stones mentioned above are arranged in the gates of 1 and 1, respectively. Now, if the external signal OE is ・0・ and the rose address datum is @l", Ai or @0", then the signal E J = @1", E 1 = "0", E
2=@0", 17='"11, the output buffer circuit 61 is activated, and the signal OE or 0# is used to input the address data fi A, ka@0'', A ka@l'. d,
Signal Ez=@o', stone=1'1'', jJ=@l', g2
= "o", the output buffer circuit 6 is in operating state a
Make it. Also, if the signal plane is 111, the signal EJ="0
"1, Correction = A, E2 = @0', EJ = "l" and puts the buffer output in a high impedance state. Of course, when the signal CE is @0" and the entire chip is in a non-operating state,
Address 7'-/A, = "0', A, = "0'l, Kono circuit power etli-Ig1m@o", Hyakugo = @11, E
Since J=“0” and EJ=“l”, the buffer output is also in a high impedance state at this time.

Using the Sense Anne 16 shown in Figure 10 and Figure 6, this sense Anne! 5 is a semiconductor memory circuit in which, like the output parallel circuit 8, the address datum and r are controlled and driven. In this way, one output power 6
Both the sense amplifier s and the sense amplifier s are reliably activated and deactivated on the right side and the left side of the decoder 1, and excess current consumption is further reduced.

In the embodiment described above, the memory cell MCID? '
The transistor Qss of the output para 7161+6M that outputs the - data to the outside. Out of the common connection points of *Ql and *Cht-Qs4, mold is generated on the right and left side of the row decoder 1.
・~OvK compatible common connection points were connected and output to the outside. In this way, since a large capacitance of about 1509F is connected externally, the capacitance caused by the wiring connecting the transistors Qs**Qs·mQ17*Q2J to each other is so small that it can be ignored.

The above-mentioned friend transistor qri5eQs・+Qs! e
1;bj (hereinafter referred to as buffer transistor e) drives a large external load capacitance, so its driving capability is extremely large, and for example, the channel length is 4 μm, and the channel length is approximately 2000 μm. Therefore, the driving capability of the transistors in the previous stage for driving the buffer transistors Qss and Qms is also set to be large. Therefore, even if the pads and 77 circuits 6 located on the right and left sides of the row decoder 1 are connected in the preceding stage of the buffer transistor Qms* (hs), the increase in the wiring capacity added for the connection is due to the buffer transistor dirt. It's not that big compared to the capacitance.Tsumashi, Power Funa... Transistor Q
sieQ*・eQsJ Even if the output buffer 61*Im is connected at the front stage of eQmj, the effect on the overall memory read speed is very small.

FIG. 11 shows a memory circuit connected to the front stage of the above-mentioned 9) tsufatotransnosta, and shows the memory circuit connected to the front stage of the above-mentioned 9) tsufatannosta. Either one of s' + (hs-) can be omitted, and this is used as a buffer transistor of 8. In this one memory circuit, when address datum 1 is 11", the memory on the right side of row decoder 1 Cell array 4 is selected, and data of 8 pins, for example, is sent to sense sensor, f5, output 7J', and output 6).
, are outputted to the outside via the FAT2NOSTAR 8. When the address data A-E-0' is '1', the memory cell 4 on the left side of the row decoder 1 is selected, and the 8-bit data is sent to the sense amplifier f5 and output. It is output to the outside via the 7A 63 and the buffer transistor 8. As shown in ?T, when the address datum l is
When the address data is 1", output #12>5 operates, and when the address data is 11", output #14 and #12>5 operate.

Figure 12 shows an example of the configuration of the output four-way buffer circuit 6 in the case of Figure 11. The circuit 8 is composed of E-type buffer transistors Qsi+Qss, and each f-) of the buffer transistors Q@@+Qmm has address data A, , A.

Output cover and F circuit 61 selectively driven by.

63 is connected. The output buffer circuits 6, . 6
m is the transistor Qsy ~ Qss + QI? '〜
Q...' and a common transistor Qs*"Qtsn, and the signal E1 is input to the ff-) of each transistor.
．． E1. E2. E2 is obtained by the signal generating circuit of FIG. 9 described above. These signals are FJ='l"
, tl="0", E2="0", and gz="i", the output cover 61 located on the right side of the decoder 1 is in operation.

The data from the memory cell array 4 detected by the sense amplifier 6 is transmitted to the buffer transistor 8 via the transistors Qss to Qva.
It is sent as k (0≦ and ≦7). At this time, the gates of transosts Qss' to Q-kai' in the output paddle 61 are all @O'', so the output paddle F 6s becomes non-powered and does not affect the output paddle 7a 61. On the contrary, the signal is E1 = "0', WJ = @l", ii:j = @l
', Ej=''O'', the output buffer 61 is inactive and the output buffer 63 is active, so data from the memory cell array 4 located on the left side of the row decoder 1 is transferred to the output buffer 63 and the buffer transistor 8. At this time, as mentioned above, the output cover, Fa 61, is output and does not affect the Fa 6 mushroom.Furthermore, when the buffer output is made to have a zero impedance, the signal B1=”O#, E1=1, E2==O
', EJ="l" and f of buffer transistor 8
-) becomes "0", so the output becomes a high impedance state.

FIG. 13 shows the circuit of FIG. 11 with additional address data A.
, A shows a semiconductor memory capable of controlling and driving not only the state cover 61.6g but also the sense amplifier 5. This circuit also has the same operation and effect as described above.

However, the present invention can also be applied to ROM (Read Only Memory). That is, conventional ROMs in which load circuits are connected to all column lines have the same problem as RAMs. Therefore, if the present invention is applied and the selection of the right and left side circuits of the row decoder 1 is switched and controlled using the address data A, lAi, the same effect as that of the RAM described above can be expected. This is particularly effective in ROM. In addition, when recharging column lines for dynamic operation, for example, if the memory cell array 4 on the right side of the row decoder is selected, if only the memory cell array 4 on the right side is recharged, the current consumption can be significantly reduced. can be reduced.

As explained above, according to the present invention, sense amplifiers and output buffers are connected corresponding to memory cell arrays of predetermined bits distributed on the right and left sides of a decoder, and data of memory cells located on the left and right sides of this decoder are connected. Wires are connected between the corresponding output buffers to be output, and the left and right output buffers are selectively driven according to the address data input to the above decoder, and the data from the memory cell array is transferred externally. Since the circuit configuration is such that the current consumption flowing through the load circuit connected to the column line can be significantly reduced, it is also possible to provide a semiconductor memory that can prevent read speed from decreasing due to wiring capacitance.

[Brief explanation of the drawing]

Figure 1 is a circuit configuration diagram of a conventional RAM, Figure M2 is a circuit configuration diagram of the memory cell in Figure 1, Figure 3 is a circuit configuration diagram of a conventional RAM, and Figure 4 is an embodiment of the present invention. FIG. 5 is a detailed circuit diagram of the output cover and amplifier of FIG. 4, FIG. 6 is a detailed circuit diagram of the sense amplifier of FIG. 4, and FIG. 7gA is a circuit diagram of the RAM. 5 is a block diagram of the If No. E, I generation circuit. A block diagram of the signals gx, x2.
12 is a detailed circuit diagram of the output buffer of FIG. 11, and FIG. 13 is a circuit diagram of the RAM according to still another embodiment of the present invention. -da, l... Column selection circuit, 4... Memory cell array, 5... Sense amplifier, 6... Output buffer, 1... Load circuit, 8...
...Buffer transistor, Ql~Qt・swQs'~
Qtomia' g Q4m'Q@7'~Q9a'...Transistor, WL...Row line, (J) *Qn・
...Column line, MC...Memory cell, MC. A1...Address data. Applicant's agent Patent attorney Suzue Takehiko No. 5Ia υr No. 61W s 11!7 Figure 11811 No. 9 @ (a)

Claims (6)

[Claims] (1) A decoder means for receiving address data and specifying a predetermined location, a plurality of memory cells arranged on the left and right sides of the decoder means in correspondence with predetermined spaces, respectively, for storing data; It is equipped with a plurality of sense amplifiers for detecting data from the cells, and a control means arranged corresponding to the sense amplifiers and selectively driven based on the data address data detected by these sense amplifiers. Q7 from the memory cell specified by p
'-The armpit that was selected and driven. A semiconductor model that outputs to the outside through the Noah group. (2) The semiconductor memory according to the present invention, wherein the control means includes a control signal generation circuit that receives an enable signal from the outside and generates a signal for selecting the output buffer #F. (3) Data of the same output bit at different addresses is stored in the left memory cell group and the right memory cell group of the decoder means, and the control means stores the data of the left memory cell group according to the address data. Claim 1, further comprising means for selecting and operating one of the output cover corresponding to the NOR group and the output cover corresponding to the right side memory cell group 77 group. semiconductor memory. (4) In output buffer groups corresponding to memory cell groups arranged on the left and right sides of the decoder means, each output buffer corresponds to the left and right memory cell groups corresponding to the predetermined bit;
3. The semiconductor memory according to claim 18i, wherein the output ends of the semiconductor memory are connected to each other. (5) In the group of nine output pads corresponding to the memory cell # disposed at the seat of the decoder means, each output pad corresponding to the left and right memory cell groups corresponding to the predetermined bit, the final output pad included in the pad. A semiconductor memory in which one of the buffer transistors in a stage is omitted and a circuit is commonly connected to the other buffer transistor to send out a predetermined pit output. (6) The control means is further characterized in that it selectively drives one of the sense amplifier groups corresponding to the memory cell groups disposed on the left and right sides of the decoder means using the address data. A semiconductor memory according to any one of the first and third scope of the patent.