JPH0217878B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory with reduced current consumption.

Figure 1 shows the circuit configuration of a conventional RAM. this
In RAM, address data A ₀ , ₀ ,...
Due to the combination of A _i and _i , the row decoder 1 to which these address data are input is connected to one row line WL
Select. In addition, the column decoder 2 selects the output line DOL of the column decoder by a combination of address data A _j , _j , ... A _o , _o , and the column selection circuit 3 selects any pair of column lines Q _o and _o from the column lines CL. And the row line selected like this
WL, column lines Qo, _o select one out of the memory cell array 4 corresponding to the output bits _O0 to _O7 , respectively _.
Data in each memory cell MC is detected by a sense amplifier 5, and the detected data is amplified by an output buffer 6 and sent out as output bits _O0 to _O7 .

Details of the above-mentioned memory cell MC are shown in FIG. 2. The area surrounded by the broken line corresponds to each memory cell MC, and this memory cell is a well-known static type consisting of cross-coupled flip-flops.
It is a RAM cell. That is, the power supply V _c (e.g.
5V) and the power supply V _s (e.g. 0V) and the enhancement type (E type) with a resistor R1 connected in series.
MOS transistor Q ₁ and the above power supplies V _c and V _s
It has a resistor R2 and an enhancement type MOS transistor _Q2 connected in series between them, and the gates of these transistors _Q2 and _Q1 are transistors.
It is connected to a connection point A between Q ₁ and a resistor R1, and a connection point B between a transistor Q ₂ and a resistor R2. Also,
These connection points A and B are connected to column lines Q _{o and o} via enhancement type MOS transistors Q ₃ and Q ₄ respectively.
The gates of transistors Q ₃ and Q ₄ are respectively connected to row line WL.

In the memory cell MC configured in this way, when the connection point A is at the "1" level (for example, 5V), the transistor _Q2 is turned on, and the connection point B is turned on.
becomes the "0" level (for example, 0V) and the transistor _Q1 is turned off, so that the points A and B are stably held at the "1" and "0" levels, respectively. now,
If this memory cell MC is selected, the row line
When WL becomes "1", transistors Q ₃ and Q ₄ are turned on, data at points A and B are transmitted to column lines Q _{o and o} , and the column selection circuit 3 selects the pair of column lines Q _o and _o . If selected, the data on this column line Q _o , _o is detected by the sense amplifier 5 and sent out by the output buffer circuit 6 .

Note that, as shown in FIG. 1, a load circuit 7 is connected to each of the column lines Q _o and _o . This is the column line
If the memory is of a type that precharges Q _{o and o} , a precharge circuit is connected as a load circuit, and when a precharge signal is given, all column lines are
Q _o and _o are uniformly precharged to a predetermined potential level. Alternatively, as shown in FIG. 2, a load transistor _Q5 is simply connected between the power supply _Vc and the column lines _Qo , _o , and this is used as a load circuit. In these load circuits 7, the potential level of the column lines Q _{o and o} falls too low, and when the memory cell MC is selected and data is read out, the "1" level of the memory cell MC becomes the "0" level, resulting in an error write. Since this may occur, it serves to maintain the "0" level of the column lines Q _o and _o at a certain intermediate potential level.
Furthermore, if the resistance values of resistors R1 and R2 in the memory cell MC are reduced, the current consumed by the memory cell MC increases, so these resistance values are made as large as possible. For this reason, it takes a very long time to charge the column lines Q _o and _o using only the resistors R1 and R2, so a load circuit is used to compensate for this.

However, the load circuit 7 described above has all column lines Q _o , _o
For example, transistors Q ₃ and Q ₄ are turned on by the row line WL even when the column lines Q _{o and o} are not selected, so that the load circuit 7 connected to all column lines Q _o and _o is activated. become. Therefore, the current supplied by this load circuit 7 becomes very large, and since the load circuit 7 also supplies current to non-selected column lines, a wasteful current flows. The memory circuit shown in FIG. 3 has been designed to reduce the current flowing through these load circuits 7 as much as possible.

In the circuit shown in FIG. 1 described above, the memory cell array 4 corresponding to 8 bits of output is arranged on each side of the row decoder 1 for 4 bits, but in the circuit shown in FIG. Cell arrays 4 are arranged on both sides of row decoder 1 for 8 bits each. For example, depending on address data A _i , when this address data A _i is “1”, the right 8 bits of row decoder 1 are selected, and when address data A _i is “0”, the left 8 bits of row decoder 1 are selected. are selected and each is output. Then, this address data A _i is “1”
When , the row line WL on the right side of the selected row decoder 1
becomes "1", and all row lines WL on the left become "0". Therefore, the data in memory cell MC is transferred to the column line.
For example, the transistors Q ₃ and Q ₄ in FIG. 2 that transmit data to Q o and o are cut off in all the memory cell arrays 4 on the left side, and the column lines Q _{o and o} are all charged _to the "1" level, so the column lines on the left side No current flows from the load circuit 7. Therefore, compared to the circuit shown in FIG. 1, the current flowing out from the load circuit 7 in the circuit shown in FIG. 3 is halved, and the current consumption can be significantly reduced.

In FIG. 3 described above, a transistor Q ₆ to which address data A _i is input into the gate and a transistor Q ₇ to which address data _i is input to the gate
When address data A _i is "1", transistor Q ₆ is turned on, and data in memory cell array 4 on the right side of row decoder 1 is transmitted to sense amplifier 5 . At this time, transistor Q ₇ is off, preventing data from the right memory cell array 4 from flowing to the left, and reducing the load capacitance up to the sense amplifier 5. When address data A _i is "0", transistor Q ₆ is turned off, transistor Q ₇ is turned on, and data in memory cell array 4 on the left side of row decoder 1 is transmitted to sense amplifier 5 . However, in the circuit configuration shown in FIG. 3, the row decoder 1
connects the right and left memory cell arrays 4 of the
In other words, the transistor Q ₆ corresponding to the output bit,
It is necessary to connect the corresponding drains of _Q7 . For example, if such a circuit is 5mm square
If fabricated on an IC chip, according to the inventors' experience, the wiring for these transistors alone would be 2 mm.
Requires length. Furthermore, two wires are required for transmitting data on the column lines Q _o and _o to the sense amplifier 5, and these wires alone occupy a considerable chip area. This means that in the circuit configuration as shown in FIG. 3, the load capacitance between the sense amplifier 5 and the column selection circuit 3 becomes extremely large. Furthermore, the dimensions of the transistors constituting the memory cell MC must be made extremely small in consideration of the chip size, which reduces the driving ability and thus slows down the read speed of the memory. Furthermore, there was a drawback that the chip size became large due to the above-mentioned wiring connections.

The present invention was made in order to eliminate the above-mentioned drawbacks, and it connects sense amplifiers and output buffers corresponding to memory cell arrays of predetermined bits arranged on the left and right sides of a decoder, and also connects the sense amplifiers and output buffers in correspondence with the left and right output buffers of this decoder. By connecting the output bits of the memory cell array with wires, and selecting and controlling the left and right output buffers according to the address data input to the decoder, data from the memory cell array is transmitted to the outside. It is an object of the present invention to provide a semiconductor memory which can significantly reduce the current consumption flowing through a load circuit connected to a semiconductor memory and which can prevent a reduction in read speed due to wiring capacitance.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. In the memory circuit shown in FIG. 4, the same reference numerals are used for the same parts as described above, and a brief description thereof will be given. That is, the circuit of FIG. 4 is the same as the circuit of FIG. 3 in that the memory cell arrays 4 on the right and left sides of the row decoder 1 are selected by, for example, address data A _i . for that,
The current flowing through the load circuit 7 is half that of the conventional circuit shown in FIG. However, this circuit is
The memory cell arrays 4 on the left and right sides of the row decoder 1 are not connected before inputting to the sense amplifier 5 as in the circuit shown in FIG. A sense amplifier 5 and an output buffer circuit 6 are connected corresponding to each of the 8 bits. Therefore, the number of sense amplifiers 5 and output buffers 6 is doubled compared to the conventional circuit. The outputs of the eight buffers 6 arranged on the right and left sides of the decoder 1 are connected to each other corresponding to the output bits _O0 to _O7 to be sent to the outside. Usually, a large capacitor of about 150 _pF is connected to the output of an IC as an external load capacitor. Therefore, as mentioned above, the load capacitance caused by the wiring connecting the output buffers 6 to each other is small enough to fall within the error range compared to the external load capacitance of 150 _pF , and the The load capacitance caused by the connection does not slow down the read speed for reading data from the memory cell.

In addition, in the circuit shown in FIG. 4, by controlling the output buffer 6 using the address data A _i , _i , data from the memory cell array 4 on the right side of the row decoder 1 or data from the memory cell array 4 on the left side can be controlled. It determines and outputs the In this way, by controlling the output buffer 6 with the address data A _i , _i , the current flowing to the load circuit 7 flows only to the right half of the load circuit 7 or the left half of the load circuit 7, resulting in a significant reduction in current consumption. Become.

FIG. 5 shows an example of an output buffer circuit controlled and driven by the address data A _i , _i mentioned above.
In the figure, 6 ₁ indicates an output buffer located on the right side of the row decoder 1, and 6 ₂ indicates an output buffer located on the left side. In this circuit 6 ₁ , an enhancement type (E type) MOS transistor Q ₈ whose gate receives address data A _{i and} a depletion type (D type) MOS transistor whose gate is connected to the source are connected between the power supplies V _{s and} V c . A transistor Q ₉ and an E-type MOS transistor Q ₁₀ whose gate is supplied with data from the sense amplifier 5 are connected in series. An E-type MOS transistor Q12 whose gate is connected to the common connection point of these transistors _Q9 and _Q10 and whose source is connected to _the power supply _Vs , and this transistor
A D-type MOS transistor _Q11 is provided whose source and gate are connected to the drain of _Q12 and whose drain is connected to the power supply _Vc . In addition, transistors Q ₁₃ to _{Q 16} are connected in series between power supplies V _c and V _s ,
Address data A _i is input to the gate of the E-type MOS transistor _Q13 , and the E-type MOS transistor _Q14
The output signal E from the output enable circuit is input to the gate of the output enable circuit. This output enable circuit consists of 1
This is used when the outputs of multiple memories are connected to one bus line.The output buffer of the selected memory is operated to output data, and the outputs of non-selective memories are put in a high impedance state and sent to the bus line. This is a circuit that eliminates the influence of
It is normally included in normal semiconductor memory. Further, the gate of the D-type MOS transistor Q ₁₅ is connected to the transistors Q ₁₁ and Q ₁₂ that constitute the second inverter I ₂ .
The gate of the E-type MOS transistor _Q16 is connected to the interconnection point of _the transistors _Q9 and _Q10 constituting the first inverter I1. The transistors Q ₁₅ and Q ₁₆ constitute the first buffer B ₁ . This transistor Q ₁₅ , Q ₁₆
E-type MOS transistors Q ₁₇ and Q ₁₈ are provided between the interconnection point of and the power supply V _s when an inverted signal of address data A _i and an inverted signal of the signal E are respectively input to the gates _. ing. Similarly, a transistor Q ₁₉ is connected between the power supplies V _c and V _s .
~Q ₂₂ is connected in series, E type MOS transistor
Address data A _i is input to the gate of _Q19 ,
The signal E is input to the gate of the E-type MOS transistor _Q20 . In addition, D-type MOS transistor
The gate of Q ₂₁ is connected to the interconnection point of the transistors Q ₉ and Q ₁₀ , and the gate of the E-type MOS transistor Q ₂₂ is connected to the interconnection point of the transistors Q ₁₁ and _{Q 12 .}
Configure the second buffer B ₂ at Q ₂₂ . Between the interconnection point of these transistors Q ₂₁ and Q ₂₂ and the power supply V _s , there are transistors whose gates are respectively inputted with the address data _i and the signal as described above.
Q ₂₄ and Q ₂₃ are connected in parallel. In addition, the power
Between V _c and V _s is an E type constituting the third buffer _B3 .
MOS transistors Q ₂₅ and Q ₂₆ are connected,
The gate of transistor Q ₂₅ is connected to the first buffer B ₁ mentioned above.
The gates of the transistors Q ₂₆ are respectively connected to the outputs of the second buffer B ₂ , and the output of the third buffer B ₃ is the output of the buffer circuit 6 ₁ located on the right side of the decoder 1 . becomes.

Similarly, the output buffer 6 ₂ located on the left side of the decoder 1 is composed of transistors Q ₈ ′ to Q ₂₆ ′ similar to the output buffer 6 ₁ described above. just,
In the case of this output buffer ₆₂ , address data A _i is input to the gates of transistors Q ₁₇ ′, Q ₂₄ ′, and address data _i is input to the gates of transistors Q ₈ ′, Q ₁₃ ′,
It is designed to be input to the gate of Q ₁₉ ′. Both outputs of the buffer circuits 6 ₁ and 6 ₂ are connected and output data corresponding to output bit O _k (0≦k≦7).

In the buffer circuit configured as above, when the address data A _i is "1", the output buffer ₆₁ is in the operating state, while the address data
Since A _i becomes "0", the output buffer 6 ₂ becomes inactive. At this time, if a sense amplifier as shown in FIG. 6 is used, the current flowing through the sense amplifier 5 and the output buffer ₆₂ on the non-selective side can be reduced to approximately zero. When the address data A _i mentioned above is "1", the data from the sense amplifier 5 is output through the output buffer ₆₁ , and at this time, since it is "0" at the gates of the transistors _Q25 ' and _Q26 ', both transistors Q ₂₅ ' and _Q26 ' are cut off and do not affect the output. Conversely, when the address data A _i is "0", that is, the address data _i is "1", the data from the sense amplifier 5 is outputted through the output buffer 6 ₂ . For example, when the address data _i is "1" and the data of the sense amplifier 5 is "1", the transistor Q ₁₀ ' is turned on and the drain of the transistor Q ₁₀ ' becomes the "0" level. At this time, transistors Q ₁₂ ′ and Q ₁₆ ′ are turned off, and the drain of transistor Q ₁₂ ′ is connected to the
It is charged by Q ₁₁ ' and reaches the "1" level. Then, since the common connection point of transistors Q ₁₅ ′ and Q ₁₆ ′ becomes “1” level, transistor Q ₂₅ ′ is turned on. Further, since transistor Q ₂₂ ' is turned on, the common connection point of transistors Q ₂₂ ' and Q ₂₁ ' becomes "0", and as a result, transistor Q ₂₆ ' is turned off, so that "1" appears at the output. sense amplifier 5
If the data from is "0", "0" will appear in the output. On the other hand, if the signal E is "0" and the signal is "1", the transistors Q ₂₅ , Q ₂₆ , Q ₂₅ ',
All gates of Q ₂₆ ' become "0", and the output becomes a high impedance state. A circuit for generating this output enable signal E is shown in FIG. 7, which will be described later.

The sense amplifier shown in FIG. 6 is a known differential type sense amplifier, which receives data from a pair of column lines Q _{o and o} , performs differential amplification, and then transmits the output signal to the output buffer 6. The aforementioned output buffer 6 ₁
In the sense amplifier 5 connected to the output buffer circuit 62, the address signal A _i is input to the gates of the E-type MOS transistors _Q27 to _Q29 , and in the sense amplifier 5 connected to the output buffer circuit ₆₂ , the E-type MOS transistors _Q27 to Q29 are input.
Address data _i is input to the gate of _Q29 . In this way, one of the address data A _i and _i becomes "0", so the current flowing through the unselected sense amplifier 5 becomes zero.

FIG. 7 shows a circuit for generating the output enable signal E. This circuit uses transistor Q ₃₀ ~
An enable signal supplied from the outside is applied to the gate of the transistor Q ₃₁ , and a chip operation signal CE is applied to the gate of the transistor _{Q 34 .} If the chip operation signal CE is at the "1" level, the chip is in the operating state, but if the signal CE is at the "0" level, the chip is in the inactive state, and at this time, the enable signal E is "0" and the signal is "1". , output buffer 6 ₁ ,
The output of 6 ₂ becomes a high impedance state. That is, the output buffer circuits 6 ₁ and 6 ₂ controlled and driven by the address data shown in FIG.
If applied to the circuit shown in the figure, a semiconductor memory can be obtained in which the current flowing through the load circuit 7 is halved, the current consumption does not flow into the unselected buffer circuits 6 ₁ or 6 ₂ , and the read speed does not change.

FIG. 8 shows another configuration circuit of the output buffer circuit 6 of FIG. 4. In FIG. In the output buffer 6 ₁ , the transistors Q ₁₃ , Q 17 , Q ₁₇ , and
Q ₁₉ and Q ₂₄ are omitted, and an E-type MOS transistor Q ₄₃ is used, whose drain is connected to the common connection point of the transistors Q ₉ and Q ₁₀ , whose source is connected to the power supply V _s , and whose gate receives address data _i . Furthermore, the circuit configuration is such that the signal E1 is supplied to the gates of the transistors Q ₁₄ and Q ₂₀ , and the inverted signal ₁ of the signal E1 is supplied to the gates of the transistors Q ₁₈ and Q ₂₃ . ₁₃ ′, Q ₁₇ ′, Q ₁₉ ′, Q ₂₄ ′ are omitted, transistor Q ₄₃ ′ is provided, and transistor Q ₁₄ ′,
Signal E2 is applied to the gate of Q ₂₀ ′, transistor Q ₁₈ ′,
The circuit configuration is such that an inverted signal 2 of the signal E2 is supplied to the gate of _Q23 '. The other circuits are the same as those shown in FIG.

The above signals E1, 1, E2, 2 are the signal E when you want to make the buffer output high impedance.
When transmitting data to the outside by setting signals 1 and E2 to "0" level and signals 1 and 2 to "1" level, for example, address data A _i is "1" and the fourth
When data is output from the memory cell array 4 on the right side of the row decoder 1 in the figure, the output buffer circuit ₆₁ is activated, and the signal E1 is "1", the signal 1 is "0", and the signal E2 is "0". ”, signal 2 is “1”
becomes. At this time as well, the current flowing through the non-selected output buffer circuit ₆₂ becomes zero.

Signals E1, 1, E shown in FIG. 8 mentioned above
An example of a circuit for generating 2, 2 and address data A _i , _i is shown in FIG. The circuit shown in FIG. 9b shapes the waveform of address data a _i input from the outside using a circuit consisting of transistors Q ₄₄ to Q ₅₈ , and outputs a signal A _i in phase with this address data a _i and a signal in reverse phase.
This is an address buffer circuit that creates A _i . In this circuit, the signal CE is the chip operation signal, and when the chip is inactive, the signal CE is "0", and at this time the current flowing through the address buffer circuit is zero.
Furthermore, if the chip is in a non-operating state and the signal CE is "0", both address data A _i and _i become "0",
The circuit is configured so that the current flowing through the output buffer circuits 6 ₁ and 6 ₂ is also zero. The upper stage of FIG. 9a receives the enable signal from the outside and receives the signal E1,
The lower part of FIG. 9a is a circuit that receives the above-mentioned signal OE and creates signals E2, 2. These circuits consist of transistors Q ₅₉ to Q ₇₁ , respectively
It is composed of transistors _Q72 to _Q84 . Further, the address data A _i is applied to the gate of the transistor _Q63 , and the address data _i is applied to the gate of the transistor _Q76 . Now, if the external signal is "0", address data A _i is "1", and _i is "0", then the signals E1 = "1", 1 = "0", E2 = "0", 2 =
When the signal OE becomes "1", the output buffer circuit ₆₁ is activated, and when the signal OE becomes "0", the address data is
If A _i is “0” and _i is “1”, the signal E1 is “0”,
E1="1", E2="1", 2="0",
The output buffer circuit ₆₂ is put into operation. Also, if the signal is “1”, the signal E1 is “0”,
E1="1", E2="0", 2="1" and the buffer output is brought into a high impedance state.
Of course, when the signal CE is "0" and the entire chip is inactive, the address data A _i = "0", _i =
becomes “0”, and from this circuit the signal E1="0",
Since E1="1", E2="0", and 2="1", the buffer output is also in a high impedance state at this time.

FIG. 10 shows a semiconductor memory circuit using the sense amplifier 5 shown in FIG. 6, in which the sense amplifier 5 is controlled and driven by address data A _i , _i in the same way as the output buffer circuit 6. In this way, both the output buffer 6 and the sense amplifier 5 can operate reliably on the right and left sides of the decoder 1.
It becomes inactive and the extra current consumption is further reduced.

In the embodiment described above, among the common connection points of the transistors Q ₂₅ , Q ₂₆ , Q ₂₅ ′, Q ₂₆ ′ of the output buffers 6 ₁ and 6 ₂ that output the data of the memory cells MC to the outside, the row decoder 1 The common connection points corresponding to output bits O ₀ to _{O 7} on the right and left sides of the circuit were connected together for output to the outside. In this way, a large capacitance of about 150 _pF is connected externally, so the capacitance caused by the wiring connecting transistors Q ₂₅ , Q ₂₆ , Q ₂₅ ′, and Q ₂₆ ′ is negligibly small. be.

The above-mentioned transistors Q ₂₅ , Q ₂₆ , Q ₂₅ ′,
Since Q ₂₆ ' (hereinafter referred to as a buffer transistor) drives a large external load capacitance, its driving capability is extremely large.For example, the channel length is 4 μm and the channel width is approximately 2000 μm. Therefore, the driving capability of the transistors in the previous stage for driving the buffer transistors Q ₂₅ and Q ₂₆ is also set to be large. Therefore, even if the buffer circuits 6 located on the right and left sides of the row decoder 1 are connected before the buffer transistors Q ₂₅ and Q ₂₆ , the increase in wiring capacitance added due to the connection is due to the gate capacitance of the buffer transistors. It's not that big compared to. In other words, buffer transistor Q ₂₅ ,
Even if the output buffers 6 ₁ and 6 ₂ are connected before Q ₂₆ , Q ₂₅ ′, and Q ₂₆ ′, the effect on the overall memory read speed is extremely small.

Figure 11 shows _a memory circuit in which _the preceding stage of the buffer transistors described above is connected.
Either Q ₂₅ ′ or Q ₂₆ ′ can be omitted, and this is shown as the buffer transistor of block 8. In this memory circuit, address data
When A _i is "1", the memory cell array 4 on the right side of the row decoder 1 is selected, and 8-bit data, for example, is outputted to the outside via the sense amplifier 5, the output buffer ₆₁ , and the buffer transistor 8.
Address data A _i is “0”, which means address data
When A _i is "1", the memory cell 4 on the left side of the row decoder 1 is selected, and 8-bit data is outputted to the outside via the sense amplifier 5, output buffer ₆₂ and buffer transistor 8. in this way,
When address data A _i is “1”, output buffer 6
₁ operates, and when the address data _i is "1", the output buffer ₆₂ operates.

FIG. 12 shows an example of the configuration of the output buffer circuit 6 in the case of FIG. 11. The block 8 is composed of E-type buffer transistors Q ₈₅ and Q ₈₆ ,
Output buffer circuits 6 ₁ and 6 ₂ selectively driven by address data A _i and _i are connected to the respective gates of buffer transistors Q ₈₅ and Q ₈₆ . These output buffer circuits 6 ₁ and 6 ₂ are common transistors with transistors Q ₈₇ to _{Q 98} and Q ₈₇ ′ to _{Q 98} ′.
The signals E1, 1, E2, 2, which are composed of Q ₉₉ to Q ₁₀₂ and input to the gates of each transistor, are obtained by the signal generating circuit shown in FIG. 9 described above. These signals are E1=“1”, 1=
When E2="0" and E2="1", the output buffer ₆₁ located on the right side of the decoder 1 is activated. The data from the memory cell array 4 detected by the sense amplifier 5 is transmitted to the transistor
It is transmitted to the buffer transistor 8 via Q ₉₅ to Q ₉₈ and sent out as an output bit O _k (0k7). At this time, since the gates of transistors Q ₉₅ ′ to _{Q 98} ′ in the output buffer 6 ₂ are all “0”, the output buffer 6 ₂ becomes non-powered and does not affect the output buffer 6 ₁ . Conversely, the signal is E1
= “0”, 1 = “1”, E2 = “1”, 2 = “0”
When , output buffer 6 ₁ is inactive and output buffer 6 ₂ is active, so row decoder 1
Data from the memory cell array 4 located on the left side of the memory cell array 4 is outputted through the output buffer ₆₂ and the buffer transistor 8. At this time too,
Similarly to the above, the output buffer 6 ₁ does not affect the output buffer 6 ₂ . Furthermore, when making the buffer output high impedance, signal E1=
“0”, 1=1, E2=“0”, 2=“1”, and the gate of the buffer transistor 8 becomes “0”, so the output becomes a high impedance state.

FIG. 13 shows a semiconductor memory in which not only the output buffers 6 ₁ and 6 ₂ but also the sense up 5 can be controlled and driven by the address data A _i and _i using the circuit of FIG. 11. This circuit also has the same operation and effect as described above.

Note that although the above-described embodiments have been described with reference to RAM, the present invention can also be applied to ROM (read only memory). In other words, for conventional ROMs in which load circuits are connected to all column lines,
A similar problem occurs with RAM. Therefore, if the present invention is applied to switch and control circuit selection on the right and left sides of the row decoder 1 using address data A _i and _i , the same effect as that of the RAM described above can be expected. For example, this is particularly effective in dynamic type ROM. Furthermore, when precharging column lines for dynamic operation, for example, if the right memory cell array 4 of the row decoder 1 is selected, current consumption can be significantly reduced by precharging only the right memory cell array 4. .

As explained above, according to the present invention, sense amplifiers and output buffers are connected corresponding to memory cell arrays of predetermined bits arranged on the right and left sides of a decoder, and data of memory cells located on the left and right sides of this decoder are connected. Corresponding output bits of the output buffers to be output are connected by wiring, and the left and right output buffers are selectively driven by the address data input to the decoder to send data from the memory cell array to the outside. Accordingly, it is possible to provide a semiconductor memory that can significantly reduce the current consumption flowing through a load circuit connected to a column line, and also prevent a reduction in read speed due to wiring capacitance.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a conventional RAM, Fig. 2 is a circuit diagram of a memory cell shown in Fig. 1, Fig. 3 is a circuit diagram of a conventional RAM, and Fig. 4 is an embodiment of the present invention. FIG. 5 is a detailed circuit diagram of the output buffer of FIG. 4, and FIG. 6 is a circuit diagram of the RAM.
7 is a block diagram of the signal E and generation circuit used in the circuit of FIG. 5, FIG. 8 is a block diagram of another embodiment of the output buffer circuit, FIG. 9 is a configuration diagram of a signal E1, E2, 1, 2 generation circuit used in the circuit of FIG. 8, FIGS. 10 and 11 are circuit configuration diagrams of a RAM according to another embodiment of the present invention, FIG. 12 is a detailed circuit diagram of the output buffer shown in FIG. 11, and FIG. 13 is a circuit diagram of a RAM according to still another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Row decoder, 2... Column decoder, 3... Column selection circuit, 4... Memory cell array, 5... Sense amplifier, 6... Output buffer, 7... Load circuit, 8... Buffer transistor, _Q1 to _Q102 , _Q8 ′～Q ₂₄ ′,
Q ₄₃ ′Q ₈₇ ′～Q ₉₈ ′...Transistor, WL...Row line, Q _o ,
Q _o ...column line, MC...memory cell, A _i , _i ...address data.

Claims (1)

[Scope of Claims] 1. A decoder means for receiving address data and specifying a predetermined location, a memory cell group consisting of a plurality of memory cell arrays each having a plurality of memory cells for storing data, and each of the memories. A plurality of sense amplifiers arranged corresponding to the cell array to detect data from the memory cells, and a plurality of output buffers arranged corresponding to each of the above sense amplifiers to output the data detected by the corresponding sense amplifier. It comprises an output buffer group consisting of a circuit, and a control means for selectively driving the plurality of output buffer circuits according to the address data, and the data from the memory cell designated by the decoder means is externally transmitted through the selectively driven output buffer circuit. Semiconductor memory that outputs data to 2. The semiconductor according to claim 1, wherein the control means includes a control signal generation circuit that receives an external enable signal and generates a signal for selectively driving the output buffer group. memory. 3. Data of the same output bit at different addresses is stored in a left memory cell group and a right memory cell group of the decoder means, and the control means uses the address data to store the output buffer group corresponding to the left memory cell group. 2. The semiconductor memory according to claim 1, further comprising means for selectively driving either one of the output buffer group corresponding to the memory cell group on the right side. 4. Claims characterized in that, in the output buffer group corresponding to the memory cell group, the output ends of each output buffer corresponding to a plurality of memory cell groups corresponding to a predetermined output bit are connected to each other. The semiconductor memory according to item 1. 5. In the output buffer group corresponding to the memory cell group, one of the final stage buffer transistors included in each output buffer corresponding to a plurality of memory cell groups corresponding to a predetermined output bit is left and the rest are omitted. 2. A semiconductor memory according to claim 1, wherein circuits are commonly connected to one buffer transistor to send out a predetermined bit output. 6. The semiconductor memory according to claim 1, wherein the control means further selectively drives a sense amplifier group corresponding to the memory cell group based on the address data.