JP3379970B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, in which an internal circuit is controlled to be active or inactive by a signal change of a two-system chip select signal. It concerns the device. 2. Description of the Related Art FIG. 2 is a block diagram showing a conventional semiconductor memory device, wherein 1 is a row address input, 2 is a row address buffer for amplifying or inverting the row address input 1, and 3 is a row address buffer. A row address decoder for decoding a row address signal applied to a row address input 1, a column address input 4, a column address buffer 5 for amplifying or inverting the column address input 4, and a column address buffer 6. A column address decoder for decoding a column address signal applied to the input 4; a memory cell array 7 in which memory cells for storing information are arranged in a matrix; 8 a multiplexer;
Reference numeral 9 denotes a sense amplifier for sensing and amplifying a small-amplitude read voltage, 10 denotes an output data buffer for amplifying the output of the sense amplifier 9 to a level that is further taken out of the semiconductor memory device, 11 denotes a read data output terminal, and 12 denotes Write data input terminal, 13 is write data input 1
2, an input data buffer for amplifying the signal given to 2, a chip select input terminal 14, a read / write control input terminal 15, and a sense amplifier 16 according to chip select / non-select and data read / write mode. 9,
The read / write control circuit controls the output data buffer 10, the write data buffer 13, and the like. FIG. 3 is a circuit diagram showing a memory cell of the semiconductor memory device shown in FIG. 2 and its peripheral portion. Here, for simplicity, a memory cell array having a two-row and two-column structure is shown. ing. In the figure, 20a and 20b,
21a and 21b are corresponding bit line pairs, respectively.
And 23 are word lines connected to the output point of the row address decoder 3, and 24a, 24b, 24c and 24d are at the intersections of the word lines 22 and 23 with the bit line pairs 20a and 20b and the bit line pairs 21a and 21b. One end of each of the arranged memory cells 25a, 25b and 26a, 26b is at the power supply potential 18, and the other end is at the bit line 20a, 20b, 2b.
Bit line loads connected to 1a and 21b, 27
The gates a, 27b, 28a and 28b receive the output signal of the column address decoder 6 shown in FIG. 2 and have their drain and source connected to bit line pairs 20a, 20b and 21 respectively.
a, 21b and the multiplexer 8 shown in FIG.
Is a transfer gate. Incidentally, FIG.
The same reference numerals indicate the same or corresponding parts. FIG. 4 shows a memory cell 2 shown in FIG.
4 is a diagram showing a circuit configuration of FIG. 4, wherein FIG. 4 (a) shows a high resistance load type NMOS memory cell and FIG. 4 (b) shows a CMOS type memory cell. In FIG., 41a, 41b has a drain connected to a storage node 45a, 4 5 b, a gate connected to the other of the drain from each other, the driver transistor of N-channel having its source connected to ground 19, 42a, 42b are The drain or source is connected to the storage nodes 45a and 45b, the gate is connected to the word line 22 or 23, and the source or drain is connected to the bit line 20 (20).
a, 20b) or 21 (21a, 21b) respectively, an N-channel access transistor 43,
a and 43b are load resistors each having one end connected to the power supply potential 18 and the other end connected to the storage nodes 45a and 45b, respectively.
Reference numerals a and 44b denote P-channel transistors each having a drain connected to the storage node, a gate connected to the other drain, and a source connected to the power supply potential 18. Hereinafter, the operation of the semiconductor memory device will be described. FIG. 5 is a diagram showing the operation timing of the semiconductor memory device. In the figure, A _IN indicates an address input, and A _OUT indicates an address.
Represents an address buffer output, WL represents a word line, I / O represents an I / O line, SA _OUT represents a sense amplifier output, and D _OUT represents a data output. For example, when selecting the memory cell 24a, the memory cell 24a to be selected from the row address input 1 is selected.
Is input, the word line 22 to which the memory cell 24a is connected is set to the selected level (for example, High level), and the other word line 23 is set.
Becomes a non-selection level (for example, Low level). Similarly, when selecting a bit line, a column address signal corresponding to a column in which a pair of bit lines 20a and 20b connected to the memory cell 24a and the memory cell 24c to be selected is input from the address input 4, and the bit line is input. Only the transfer gate 27a, 27b connected to the pair 20a, 20b conducts, only the selected bit line 20a, 20b is connected to the I / O line pair 29a, 29b, and the other bit lines 21a, 2b
1b is deselected and disconnected from the I / O line pair 29a, 29b. Next, the read operation of the selected memory cell 24a will be described. Now, when the storage node 45a of the memory cell shown in FIG.
5b is at the low level. At this time, one driver transistor 41a of the memory cell is in a non-conductive state, the other driver transistor 41b is in a conductive state, and the word line 22 is in a state selected by High. Transistors 42a, 4
2b are turned on, a DC current flowing through these paths is generated in the path of power supply potential 18 → bit line load 25b → bit line 20b → access transistor 42b → driver transistor 41b → ground 19, and the other Since the driver transistor 41a is non-conductive in the path of the power supply potential 18 → the bit line load 25a → the bit line 20a → the access transistor 42a → the driver transistor 41a → the ground 19, no DC current flows. At this time, the potential of the bit line 20a where no DC current flows is set to the bit line load transistor 25a.
a, 25b, 26a, when the threshold voltage of 26b and V _th, "supply potential -V _th" becomes, also, the potential of the bit line 20b towards the flow of direct current, driver transistor 41b, the access transistor 42b and the resistance of the bit line load 25b.
"Potential is lowered from only ΔV," V _th power supply potential -V _th -
ΔV ”. Here, ΔV is called a bit line amplitude,
Usually, it is about 50 mV to 500 mV, and is adjusted according to the magnitude of the bit line load. Then, this bit line amplitude Δ
V is applied to I through transfer gates 27a and 27b.
/ O lines 29a and 29b, amplified by the sense amplifier 9, further amplified by the output buffer 10, and output data 1
Reads as 1. The input data buffer 1
3 indicates that in the case of reading, the I / O line pair 29a, 29b is not driven by the read / write control circuit 16;
On the other hand, in the case of writing, the potential of the bit line on which Low data is to be written is forcibly lowered to a low potential, and the potential of the other bit line is raised to a high potential. For example, when writing inverted data in the memory cell 24a, one I / O
The write operation is performed by setting the O line 29a to a low level, setting the other I / O line 29b to a high level, setting one bit line 20a to a low level, and setting the other bit line 20b to a high level. On the other hand, in this semiconductor memory device, the above-described internal circuit operates in response to two systems of chip select signals from another system.
Together with a CS (chip select) buffer circuit to be transmitted to the IC chip. FIG. 6 is a diagram schematically showing an arrangement state of circuits on an IC chip of a semiconductor memory device having the CS buffer circuit. In the figure, 51 is an IC chip,
Reference numerals 52a and 52b denote CS2 buffers and / CS1 buffers, respectively, and reference numerals 53a and 53b denote wirings along the longer sides of the chip. The same reference numerals as those in FIG. 2 denote the same or corresponding parts. FIG. 7 is a diagram showing a circuit configuration of the CS buffer circuit shown in FIG. 6, in which the same reference numerals as those in FIG. 6 denote the same parts, and reference numerals 60, 61, 63, 64
Is a node, 62 is a NOR gate, 65 is a NAND gate, 66 is a NOT gate, and / C shown in FIG. 6 is provided by the NOR gate 62 and inverters 66d, 66e, 66f.
An S1 buffer 52b is formed, and inverters 66a, 6
6b and 66c and the NAND gate 65, the C shown in FIG.
The S2 buffer 52a is configured. [0010] In FIG. 6, the read / write control circuit 16 and the chip selector transfected input terminal 14 is the one, which is intended to correspond to the chip select outputs from / CS 1 buffer 52 b, C in the vicinity of S 2 buffer 52 a
Read / write corresponding to the C S 2 buffer 52a is
Only control circuit and chip select input terminal (both shown
And / CS1 buffer 52b, C
The chip select output of the S2 buffer 52a, ie, / C
When both SA and / CSB are at the low level, the internal circuit is activated and the above-described read / write operation is performed. Hereinafter, the operation of the CS buffer circuit will be described by taking as an example a case where / CS1 changes from Low and CS2 changes from Low to High level. Now, / CS
1 and CS2 are both at the Low level. In this state, the outputs of the / CS1 buffer 52b and the CS2 buffer 52a are both at the High level and are in the enabled state. Then, the signal input to CS2 of the node 60 is Low.
From the high level to the low level, the inverters 66a,
The node 53, which is the long side of the chip, passes through 66b and 66c.
b changes from High to Low level. At this time,/
Since the input of CS1 is at the low level, the NOR gate 62
As a result, the node 63 goes high, and the low level is output to / CSA through the three inverter stages (inverters 66d, 66e, 66f). And
The / CSA Low level signal is input from the chip select input terminal 14 to the read / write control circuit 16. On the other hand, the output of / CSB is output from the node 60 through the node 53b, the node 64, and the node 53a to the NAND.
High level signal reaching gate 65 and node 6
1 to a low level in response to a high-level signal that has reached the NAND gate 65, and the NAND gate 65
Is input to a chip select input terminal of an operation control circuit (not shown) similar to the read / write control circuit 16 in the vicinity of. The internal circuit is activated by these two low-level chip select outputs. In a conventional semiconductor memory device in which an internal circuit is controlled to be active or inactive by two systems of chip select signals, the CS buffer circuit receiving the chip select signal is as described above. When the signal entering the CS2 buffer at the node 60 changes from Low to High, the internal signal of the / CS1 buffer enters the CS2 buffer from the / CS1 buffer, and the internal signal of the / CS1 buffer passes through the nodes 53a and 53b which are the longer sides of the chip. to enter the back and forth CS2 buffers, the change in the output of the C S2 buffer, i.e., / CSB change in the signal level of, / CS1
The change in the output of the buffer, that is, the change in the signal level of / CSA, results in the / CS1 buffer and CS2
There is a problem that a difference occurs in the access time for both outputs of the buffer and the timing margins such as write recovery. The present invention has been made in order to solve the above-mentioned problems. Signal changes of two chip select signals are equally transmitted to an internal circuit, and access time and write recovery for these two signals are performed. It is an object of the present invention to obtain a semiconductor memory device capable of equalizing a timing margin. According to a first aspect of the present invention, there is provided a semiconductor memory device having a semiconductor memory device mounted thereon.
The chips (51) are arranged at positions separated from each other, and
Chip select signal (CS2) input from the section
And a signal change of the second chip select signal (/ CS1).
First to transmit the modification to the internal circuit of the semiconductor chip (51)
(75, 76, 77, 74, 80) and a second buffer
Circuit (81, 78, 71, 73, 79)
(75, 76, 77, 74, 8)
0) and the second buffer circuit (81, 78, 71, 7).
(A) and a second arrangement for connecting
Line (70), the first buffer circuit (75,
76, 77, 74, and 80) receive the first chip select signal (CS2) and receive the first signal (76 ) in response to the first chip select signal (CS2).
Of the first chip select signal (C).
When S2) is in the selected state (H) , the first signal
(Output of 76) to a first state (H) , a first input circuit (75, 76), and the first signal (output of 76) and the first signal (76).
And a second signal to be described later via the first wiring (A).
(The output of 78) is input and the first signal (the output of 76) is input.
Force) and a third signal according to the second signal (output of 78).
And outputs the first signal (/ CSB).
Output) is in the first state (H) and the second signal
Is in the second state (L), the third signal (/ C
SB) to be in the selected state (L).
74, 80) and the second buffer circuit (8
1, 78, 71, 73, 79) are the second chip select signal (/ CS1) and the second wiring (70).
Together with said first signal (output of 76) is input via the second signal in response to the second chip select signal (/ CS1) and said first signal (output of 76)
(Output of 78) , and when the second chip select signal (/ CS1) is in the selected state (L) , the first
A second input circuit to the chip select signal (CS2) state to the second regardless of the signal (78 output) of the second state (L) (81,78), said second signal (7
8) and the first signal (output of 76) is input via the second wiring (70), and the first signal
(The output of 76) and the second signal (the output of 78 ) to output a fourth signal (/ CSA), and the first signal (the output of 76) is in the first state (H). When the second signal (output of 78) is in the second state (L) , the second logic circuit (71 ) sets the fourth signal to the selected state (L). , 73, 79), and the third (/
CSB) and the fourth signal (/ CSA) are both selected.
In the state (L), the internal circuit is activated.
It was made . According to the present invention, the configuration as described above is provided.
Activates the internal circuit when both are selected
First and second signals for generating third and fourth signals
When generating a signal, the first and second chip select signals
And a configuration using the second and first signals.
Electrical length of first and second wirings for transmitting the first signal
Are substantially equal to each other, so that a change in the signal level of the chip select signal input to each of the two buffer circuits can be equally transmitted to the internal circuit. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a circuit configuration of a CS buffer circuit of a semiconductor memory device according to one embodiment of the present invention. In the drawing, reference numerals 71, 75, 76, 77, 78, 79, and 80 denote inverters , and Nodes 73 and 74 are NOR gates, 81 is a NAND gate , and A and 70 are on the long side of the chip.
Along the wiring , the NAND gate 81 and the inverter 7
1,78,79 and the NOR gate 73 / CS1 buffer is configured, the inverter 7 5, 7 6, 7 7, 80 and NOR gate 74 is configured for CS2 buffer, drawing / CS1, CS2, respectively / CS1 An input signal input to the buffer and an input signal input to the CS2 buffer are shown, and / CSA and / CSB indicate an output signal of the / CS1 buffer and an output signal of the CS2 buffer, respectively. In this semiconductor device, similarly to the conventional semiconductor memory device shown in FIG. 6, a CS buffer circuit composed of the / CS1 buffer and the CS2 buffer has chip select inputs of two operation control circuits on the chip. It is formed on the chip so as to be arranged near the terminal. still,
The circuits other than the CS buffer circuit have the same configuration as the conventional semiconductor memory device shown in FIG. The operation of the CS buffer circuit will be described below. Table 1 below is a truth table of this CS buffer circuit, and shows the signal levels of / CS1 and CS2, the levels of wiring A and node B, and the levels of / CSA and / CSB corresponding to these signal levels. , CS2
Is high level and / CS1 is low level, / C1
Both SA and / CSB become Low level, and this Low
When two signals of the level are input from the chip select input to the internal circuit, the internal circuit is activated and operates. [Table 1] Next, the operation when the signal levels of / CS1 and CS2 change will be described. Here, / CS
An example in which CS2 changes from low level to high level while 1 remains at low level will be described. Before the signal level changes, as shown in the upper column of Table 2 below, / CS1 and CS2 are both Low level, wiring A is Low level, node B is High level, / CSA and / CSB are Low level. Both are at High level,
Chip select operation is disabled. When the chip select signal input to CS2 changes from low to high level, the signal passes through inverters 75 and 76, and the wiring 70 changes from low to high. The signal change of / CSA changes as follows. That is, through the wiring 70 which is the long side of the chip, the node 72 of the inverter 71 goes from High to Low level,
At the NOR gate 73, this Low level and the Lo of the wiring A
At the w level (this wiring A is at the same level as before the signal change), the CSV _ss becomes the high level. Then, / CSA is changed from High to Low by the inverter 79. On the other hand, / CSB changes as follows. The node B goes high through the inverter 77 one step from the wiring 70.
It changes from h to Low. Then, at the NOR gate 74,
This Low level and the Low level of the wiring A (this wiring A
Is the same level as before the signal change) and the CSV _cc goes to the high level, and the output of the inverter 801 is changed from High to L
ow. When both / CSA and / CSB become Low level, the internal circuit to which / CSA and / CSB are input changes from the disabled state before the signal change to the active state. [Table 2] It should be noted that while CS2 remains at the high level,
If CS1 is changed from the High level to the Low level, and, High level CS2 from Low level,
Even when / CS1 changes from the High level to the Low level, as shown in the middle and lower columns of Table 2 above, / CSA and / CSB both become the Low level as described above. The chip select operation of the internal circuit receiving CSA and / CSB changes from the disabled state before the signal change to the active state. In the semiconductor memory device of the present embodiment, the signal running on the long side of the chip, that is, the signal running on the wiring A is not affected by the change in the signal levels of / CS1 and CS2.
Since the CS buffer circuit is configured to be active when the signal level of / CS1 is active, / C1
Changes in the signal levels of S1 and CS2 can be transmitted to / CSA and / CSB without making one round trip on the long side of the chip. As a result, the signal changes of the two chip select signals are transmitted equally to the internal circuit. Therefore, the internal circuit can be controlled from the active state to the inactive state, or vice versa, without causing a difference in the timing margins such as access time and write recovery for these signals. In the above embodiment, the / CS1 buffer 5
Although the device in which the node connecting CS2b and CS2 buffer 52a is arranged in the direction of the longer side of the chip has been described, the / CS1 buffer 52b
In the case where a node that connects the CS2 buffer and the CS2 buffer 52a is arranged in another part, the same effect as in the above embodiment can be obtained. As described above, according to the present invention, the first chip select output is transmitted to the internal circuit based on one of the two chip select signals and the internal signal of the second buffer. One buffer, the other of the two systems of chip select signals and the internal signal of the first buffer are input, and the other of the two systems of chip select signals is at a level at which the first chip select output should be activated. At this time, the CS buffer circuit is constituted by the internal buffer to the first buffer and the second buffer configured to have the signal level at which the first chip select output should be activated. Each change in the signal of the select input can be transmitted equally to the internal circuit, and as a result, the access time and write recovery time for both signals can be reduced. Thus, there is an effect that the operating state of the internal circuit can be controlled at high speed without causing unnecessary delay time.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating a semiconductor memory device according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of an S buffer circuit. FIG. 2 is a block diagram of an embodiment of the present invention and a portion of a conventional semiconductor memory device excluding a CS buffer circuit. FIG. 3 is a circuit diagram showing in detail a memory cell array shown in FIG. 2 and a peripheral portion thereof; 4 is a diagram showing a circuit configuration of a memory cell constituting the memory cell array of FIG. 3, and FIG.
FIG. 4B is a circuit diagram of a CMOS memory cell. FIG. 5 is a diagram showing operation timings of the semiconductor memory device shown in FIG. 2; FIG. 6 is a diagram schematically showing a pattern layout on an IC chip of a conventional semiconductor memory device. FIG. 7 is a circuit diagram of a CS buffer circuit of a conventional semiconductor memory device. [Description of Signs] 1 row address input 2 row address buffer 3 row address decoder 4 column address input terminal 5 column address buffer 6 column address decoder 7 memory cell array 8 multiplexer 9 sense amplifier 10 output data buffer 11 read data Output terminal 12 Write data input terminal 13 Input data buffer 14 Chip select input terminal 15 Read / write control input terminal 16 Read / write control circuit 18 V _cc 19 Ground 20 a, 20 b, 21 a, 21 b Bit line 22, 23 Word line 24 a , 24b, 24c, 24d Memory cells 25a, 25b, 26a, 26b Bit line loads 27a, 27b, 28a, 28b Transfer gates 41a, 41b, 42a, 42b N-channel driver transistor 43a 43b load resistor 44a, 44b PMOS transistor 51 IC chips 52a CS2 buffer 52 b / CS1 buffer 53a wiring 53b wiring 60,61,63,64 node 62 NOR gates 65 NAND gates 66a, 66b, 66c, 66d, 66e, 66f
Inverter 70 wiring 71 Inverter 72 Nodes 73 and 74 NOR gates 75, 76, 77, 78, 79, 80 Inverter 81 NAND gate A wiring B node

Claims (1)

(57) [Claims] 1. A semiconductor chip on which a semiconductor memory device is mounted.
Are arranged at a distance from each other on the
A first chip select signal and a second chip select signal
Signal change of the external signal to the internal circuit of the semiconductor chip
First and second buffer circuits, and first and second buffers disposed at the separated positions
And first and second wiring connecting the circuit to each other, said first buffer circuit, together with the first chip select signal is input,
A first input circuit that outputs a first signal in response to the first chip select signal, and sets the first signal to a first state when the first chip select signal is in a selected state; , Will be described later via the first signal and the first wiring.
A second signal is input, and the first signal and the second signal
A third signal is output according to the signal of
In the first state and when the second signal is in the second state
A first logic for setting the third signal to a selected state
And a circuit, said second buffer circuit, the second chip select signal and the second wiring
The first signal is input through the
And outputting a second signal in response to the chip select signal and the first signal. When the second chip select signal is in the selected state, the second signal is output regardless of the state of the first chip select signal. second for the signal and the second state
Of the input circuit and said second signal and through the second wire the first
And outputs a fourth signal in response to the first signal and the second signal. The first signal is in the first state, and the second signal is the second signal. when a second state, and a second logic circuit for the selected state said fourth signal, when the third and fourth signals are both selected
Can, the internal circuit is activated, the semiconductor memory device, characterized in that.