JPH0636592A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory in which access time is not delayed even when a redundant circuit is used. CONSTITUTION:When a redundant row is selected, a signal making a normal cell block as disable is not outputted, a state in which both a redundant cell 55 and a normal cell 24 are selected is made. Also, caused by that an area of a redundant memory cell is larger than that of a normal memory cell, correct data of the redundant memory cell 55 is outputted to a bit line even when the redundant memory and a defective normal memory cell are doubly selected. Consequently, access time at the time of selecting the normal cell after the redundant circuit is used becomes high speed, wiring is reduced, and the circuit can be simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, when a redundant row is selected in a redundant circuit,
Redundant cells can be output correctly even if multiple defective normal cells and redundant cells are selected by not using the signal that disables the normal cell block. The present invention relates to a semiconductor memory device including a memory cell.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing an example of a conventional semiconductor memory device. In the figure, 1 is a row address data input, 2 is a row address buffer for amplifying or inverting the row address input 1, 3 is a row address buffer for decoding the row address signal given to the row address input 1. Decoder 4, column address data input, 5 column address buffer for amplifying or inverting column address input 4, 6 column address decoder for decoding column address signal provided to column address input 4 Is. 7
Is a memory cell array in which memory cells for storing information are arranged in a matrix, 8 is a multiplexer, 9 is a sense amplifier that senses and amplifies read-out voltage of a small amplitude, and 10 is an output of the sense amplifier 9 which is further external to the semiconductor memory device. Output data buffer for amplification to the level to be taken out to
Reference numeral 11 is a read data output, 12 is a write data input, and 13 is an input data buffer for amplifying a signal given to the write data input 12. 14 is a chip selection input, 15 is a read / write control input, 1
6 is a sense amplifier 9 and an output data buffer 1 according to chip selection / non-selection and data read / write mode
0, a read / write control circuit for controlling the write data buffer 13 and the like.

FIG. 5 shows a peripheral portion of a memory cell of the semiconductor memory device of FIG. 2 lines 2 for simplicity
The configuration of columns is shown. In FIG. 5, 20a,
Reference numerals 20b, 21a and 21b are corresponding bit line pairs, 22 and 23 are word lines connected to the output point of the row address decoder 3, and 24a to 24b are word lines 2
2, 23 and bit line pairs 20a, 20b, 21a, 21b
Memory cells, 25a, 25b and 2 arranged at the intersection of
6a and 26b are bit line loads having one end connected to the power supply potential 18 and the other end connected to the bit line. 27a, 27b and 2
The output signals of the column address decoder 6 of FIG. 4 are input to the gates of 8a and 28b, and the drains or sources thereof are connected to the bit lines 20a and 20b and 21a and 21b, respectively.
It is a gate. Reference numeral 9 is a sense amplifier that detects the potential difference between the I / O line pair 29a and 29b, and 10 is an output buffer that amplifies the output of the sense amplifier 9.

The memory cell 24 shown in FIG.
The high resistance load type NMOS memory cell shown in FIG.
The CMOS type memory cell shown in (b) is used. Figure 6
In (a) and (b), 41a and 41b are N-channel drivers having drains connected to storage nodes 45a and 46b, gates connected to the other drains, and sources connected to ground.
The transistors 42a and 42b have drains or sources as storage nodes 45a and 45b and gates as the word line 22.
Or 23, the source or drain is connected to the bit line 20
a, 20b or 21a, 21b are N-channel access transistors, 43a, 43b are load resistors connected at one end to the power supply potential 18 and the other ends are connected at the storage nodes 45a, 45b, 44a, 44b are drains at the storage node 45a and 45b, P-channel transistors having gates connected to each other's drains and sources connected to the power supply potential 18.

Next, the operation will be described with reference to the operation timing chart of FIG. Ain is address input, Ao
ut is an address buffer output, WL is a word line, I /
O is an I / O line, SAout is a sense amplifier output, and Dou
t is a data output. When selecting the memory mol 24a, the memory cell 2 to be selected from the row address input 1 is selected.
A row address signal corresponding to the row in which 4a is located is input, the word line 22 connected to the memory cell 24a is set to a selected (for example, High) level, and the other word lines 23 are set to a non-selected (for example, Low) level. It Similarly, when selecting a bit line, a column address signal corresponding to the column in which the memory cell 24a to be selected and the bit line pair 20a, 20b to which the memory cell 24a is connected are input from the column address input 4 and Since only the transfer gates 27a and 27b connected to the bit lines 20a and 20b are made conductive, only the selected bit lines 20a and 20b are I / O'd.
The other bit line 21a, which is connected to the line pair 29a, 29b,
21b is deselected and disconnected from the I / O line pair 29a, 29b.

Next, the read operation of the selected memory cell 24a will be described. Now, the storage node 45a of the memory cell 24a is at the high level, and the storage node 45b
Is at a low level. At this time, the memory cell 24a
One driver transistor 41a is non-conductive, and the other driver transistor 41b is conductive. Since the word line 22 is in the high-selected state, the access transistor 4 of the memory cell 24a
Both 2a and 42b are in a conductive state. Therefore, Vcc1
8 → bit line load 25b → bit line 20b → access
Transistor 42b → driver transistor 41b →
A direct current is generated in the path of the ground 19. However, in the other path, that is, the power supply Vcc18 → bit line load 25a → bit line 20a → access transistor 42a → driver transistor 41a → ground 19, the driver transistor 41a is non-conductive, so that a direct current flows. Absent. At this time, the bit line 20 on which the direct current does not flow
The potential of a is the bit line load transistors 25a, 25
If the threshold voltage of b, 26a, and 26b is Vth,
It becomes "power supply potential-Vth". Further, the potential of the bit line 20a through which the direct current flows is resistance-divided by the conduction resistances of the driver transistor 41b, the access transistor 42b and the bit line load 25b to obtain "power potential -V
The potential decreases by ΔV from “th”, and “power supply potential−Vth
−ΔV ″, where ΔV is called the bit line amplitude,
It is usually about 50 mV to 500 mV, and is adjusted according to the magnitude of the bit line load. This bit line amplitude is transferred to the I / O line 29a via the transfer gates 27a and 27b.
29b, which is amplified by the sense amplifier 9, further amplified by the output buffer 10, and read as the data output 11. In the case of reading, the read / write control circuit 16 of the input data buffer 13 does not drive the I / O line pair 29a, 29b. In the case of writing, writing is performed by forcibly lowering the potential of the bit line on the side where the low data is written to a low potential and raising the potential of the other bit line to a high potential. For example, in order to write the inverted data to the memory cell 24a, one I /
A write operation is performed by setting the O line 29a to the low level, the other I / O line 29a to the high level, the one bit line 20a to the low level, and the other bit line 20a to the high level.

[0007]

The conventional semiconductor memory device is configured as described above, and the conventional semiconductor memory device is further shown in FIG. 8 in order to improve the yield at the time of production. It has a redundant circuit. When using this redundant circuit, especially the redundant Row memory cell 55,
When the address data 50 hits the program circuit 51, the program circuit 51 outputs NEDR (Normal Element).
Disable Row) signal 52 is output. The NEDR signal 52 is input to the redundant local decoder 54 and redundant R
The word line 57 of the OW cell 55 is raised, and at the same time, it is inputted to the decoder buffer 3 in order to disable the normal ROW having a defective bit. As a result, the decoder buffer 3 and the subsequent sections remain disabled, the normal word line that is the output of the normal local decoder 53 is not selected, the memory cell array 7 is not selected, and only the correct data from the redundant cell 55 is stored in the bit line. Is output.

Since the conventional redundant ROW circuit is configured as described above, when the normal cell is accessed after the redundant cell is accessed, the NEDR signal output from the redundant program circuit 51 falls-> the decoder 3 is enabled. → The normal local decoder 53 is enabled → The word line is selected, so that the access time is delayed from the normal access by the waiting time until the NEDR signal falls. There was a problem. The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor memory device in which access time is not delayed even if a redundant circuit is used.

[0009]

A semiconductor memory device according to the present invention does not select a cell circuit forming a redundant ROW by using a NEDR signal for deselecting a normal cell, but a redundant cell and a normal cell. Both are selected,
In this multi-selection state, the redundant cell structure is such that the combined output of the redundant cell data and the defective normal cell data becomes the same as the correct data of the redundant cell and is output to the bit line.

In the semiconductor memory device according to the present invention, the redundant cell has a larger area than the normal cell. A semiconductor memory device according to the present invention is configured by providing a plurality of redundant cells having the same area as that of a normal cell.

[0011]

In the structure of the redundant ROW circuit according to the present invention,
By setting the redundant cell to have a larger area than the normal cell, in the multi-selection state, the same data as the correct data of the redundant cell is output as the combined output of the redundant cell and the normal cell. There is no need for non-selection signals and circuits, and there is no delay in access time when using redundant circuits. Moreover, since a signal for deselecting a normal cell is not required, the circuit configuration is simplified and the wiring is reduced.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. Example 1. FIG. 1 shows a redundant ROW circuit in a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 schematically shows a state of bit line potential by the redundant cell 55 and the normal cell 24 of FIG. The bit line potential by the redundant memory cell is shown. The upper one is the potential when the stored content of the redundant cell is "High", the lower one is the potential when "Low", and the broken line is the bit line potential by the normal memory cell. Similarly, the upper one is the potential at "High" and the lower one is the potential at "Low".

In this embodiment, as shown in the figure, the area of the redundant memory cell 55 is made larger than that of the normal memory cell 24. That is, the access transistors (42a, 42b in FIG. 6) and the driver transistors (41a, 41b in FIG. 6) of the redundant memory cell 55 are made 4 to 5 times larger than that of the normal memory cell 24 in the layout as much as possible. ing. In the present embodiment, even when the redundant cell 55 is selected by the redundant word line 57,
A signal such as the NEDR signal 52 which disables the normal cell block in the above-mentioned conventional configuration is not output. Further, when the redundant cell 55 is selected, in addition to this, one of the normal word lines 56 is selected from the normal cells 24 by one normal word line selected by the row decoder 3 in response to the row address input 1. One of the
The multi-selection state of the redundant cell 55 and the normal cell 24 is set. At the time of this multi-selection, the data of the normal cell 24 which is the defective cell is "High" and the data of the redundant cell 55 is "Low", and even if these data are output to the bit lines 20 and 21, they are redundant. Since the area of the cell 55 is 4 to 5 times as large as that of the normal cell 24, the bit line potential at that time is slightly higher than the bit line potential due to the "Low" data of the redundant memory cell of FIG. 2 (see FIG. 2). It never rises above the bit line potential due to the "Low" data of the normal cell shown).
Since the t-line potential is also detected as "Low" by the sense amplifier, the data in the redundant cell 55 is not inverted. On the other hand, when the data in the redundant cell 55 is "High", even if the data in the normal cell 24 is "Low",
Since the "high" data is directly supplied from the power supply via the bit line load, it is hardly affected by the "Low" data of the normal cell, and the data detected from the bit line becomes "High". When the data of the normal cell 24, which is a defective cell, is the same as the data of the redundant cell 55, the combined output data is the same as the data of the redundant cell, and no problem occurs.

As described above, according to this embodiment, even when the redundant memory cell 55 and the defective normal memory cell 24 are set in the double selected state, the access transistor and the driver transistor of the redundant cell are 5 to 6 more than those of the normal cell. Since the correct data of the redundant cell is output to the bit line by being twice as large, the access time is not delayed when accessing the normal cell after the redundant circuit is used. Moreover, since a signal for deselecting a normal cell is not required, there is an effect that the circuit configuration is simple and the wiring is reduced.

Example 2. FIG. 3 shows a layout method of redundant cells in a semiconductor memory device according to a second embodiment of the present invention.

As in the first embodiment of FIG. 1, there is no area for providing a large access transistor and driver transistor in the layout, and in one memory cell, the data in the redundant cell is inverted when it is combined with the data in the normal cell. If it is not possible to eliminate the above, the redundant cells 1 to 4 (55) of the same pattern as the normal cell 24 are arranged on the same bit line 20, 21 as shown in FIG. By simultaneously selecting the redundant word line 1 to the redundant word line 4 to be used, it is possible to equivalently obtain the same configuration as that in which the redundant cells of 4 to 5 times the normal cells are laid out. Therefore, also in this embodiment, the first embodiment
Similarly, the access time is not delayed when accessing the normal cell after the redundant circuit is used. Further, it is possible to obtain an effect that the circuit configuration is simplified and the number of wirings is reduced because a signal for deselecting a normal cell is not required.

[0017]

As described above, according to the present invention, the redundant memory cell has a larger area than that of the normal memory cell, or a plurality of redundant memory cells are provided, so that the redundant memory cell and the defective normal memory cell are duplicated. The redundant memory cell structure ensures that the correct data in the redundant cell is output to the bit line even in the double-selected state. Therefore, even if a redundant circuit is used, the access time is not delayed, and the normal cell is not selected. Since no means is required, the circuit configuration is simplified and the number of wirings is reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a cell structure of a redundant ROW cell in a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing bit line potentials of a redundant cell and a normal cell in the embodiment of FIG.

FIG. 3 is a diagram showing a layout method of redundant ROW cells according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of an example of a conventional semiconductor memory device.

5 is a diagram showing a memory cell peripheral portion of the semiconductor memory device of FIG. 4;

FIG. 6 is a diagram showing a high resistance load type NMOS memory cell (FIG. (A)) and a CMOS type memory cell (FIG. (B)).

7 is an operation timing chart of the conventional semiconductor memory device of FIG.

FIG. 8 is a schematic diagram of a redundant ROW circuit in a conventional semiconductor memory device.

[Explanation of symbols]

1 row address input 2 row address buffer 3 row address decoder 4 column address input 5 column address buffer 6 column address decoder 7 memory cell array 8 multiplexer 9 sense amplifier 10 output data buffer 11 read data output 12 write data input 13 input data buffer 14 chip selection input 15 read / write control input 16 read / write control circuit 18 Vcc 19 ground 20, 21, 20a, 20b, 21a, 21b bit line 22, 23 word line 24, 24a, 24b , 24c, 25d Memory cell 25a, 25b, 26a, 26b Bit line load 27a, 27b, 28a, 28b Transfer gate 41a, 41b N channel driver transistor 42a, 42b N channel Access transistor 43a, 43b load resistance 44a, 44b PMOS transistor 50 address data 51 redundant program circuit 52 NEDR signal 53 normal local decoder 54 redundant local decoder 55 redundant memory cell 56 normal word line 57 redundant word line

[Procedure amendment]

[Submission date] November 16, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction content]

[0009]

A semiconductor memory device according to the present invention does not select a cell circuit forming a redundant ROW by using a NEDR signal for deselecting a normal cell, but a redundant cell and a normal cell. Both are selected,
In this multi-selection state, the data of the normal cell is bad is obtained by a redundant cell structure is output to the correct data and is synthesized bi <br/> Tsu DOO line of redundant cells.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

As described above, according to this embodiment, even when the redundant memory cell 55 and the defective normal memory cell 24 are set to the double selected state, the access transistor and driver transistor of the redundant cell are 4 to 5 times larger than those of the normal cell. Since the correct data of the redundant cell is output to the bit line by being twice as large, the access time is not delayed when accessing the normal cell after the redundant circuit is used. Moreover, since a signal for deselecting a normal cell is not required, there is an effect that the circuit configuration is simple and the wiring is reduced.

Claims (3)

[Claims] 1. In a semiconductor memory device having a redundant circuit, when a redundant row is selected, a signal for disabling a normal cell block is not output and both a redundant cell and a normal cell are selected. A semiconductor memory device characterized in that an output obtained by combining both outputs of the both cells is logically the same as an output of the redundant cell. 2. The semiconductor memory device according to claim 1, wherein the redundant cell has a larger area than the normal cell. 3. The semiconductor memory device according to claim 1, wherein a plurality of redundant cells having the same area as a normal cell are provided.