JPH0322461A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable supply of a power without narrowing the width of a power line by providing a power wire for a prebuffer which is connected to one of power wires of a semiconductor integrated circuit having an input-output buffer containing the power wires in a plurality. CONSTITUTION:A ground line 105 for a prebuffer, a VDD line 106 for a prebuffer, a first line 107, a second power line 108 and a ground line 109 for an external buffer form a power line by connecting, through a through hole, the same places of inputoutput blocks on a first wiring face to which said lines correspond. A second aluminum wiring face is integrated with a wiring 112, on the other side, and by changing connection of these wirings with the input-output blocks on the first wiring face, the wiring 112 on the first wiring face can be connected with the second power line 108 by providing a through hole in a part A.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to an input/output buffer of a CMOS gate array.

[Conventional technology]

FIGS. 3(a), (b), and (C) show an example of the artwork of a conventional semiconductor integrated circuit; the base surface on the semiconductor chip, the first aluminum wiring surface on the base surface, and the FIG. 2 is a plan view of the aluminum wiring surface of No. 2; Conventionally, the artwork for this type of semiconductor integrated circuit first consists of functional elements such as an N-channel prebuffer 3Q1 and a P-channel prebuffer 3 on the bottom surface of a semiconductor chip, as shown in FIG. 3(a).
02, a P channel external buffer 303 and an N channel external buffer are formed. In addition, the first aluminum wiring surface formed on the base surface has wiring 3 that contacts the functional elements on the base surface, as shown in FIG. 3(b).
12 mag is formed. Furthermore, as shown in FIG. 3(c), the second aluminum wiring surface formed on the first aluminum wiring surface is connected to the wiring on the first aluminum wiring surface via a through hole. Wiring of a pre-buffer power line and an external buffer power line for applying potentials to the pre-buffer and external buffer is well established. In this way, artwork usually has a pre-buffer power supply line and an external buffer power supply line separated, and when there are multiple power supplies, separate power supplies are provided for the pre-buffer and the external buffer.

[Problem to be solved by the invention]

In the above-mentioned conventional artwork, since a plurality of power lines pass through the pre-buffer power line, the width of each power line becomes narrower, and the power impedance becomes higher. Further, there are also drawbacks such as power supply noise during simultaneous operation, which is a problem when a plurality of buffers operate simultaneously, and the width of the power supply line itself, which is disadvantageous against electromigration, for example. An object of the present invention is to provide a semiconductor integrated circuit having artwork that solves this problem.

[Means to solve the problem]

A semiconductor integrated circuit of the present invention is a semiconductor integrated circuit having an input/output buffer including a plurality of power supply lines, and includes a pre-buffer power supply line connected to one of the power supply lines.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a), (b), and (c) show an example of artwork for a semiconductor integrated circuit according to the present invention, showing a base surface of a semiconductor chip, a first aluminum wiring surface on the base surface, and a first aluminum wiring surface above the base surface. FIG. 3 is a plan view of the second aluminum wiring surface of FIG. In this semiconductor integrated circuit artwork, the input/output buffer is operated by the second of two power supplies. The underlying surface of this artwork is the same as the conventional example shown in FIG. Furthermore, as shown in FIG. 1(C), the second aluminum wiring surface has almost fixed artwork regardless of the function of the input/output block. Further, the pre-buffer ground line 105, the pre-buffer VDD line 106, the first line 107, the second power supply line 108, and the external buffer ground line 109 are located at the same location in the input/output block on the corresponding first wiring surface. A power supply line is formed by connecting the two through a through hole. on the other hand,
As shown in FIG. 1(b), the second aluminum wiring surface has integrated wiring 112, and its function can be improved by changing the connections between these wirings and the input/output blocks on the first wiring surface. It can be changed. For example, as shown in FIGS. 1(a) and (b), by providing a through hole in part A, it is possible to connect the wiring 112 on the first wiring surface to the second power supply line 108. At the same time, by providing a through hole in the portion C, power can be supplied to the pre-buffer VDD line 106. Figures 2 (a), (b) and (C) show the semiconductor integrated circuit of the present invention. FIG. 7 is a plan view of the underlying surface of the semiconductor chip, the first aluminum wiring surface on the underlying surface, and the second aluminum wiring surface thereon, showing another example of the artwork. This is a case where the human output buffer is operated by the
As shown in Figures (b) and (C), B and C of the wiring 212
By providing through holes between the region, B of the first power supply line 207, and C of the prebuffer VDD line 206, the prebuffer VDD 206 is set to the same potential as the first power supply line 206.

〔Effect of the invention〕

As explained above, each artwork of the semiconductor integrated circuit of the present invention can be provided with a pre-buffer VDD line input/output buffer and supplied with power, even when multiple power supplies are required. This has the effect that power can be supplied without narrowing the width of the pre-buffer power supply line. Furthermore, since it has a mesh structure, it also has the effect that the power supply impedance seen from the input/output buffer side appears to be small.

[Brief explanation of drawings]

FIGS. 1(a), (b) and (c) show an example of the artwork of a semiconductor integrated circuit according to the present invention; the base surface of a semiconductor chip, the first aluminum wiring surface on the base surface, and the top surface of the semiconductor chip; FIG. FIGS. 2(a), 2(b) and 2(c) are a plan view of the second aluminum wiring surface of the semiconductor chip and the underlying surface of the semiconductor chip showing other embodiments of the artwork of the semiconductor integrated circuit of the present invention. 1st above
3(a), (b) and (c) show an example of the artwork of a conventional semiconductor integrated circuit. This is the base surface of the chip, the first aluminum wiring cotton fabric on the base surface, and the second aluminum wiring surface above it. 101,201,301...N channel prebuffer, 102,202,302...P channel prebuffer, 103,203,303...P channel external buffer, 104,204,304...N channel external Buffer, 105, 205, 305... Ground line for pre-buffer, 106, 206... VDD line for pre-buffer, 307... Second power supply line for pre-buffer, 107, 207... First power supply Line, 108, 208...Second power line, 308...
・First power supply line for external power supply, 108, 209, 3
10...Ground line for external buffer, 110,2
10.311...I/O pad, 111,211,1
12,212...Wiring.

Claims (1)

[Claims] 1. A semiconductor integrated circuit having an input/output buffer including a plurality of power supply lines, the semiconductor integrated circuit comprising a pre-buffer power supply line connected to one of the power supply lines.