JPH0774196A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH0774196A
JPH0774196A JP6006908A JP690894A JPH0774196A JP H0774196 A JPH0774196 A JP H0774196A JP 6006908 A JP6006908 A JP 6006908A JP 690894 A JP690894 A JP 690894A JP H0774196 A JPH0774196 A JP H0774196A
Authority
JP
Japan
Prior art keywords
power supply
chip
integrated circuit
pad
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6006908A
Other languages
Japanese (ja)
Other versions
JP2520225B2 (en
Inventor
Eiji Sugiyama
英治 杉山
Mitsuaki Natsume
光章 夏目
Toshiharu Saito
寿治 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6006908A priority Critical patent/JP2520225B2/en
Publication of JPH0774196A publication Critical patent/JPH0774196A/en
Application granted granted Critical
Publication of JP2520225B2 publication Critical patent/JP2520225B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To provide a semiconductor integrated circuit incorporating power supply terminals which make the power supply voltage in a chip uniform. CONSTITUTION:In a semiconductor deice composed of an integrated circuit chip 10, conductive layer 44 on which the chip 10 is mounted, and package substrate having, a conductive pattern 43 which is connected to an external terminal on one side and to a pad on the chip 10 on the other side, the pattern 43 is connected to a pair of first power supply pads 34 which are respectively arranged near centers of sides facing each other through power supply wiping on the chip 10. Therefore, second power supply pads 35 are provided at the corner sections of the chip 10 and the conducting layer 44, a plurality of pads 42 for wire connection which are connected to the pattern 43 through the layer 44, further connected to the second power supply pads 35, and not led out to the outside from a package are selectively provided on a package substrate.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、チップ内の電源電圧を
均一化する電源端子を内蔵した半導体集積回路装置に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a power supply terminal for equalizing the power supply voltage in a chip.

【０００２】[0002]

【従来の技術】ＥＣＬゲートアレイは一般に２電源方式
を採用し、高電圧側をＶCC、低電圧側をＶEEと呼ぶこと
が多い。図１はかかるＬＳＩ（大規模集積回路）の電源
系統に関するレイアウトで、１０はＩＣチップ、２０は
ＶCC側の配線パターン、３０，３１，３２はＶEE側の配
線パターンである。配線パターン２０，３０，３１は第
１層のアルミニウム（Ａｌ）配線層により形成される。
尚、ＩＣチップ１０内には図２の如き基本ゲートを有す
る複数の基本セルが形成されている。（図示せず）これ
に対し、横方向の配線パターン３２はこれらと交叉する
ように第２層のＡｌ配線層により形成され、そして第１
層の配線パターンのうちＶEE側の３０，３１と・印個所
３３でコンタクトする。ＶCC側の配線パターン２０は第
１層で全て連結しており、且つ周辺に全体で６個のボン
ディングパッド２１が設けてある。これに対しＶEE側に
ついては両側の配線パターン３０に２個所ボンディング
パッド３４があるに過ぎない。2. Description of the Related Art Generally, an ECL gate array adopts a dual power supply system, and a high voltage side is often called V CC and a low voltage side is often called V EE . FIG. 1 shows a layout related to a power supply system of such an LSI (Large Scale Integrated Circuit), 10 is an IC chip, 20 is a wiring pattern on the V CC side, and 30, 31, 32 are wiring patterns on the V EE side. The wiring patterns 20, 30, and 31 are formed of a first-layer aluminum (Al) wiring layer.
A plurality of basic cells having basic gates as shown in FIG. 2 are formed in the IC chip 10. (Not shown) On the other hand, the lateral wiring pattern 32 is formed by the Al wiring layer of the second layer so as to intersect these, and
Contact with V EE side 30, 31 and, mark point 33 of the wiring pattern layers. The wiring patterns 20 on the V CC side are all connected in the first layer, and a total of 6 bonding pads 21 are provided in the periphery. On the other hand, on the V EE side, there are only two bonding pads 34 on the wiring patterns 30 on both sides.

【０００３】縦方向に走るＶEE側の配線パターン３０，
３１はそれぞれ独立していて前述したように横方向の配
線パターン３２で各所が接続されるが、パッド３４が左
右に２個所しかないので電源電圧ＶEEにチップ内でばら
つきが生ずる。特に回路規模が大きくなるにつれて消費
電力が増加すると、低電圧側電源といえどもその供給電
圧のずれが平面的に生じ、回路形式によってはこれを無
視できなくなる。A wiring pattern 30 on the V EE side running in the vertical direction,
31 are independent of each other and are connected to each other by the horizontal wiring pattern 32 as described above, but since there are only two pads 34 on the left and right, the power supply voltage V EE varies within the chip. In particular, when the power consumption increases as the circuit scale increases, even if the power source is on the low voltage side, the supply voltage shifts in a planar manner, which cannot be ignored depending on the circuit type.

【０００４】例えば図２に示すＥＣＬゲートはＶEE側を
基準にして定電流源用のトランジスタＱ1 のベース電圧
ＶCSを設定するが、ＶEEに差があると定電流に差が生
じ、ひいては出力電圧等に差が出る。この差を吸収する
にはエミッタ抵抗ＲE の値を変える等の手段をとり得る
が、各エミッタ抵抗の値をゲート位置に応じて変えるの
は甚だ厄介で、実用性に乏しい。尚、同図において
Ｑ2 ，Ｑ3 は基準電圧ＶBBと入力ＩＮに対する差動対を
構成するトランジスタ、Ｑ4 ，Ｑ5 は出力ＯＵＴ，反転
ＯＵＴを得る出力段のトランジスタである。For example, the ECL gate shown in FIG. 2 sets the base voltage V CS of the transistor Q 1 for a constant current source with reference to the V EE side, but if there is a difference in V EE , a difference in constant current occurs, As a result, there is a difference in output voltage. To absorb this difference, means such as changing the value of the emitter resistance R E can be taken, but changing the value of each emitter resistance according to the gate position is extremely troublesome and impractical. In the figure, Q 2 and Q 3 are transistors forming a differential pair with respect to the reference voltage V BB and the input IN, and Q 4 and Q 5 are transistors at the output stage for obtaining the output OUT and the inverted OUT.

【０００５】[0005]

【発明が解決しようとする課題】本発明は、電源端子の
配置等を工夫してチップ内の電源電圧を均一化しようと
するものである。また集積回路では端子ピンの個数に制
約を受けるから、上記電源電圧の均一化は端子ピン数の
増加をもたらさずに行おうとするものである。SUMMARY OF THE INVENTION The present invention intends to equalize the power supply voltage in a chip by devising the arrangement of power supply terminals and the like. Further, in an integrated circuit, the number of terminal pins is limited, so that it is intended to make the power supply voltage uniform without increasing the number of terminal pins.

【０００６】[0006]

【課題を解決するための手段】本発明の半導体集積回路
装置は、集積回路チップと、該集積回路チップが搭載さ
れる導電層と、一端が外部端子に接続され他端が該集積
回路チップ上のパッドと接続されている導電パターンを
有するパッケージ基体からなる半導体装置であって、該
集積回路チップ上には、対向する辺の中央付近にそれぞ
れ配置され、前記導電パターンと接続される一対の第１
の電源パッドと、該第１の電源パッドと該チップ上の電
源配線を介して接続され、該チップのコーナー部に設け
られた第２の電源パッドを有し、該パッケージ基体上に
は、該導電層及び該導電層を介して前記導電パターンと
接続され、さらに前記第２の電源パッドと接続され、且
つパッケージ外部には導出されない、選択的に配設され
た複数のワイヤ接続用パッドを備えていることを特徴と
するものである。A semiconductor integrated circuit device according to the present invention includes an integrated circuit chip, a conductive layer on which the integrated circuit chip is mounted, one end connected to an external terminal, and the other end on the integrated circuit chip. Of the package base having a conductive pattern connected to the pads of the pair, and a pair of first semiconductor devices arranged on the integrated circuit chip in the vicinity of the centers of opposite sides and connected to the conductive pattern. 1
And a second power pad connected to the first power pad via a power wiring on the chip and provided at a corner portion of the chip. A conductive layer and a plurality of selectively arranged wire connection pads connected to the conductive pattern through the conductive layer, further connected to the second power supply pad, and not led out to the outside of the package It is characterized by that.

【０００７】[0007]

【作用】本発明により、集積回路チップ上には、パッケ
ージ基体上の導電パターンを介して外部端子の電源に接
続される第１の電源パッドのほか、この第１の電源パッ
ドに集積回路チップ上の電源配線を介して接続される第
２の電源パッドが設けられる。この第２の電源パッド
は、さらに集積回路チップが搭載されるパッケージ基体
上の導電層を介して、上記パッケージ基体上の導電パタ
ーンに接続される。According to the present invention, on the integrated circuit chip, in addition to the first power supply pad connected to the power supply of the external terminal through the conductive pattern on the package substrate, the first power supply pad is also provided on the integrated circuit chip. A second power supply pad connected via the power supply wiring is provided. The second power supply pad is further connected to the conductive pattern on the package substrate via the conductive layer on the package substrate on which the integrated circuit chip is mounted.

【０００８】したがって、集積回路チップ上の電源配線
には、外部端子の電源が、第１の電源パッドを介して接
続されるほか、第２の電源パッドを介しても並列に接続
される。しかも第１の電源パッドと第２の電源パッド
は、集積回路チップ上の電源配線の異なる部位に接続さ
れるから、電源配線上に分布する電源電圧に生じるずれ
を小さく抑制することができ、集積回路チップ内の各Ｅ
ＣＬゲート等の動作特性にずれが出るのを防止できる。Therefore, the power source wiring on the integrated circuit chip is connected to the power source of the external terminal through the first power source pad and in parallel through the second power source pad. Moreover, since the first power supply pad and the second power supply pad are connected to different portions of the power supply wiring on the integrated circuit chip, it is possible to suppress the deviation caused in the power supply voltage distributed on the power supply wiring, and to reduce the integration. Each E in the circuit chip
It is possible to prevent the operation characteristics of the CL gate or the like from deviating.

【０００９】[0009]

【実施例】以下図示の実施例を参照しながらこれを詳細
に説明する。図３は本発明の一実施例を示すチップ側の
レイアウトで、図１と同一部分には同一符号が付してあ
る。本例が図１と異なる点は、４隅にＶEE用のパッド３
５を追加し、且つここまで上下の第２層配線パターン３
２の端部を延長した点である。このようにするとＶEE側
もＶCCと同様に周囲に６個所ボンディングパッドができ
るので、内部の電源電圧はＶCC並みに均一化される。但
し、このことによってパッケージの外部端子数が増加す
ることは好ましくない。Embodiments will be described in detail below with reference to the embodiments shown in the drawings. FIG. 3 is a layout on the chip side showing an embodiment of the present invention, and the same portions as those in FIG. 1 are designated by the same reference numerals. This example is different from FIG. 1 in that V EE pads 3 are provided at the four corners.
5 is added and the upper and lower second layer wiring patterns 3
This is the point where the end of 2 is extended. In this way, since the V EE side has six bonding pads in the periphery as in the case of V CC , the internal power supply voltage is equalized to V CC . However, it is not preferable that this increases the number of external terminals of the package.

【００１０】そこで本発明では図４に示すように、パッ
ド３５に対しボンディングワイヤ４０で接続されるパッ
ケージ４１側のパッド４２は、パッド３４に対応するパ
ッド４３とは異なり外部端子（リード）には接続しない
ようにする。代わりに、パッケージ４１底部の導電層
（通常Ａｕ）４４にパッド４２および４３を接続する。
あるいは、パッケージ４１は通常多層セラミックなどで
構成され、各層に配線があってこれらはスルーホールで
連結されるが、この場合はそのスルーホールでパッド４
２，４３を導電層４４へ接続する。このようにすれば、
導電層４４が通常Ａｌより抵抗率の低い金（Ａｕ）であ
ることから、また仮にＡｕでなくとも面積が低抵抗であ
るから電位的にはパッド４２をパッケージ外に導出した
とほぼ等価になる。尚、４５はＶCC用のパッド２１を外
部リードにつなげるパッドである。Therefore, in the present invention, as shown in FIG. 4, the pad 42 on the package 41 side connected to the pad 35 by the bonding wire 40 is different from the pad 43 corresponding to the pad 34 in the external terminal (lead). Try not to connect. Instead, pads 42 and 43 are connected to a conductive layer (typically Au) 44 at the bottom of package 41.
Alternatively, the package 41 is usually composed of a multilayer ceramic or the like, and there are wirings in each layer and these are connected by through holes. In this case, the pads 4 are formed by the through holes.
2, 43 are connected to the conductive layer 44. If you do this,
Since the conductive layer 44 is usually gold (Au) having a resistivity lower than that of Al, and even if it is not Au, the area is low resistance, it is almost equivalent to leading the pad 42 out of the package in terms of potential. . Reference numeral 45 is a pad for connecting the V CC pad 21 to an external lead.

【００１１】[0011]

【発明の効果】以上述べたように本発明によれば、パッ
ケージの外部端子を増加させることなくチップ内部の電
源電圧を均一化できる利点がある。As described above, according to the present invention, there is an advantage that the power supply voltage inside the chip can be made uniform without increasing the number of external terminals of the package.

【図面の簡単な説明】[Brief description of drawings]

【図１】従来のＬＳＩにおける電源系統のレイアウトを
示す平面図である。FIG. 1 is a plan view showing a layout of a power supply system in a conventional LSI.

【図２】ＥＣＬゲートの等価回路図である。FIG. 2 is an equivalent circuit diagram of an ECL gate.

【図３】本発明実施例のＬＳＩにおける電源系統のレイ
アウトを示す説明図である。FIG. 3 is an explanatory diagram showing a layout of a power supply system in the LSI according to the embodiment of the present invention.

【図４】本発明実施例のＬＳＩにおける電源系統のパッ
ド結線を示す説明図である。FIG. 4 is an explanatory diagram showing pad connection of the power supply system in the LSI of the embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１０ チップ ２０ 電源高電圧の配線パターン ３０，３１，３２ 電源低電圧側配線パターン ２１，３４ 電源パッド ３５ 付加電源パッド ４０ ボンディングワイヤ ４１ パッケージ ４２ 付加パッド ４３ 低電位側配線パターン周辺の左右の辺の電源パッ
ドに接続されるスタッド ４４ 導電層10 chips 20 power supply high voltage wiring pattern 30, 31, 32 power supply low voltage side wiring pattern 21, 34 power supply pad 35 additional power supply pad 40 bonding wire 41 package 42 additional pad 43 low potential side power supply on the left and right sides Stud 44 connected to pad 44 Conductive layer

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/04 21/822 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01L 27/04 21/822

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 集積回路チップ（１０）と、 該集積回路チップが搭載される導電層（４４）と、一端
が外部端子に接続され他端が該集積回路チップ上のパッ
ドと接続されている導電パターン（４３）を有するパッ
ケージ基体からなる半導体装置であって、 該集積回路チップ上には、対向する辺の中央付近にそれ
ぞれ配設され、前記導電パターン（４３）と接続される
一対の第１の電源パッド（３４）と、該第１の電源パッ
ド（３４）と該チップ上の電源配線を介して接続され、
該チップのコーナー部に設けられた第２の電源パッド
（３５）を有し、 該パッケージ基体上には、該導電層（４４）及び該導電
層（４４）を介して前記導電パターン（４３）と接続さ
れ、さらに前記第２の電源パッド（３５）と接続され、
且つパッケージ外部には導出されない、選択的に配設さ
れた複数のワイヤ接続用パッド（４２）を備えているこ
とを特徴とする半導体集積回路装置。1. An integrated circuit chip (10), a conductive layer (44) on which the integrated circuit chip is mounted, one end connected to an external terminal and the other end connected to a pad on the integrated circuit chip. What is claimed is: 1. A semiconductor device comprising a package base having a conductive pattern (43), wherein a pair of first semiconductor devices are provided on the integrated circuit chip in the vicinity of the center of opposite sides and are connected to the conductive pattern (43). 1 power supply pad (34) is connected to the first power supply pad (34) via power supply wiring on the chip,
A second power supply pad (35) provided at a corner portion of the chip, the conductive layer (44) and the conductive pattern (43) on the package substrate via the conductive layer (44). And further connected to the second power supply pad (35),
Further, the semiconductor integrated circuit device is provided with a plurality of wire connection pads (42) selectively arranged, which are not led out to the outside of the package.
JP6006908A 1994-01-26 1994-01-26 Semiconductor integrated circuit device Expired - Lifetime JP2520225B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6006908A JP2520225B2 (en) 1994-01-26 1994-01-26 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6006908A JP2520225B2 (en) 1994-01-26 1994-01-26 Semiconductor integrated circuit device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP57230288A Division JPS59124151A (en) 1982-06-30 1982-12-29 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPH0774196A true JPH0774196A (en) 1995-03-17
JP2520225B2 JP2520225B2 (en) 1996-07-31

Family

ID=11651344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6006908A Expired - Lifetime JP2520225B2 (en) 1994-01-26 1994-01-26 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JP2520225B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6080681A (en) * 1998-01-21 2000-06-27 Yamaha Corporation Method of forming wiring pattern
JP2007184544A (en) * 2005-12-29 2007-07-19 Samsung Electronics Co Ltd Heat-radiating semiconductor chip, tape-wiring substrate and tape package using them

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54132273U (en) * 1978-03-03 1979-09-13
JPS5662352A (en) * 1979-10-26 1981-05-28 Hitachi Ltd Semiconductor integrated circuit device for acoustic amplification circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54132273U (en) * 1978-03-03 1979-09-13
JPS5662352A (en) * 1979-10-26 1981-05-28 Hitachi Ltd Semiconductor integrated circuit device for acoustic amplification circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6080681A (en) * 1998-01-21 2000-06-27 Yamaha Corporation Method of forming wiring pattern
JP2007184544A (en) * 2005-12-29 2007-07-19 Samsung Electronics Co Ltd Heat-radiating semiconductor chip, tape-wiring substrate and tape package using them

Also Published As

Publication number Publication date
JP2520225B2 (en) 1996-07-31

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