JPS59100550A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make the width of a wiring pattern narrow, by providing a plurality of pads for connecting power sources. CONSTITUTION:In a semiconductor device such as a memory, a plurality of Vcc pads 2a and 2b and Vss pads 3a and 3b, which supply power to a memory chip 1, are provided. Lead frames 4a, 4b, 5a and 5b are provided in correspondence with the pads. The parts between the pads and the lead frames are connected by bonding wires 6a, 6b, 7a and 7b. Since there are a plurality of power source pads, wiring to each circuit becomes short, and the width of a wiring pattern can be made small without increasing wiring resistance. In this case, not only the power source pads, but also a plurality of input and output pads for signals can be provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor memory device housed in a dual in-line package (hereinafter abbreviated as DIP).

[Prior art]

FIG. 1 shows a schematic structure inside a DIP in a conventional semiconductor memory device of this type. In this Figure 1,
Symbol (1) is a memory chip, (2) is a pad (hereinafter abbreviated as Vcc pad) formed on the chip for supplying power supply voltage to this memory chip (1), (31 is also this memory chip) (1) is a pad (hereinafter abbreviated as Vss pad) formed on the chip to give a ground potential to the lead frame connected to the power supply voltage pin (hereinafter abbreviated as Vcc pin) of the DIP; (
5) is a lead frame that similarly connects to the ground potential pin of the DIP (hereinafter abbreviated as Vss pin), (6) is a bonding wire that electrically connects the Vcc pad (2) and frame (4), and (7) is a A bonding wire electrically connects the Vss pad (3) and the frame (5), and each pad (2+, (31) is formed once per chip.

In this conventional semiconductor memory device, the voltage necessary for device operation is applied from the outside between the Vcc pin and the Vss pin, and the voltage is applied to the lead frames (4), (5), the Vcc pad (21, and the Vss pad (3)). As shown in Figure 2, each of these pads (2+, (3
Vcc wiring (8) mutually extended from 1 to Vss
The power is supplied to each part of the memory circuit via wiring (9).

Therefore, according to this conventional configuration, since there is one each of Vcc and Vss pads (2+, (3)) on the memory chip (1), as in this example, each of these pads (2) , (31 is arranged facing each end of the chip in the longitudinal direction (hereinafter abbreviated as the In order to supply power to the circuit section where the
On the other hand, in order to lower the resistance of this wiring, it is necessary to increase the width of each wiring pattern, which is necessary in the short direction of the chip (hereinafter abbreviated as the X direction). ), but on the other hand, if you try to keep the length in the X direction small, the width of each wiring pattern will become smaller, resulting in increased wiring resistance and the inability to supply sufficient power. was there.

[Summary of the invention]

In view of these conventional drawbacks, the invention of ζ was developed by increasing the number of Vcc and Vss pads per chip, thereby increasing the power applied to the pads without increasing the chip width or wiring resistance. Alternatively, signals can be supplied to circuits on the chip.

[Embodiments of the invention]

Hereinafter, one embodiment of the inventive device will be described in detail with reference to FIGS. 3 and 4.

This is an example in which two Vss pads are provided, and in these figures, (1) is the memory chip, and (2a) is the memory chip.
, (2b), (3a), and (3b) are Vcc and Vss formed two each at the end of the chip in the X direction.
Pads, (4a), (4b) and (5a), (5b)
is connected to each pin of Vcc and Vss, and each pad (
Each lead frame (6a), (6b) provided corresponding to 2a), (2b) and (3a), (3b)
and (7a) and (7b) are the respective pads, lead frames (2a) and (4a), (2b) and (4b)
, (3a) and (5a), bonding wires connecting (ab) and (5b), (8) and (9) are each pad (2a), (2b) and (3a), (
3b) t:r) Vcc and Vss wiring. When actually used as a memory, in order to provide necessary signals in addition to these, from the lead frame connected to each signal pin of the DIP, Connections are made by bonding wires to each pad on the chip for receiving each signal.

However, in this embodiment as well, the power supply voltage is supplied to each circuit formed on the chip through the Vcc and Vss pads (2a), (2b) and (3a), (3b).
This is done through each wiring (8) and (9) on the chip,
The wiring to each circuit at this time is two pads each,
All you have to do is connect it to the easier wire. Now let's consider the cases shown in Figures 2 and 4 as wiring examples.

That is, as shown in Figure 2, each pad of Vcc and Vss (
2) and (3) are the case of the conventional example with one each, and the case of the fourth
Comparing the case where there are 5 pads (2a), (zb) and 2 pads (3a), (3b) each as shown in the figure, the length of the chip (1) in the X direction is L, And if we ignore the length in the X direction, the wiring length from the pad to the farthest position is L/2 in the case of Figure 2 and L/2 in the case of Figure 4, and the sheet resistance is 0.10 mm. With kl wiring,
In order to make the resistance of L==8wn wiring from the pad to the farthest position 0.1 KQ, the width of the wiring is 8 μm in the case of Fig. 2 and 8 μm in the case of Fig. 4. 4μm
becomes. At this time, the difference in area due to the difference in wiring width of 4 μm is approximately 64000 μ−.

If the pad is 100μm x 100μm, the increase in area due to the addition of two pads is 20Ω00.
It becomes μi. Therefore, considering the above conditions,
Compared to FIG. 3, the area of the pad and wiring portion in FIG. 4 can be made smaller.

In the above embodiment, a case has been described in which pads are formed at both ends of the chip in the X direction, but the pads may be formed anywhere on the chip, and each pad may be formed in two or more. Good too.

Furthermore, although the embodiments are for Vcc and Vss pads, it goes without saying that the present invention may also be applied to other signal pads and output pads.

〔Effect of the invention〕

As detailed above, according to the present invention, in a chip having pads for connection with the outside, CC and Vss
Since a plurality of pads and other signal pads are formed at relatively distant positions on the same chip, there is no need to run long wiring on the chip.
This has the advantage of suppressing wiring resistance and reducing the wiring area and ultimately the chip size.

[Brief explanation of drawings]

1 and 2 are plan views, respectively, showing the general configuration and wiring examples of a semiconductor memory device housed in a conventional dual in-line package; FIGS. 3 and 4, respectively.
The figures are plan views showing a schematic configuration and wiring example of the above device to which an embodiment of the present invention is applied. (1) ... temple memory chip, (2a), (2b) and (3a) + (3b) ・""" pad, (4a
), (4b) and (5a), (5b) II @ *
11 lead frame, (6a). (6b) and (7a), (7b) Φ... bonding wire, (8) and (9)... wiring. Agent Makoto Kuzuno - Tube 1 drawing y direction 20 y direction cutting

Claims (3)

[Claims] (1) A semiconductor device having a pad for connection with the outside, characterized in that a plurality of two or more pads for the same input or output signal are provided. (2) The semiconductor device according to claim 1, wherein a plurality of pads are provided for each of the same input or output signal reservoirs, facing each other at both ends of the chip. (3) The semiconductor device according to claim 1 or 2, wherein the same input or output signal is a power supply voltage and a ground potential.