JPH05144996A - Surface mounting semiconductor device - Google Patents
Surface mounting semiconductor deviceInfo
- Publication number
- JPH05144996A JPH05144996A JP3304345A JP30434591A JPH05144996A JP H05144996 A JPH05144996 A JP H05144996A JP 3304345 A JP3304345 A JP 3304345A JP 30434591 A JP30434591 A JP 30434591A JP H05144996 A JPH05144996 A JP H05144996A
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor device
- mounting
- circuit board
- printed circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は表面実装型半導体装置
に係わり、特にアウターリードの形状に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount semiconductor device, and more particularly to the shape of outer leads.
【０００２】[0002]
【従来の技術】表面実装型半導体装置のプリント基板へ
の実装はプリント基板のおもて面に対して行われるばか
りではなく、実装密度を向上させるためにプリント基板
の裏面に対しても行われている。2. Description of the Related Art Mounting a surface mount semiconductor device on a printed circuit board is not only performed on the front surface of the printed circuit board, but also on the back surface of the printed circuit board to improve the mounting density. ing.
【０００３】従来の表面実装型半導体装置をプリント基
板に実装した状態を図４及び図５に示す。図４はパッケ
ージの裏面を実装面とするプリント基板のおもて面に実
装した後の状態である。パッケージ10の両側から出てい
るアウターリード11，11，…の先端が、プリント基板12
上に形成されている図示していない配線に対し、半田13
によって半田付けされている。アウターリード11，11，
…の形状は緩やかなＳ字状になっている。そして、その
先端部分はパッケージ10の底面よりもさらに下側に位置
し、このようなリードの曲げ状態を正曲げと称する。こ
の場合、アウターリード11，11，…はパッケージ10の底
面と基板12との間隔（スタンドオフ）が約０．１ｍｍに
なるように曲げられている。なお、図において、14は半
導体チップ、15はベット、16，16，…はボンディングワ
イヤである。FIGS. 4 and 5 show a state in which a conventional surface mount semiconductor device is mounted on a printed circuit board. FIG. 4 shows a state after the package is mounted on the front surface of the printed circuit board with the back surface of the package as the mounting surface. The ends of the outer leads 11, 11, ...
For the wiring not shown, which is formed above, solder 13
Soldered by. Outer leads 11, 11,
The shape of ... is a gentle S-shape. The tip portion is located further below the bottom surface of the package 10, and such a bent state of the lead is called normal bending. In this case, the outer leads 11, 11, ... Are bent so that the space (standoff) between the bottom surface of the package 10 and the substrate 12 is about 0.1 mm. In the figure, 14 is a semiconductor chip, 15 is a bed, and 16, 16, ... Are bonding wires.
【０００４】図５はパッケージの上面を実装面とし、プ
リント基板12の裏面に実装した後の状態を示す。なお、
図５において図４と対応する箇所には同じ符号を付して
説明を行う。この場合、プリント基板12の裏面に実装さ
れる表面実装型半導体装置はアウターリード11，11，…
それぞれのプリント基板12に対する配置がおもて面実装
のものと同じになるようにされる。したがって、アウタ
ーリード11，11，…に対する上記Ｓ字状の曲げ加工は、
パッケージ10をおもて面に実装するものとは逆にして行
われる。この場合、アウターリード11，11，…の先端部
分はパッケージ10の上側よりもさらに上側に位置し、こ
のようなリードの曲げ形状を逆曲げと称する。FIG. 5 shows a state after the package is mounted on the back surface of the printed circuit board 12 with the upper surface of the package as the mounting surface. In addition,
In FIG. 5, the portions corresponding to those in FIG. In this case, the surface mount type semiconductor device mounted on the back surface of the printed circuit board 12 has outer leads 11, 11, ...
The layout of each printed circuit board 12 is the same as that of the front surface mounting. Therefore, the S-shaped bending process for the outer leads 11, 11, ...
This is performed in reverse to the case where the package 10 is mounted on the front surface. In this case, the tip portions of the outer leads 11, 11, ... Are located further above the upper side of the package 10, and such a bent shape of the leads is called reverse bending.
【０００５】[0005]
【発明が解決しようとする課題】上記従来技術では表面
実装型半導体装置にはアウターリードの曲げ方により正
曲げと逆曲げの２種類がある。このため、アウターリー
ド11，11，…の曲げ加工の際にミスが生じるという問題
がある。これはパッケージ10の上下の面には外観状大き
な違いがないため、アウターリードの曲げ加工を行う装
置にパッケージ10の上下を逆にセットしてしまうために
起こる。このため、本来は正曲げのものを製造しようと
したのに逆曲げのものができたり、逆に逆曲げのものを
製造しなければならないのに正曲げのものができるとい
う問題である。In the above-mentioned prior art, there are two types of surface mount type semiconductor devices: forward bending and reverse bending, depending on how the outer leads are bent. For this reason, there is a problem in that a mistake occurs during bending of the outer leads 11, 11, .... This is because there is no large difference in appearance between the upper and lower surfaces of the package 10, and the upper and lower sides of the package 10 are set upside down in an apparatus for bending outer leads. For this reason, there is a problem that an originally bent product can be manufactured while a reverse bent product can be produced, or a reverse bent product can be manufactured while a reverse bent product can be manufactured.
【０００６】この発明は上記のような事情を考慮してな
されたものであり、その目的は、プリント基板のおもて
面及び裏面の両方に実装することが出来る表面実装型半
導体装置を提供することである。The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a surface mount semiconductor device which can be mounted on both the front surface and the back surface of a printed circuit board. That is.
【０００７】[0007]
【課題を解決するための手段】この発明による表面実装
型半導体装置は上面、下面及び側面を有する樹脂封止型
パッケージと、上記パッケージの側面から導出され、こ
のパッケージの上面よりも上部に位置する第１の実装部
及びこのパッケージの下面よりも下部に位置する第２の
実装部を有する形状に折曲げ形成されたアウターリード
とを具備したことを特徴とする。A surface mount semiconductor device according to the present invention is a resin-sealed package having an upper surface, a lower surface and a side surface, and is guided from the side surface of the package and is located above the upper surface of the package. It is characterized by comprising an outer lead bent into a shape having a first mounting portion and a second mounting portion located below the lower surface of the package.
【０００８】[0008]
【作用】この発明による表面実装型半導体装置は以上の
ような構成であるから、パッケージの上面、下面のどち
らも実装面とすることができる。Since the surface mount type semiconductor device according to the present invention has the above-mentioned structure, both the upper surface and the lower surface of the package can be mounted surfaces.
【０００９】[0009]
【実施例】以下、図面を参照しながらこの発明を実施例
により説明する。図１はこの発明の第１の実施例に係る
表面実装型半導体装置をプリント基板のおもて面に実装
した状態の断面を示している。図２は同じ表面実装型半
導体装置をプリント基板の裏面に実装した状態の断面を
示している。図において、半導体チップ20はベット21上
に接着固定されている。そして、半導体チップ20上の図
示しない電極とインナーリード22，22，…とがボンディ
ングワイヤ23，23，…により電気的に接続されている。
これらは樹脂によるパッケージ24によって封止されてい
る。そして、パッケージ24の各側面からアウターリード
25，25，…が導出されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a cross section of a state in which a surface mount semiconductor device according to a first embodiment of the present invention is mounted on the front surface of a printed circuit board. FIG. 2 shows a cross section of the same surface mount semiconductor device mounted on the back surface of a printed circuit board. In the figure, a semiconductor chip 20 is adhesively fixed onto a bed 21. The electrodes (not shown) on the semiconductor chip 20 and the inner leads 22, 22, ... Are electrically connected by the bonding wires 23, 23 ,.
These are sealed by a resin package 24. Then, from each side of the package 24, the outer leads
25, 25, ... have been derived.
【００１０】これらのアウターリード25，25，…は直線
状リードを折曲げ加工することにより形成されており、
それぞれパッケージ24の上面と平行しこの上面よりも上
部に位置する第１の平坦な実装部26と、パッケージ24の
下面と平行しこの下面よりも下部に位置する第２の平坦
な実装部27と、上記第１の実装部26とパッケージ24から
の導出部分とを連結する第１連結部28と、上記第１の実
装部26と第２の実装部27とを連結する第２連結部29とか
ら構成されている。そして、パッケージ24のアウターリ
ードの導出部分が第１の実装部26と第２の実装部27のほ
ぼ中間に位置し、また、図１のようにパッケージ24の下
面をプリント基板30に対する実装面としたとき、第２の
実装部27とパッケージ24の下面との間の間隔（図１中の
ｔ１）が約０．１ｍｍとなるように折曲げ加工がなされ
ている。同様に図２のようにパッケージ24の上面をプリ
ント基板30に対する実装面としたとき、第１の実装部26
とパッケージ24の上面との間の間隔（図２中のｔ２）が
約０．１ｍｍとなるように折り曲げ加工がなされてい
る。These outer leads 25, 25, ... Are formed by bending straight leads.
A first flat mounting portion 26 that is parallel to the upper surface of the package 24 and is located above the upper surface, and a second flat mounting portion 27 that is parallel to the lower surface of the package 24 and is located below the lower surface. A first connecting portion 28 connecting the first mounting portion 26 and a lead-out portion from the package 24, and a second connecting portion 29 connecting the first mounting portion 26 and the second mounting portion 27. It consists of The outer lead lead-out portion of the package 24 is located approximately in the middle of the first mounting portion 26 and the second mounting portion 27, and the lower surface of the package 24 serves as a mounting surface for the printed circuit board 30 as shown in FIG. At this time, the bending process is performed so that the distance (t1 in FIG. 1) between the second mounting portion 27 and the lower surface of the package 24 becomes about 0.1 mm. Similarly, when the upper surface of the package 24 is the mounting surface for the printed circuit board 30 as shown in FIG.
Bending is performed so that the distance between the upper surface of the package 24 and the upper surface of the package 24 (t2 in FIG. 2) is about 0.1 mm.
【００１１】そして、この表面実装型半導体装置のパッ
ケージ24の底面を実装面とするプリント基板30のおもて
面への実装は、第２の実装部27とプリント基板30上の図
示していない配線パターンとを半田31により半田付けす
ることにより行う。また、この表面実装型半導体装置の
パッケージ24の上面を実装面とするプリント基板30の裏
面への実装は、第１の実装部26とプリント基板30裏面上
の図示していない配線パターンとを半田31により半田付
けすることにより行う。The mounting of the surface mounting type semiconductor device on the front surface of the printed circuit board 30 whose mounting surface is the bottom surface of the package 24 is not shown on the second mounting portion 27 and the printed circuit board 30. This is performed by soldering the wiring pattern to the solder 31. Further, the mounting of the surface mounting type semiconductor device on the back surface of the printed circuit board 30 having the upper surface of the package 24 as the mounting surface is performed by soldering the first mounting portion 26 and a wiring pattern (not shown) on the back surface of the printed circuit board 30. It is done by soldering with 31.
【００１２】上記実施例のような表面実装型半導体装置
は、アウターリードにパッケージの上面及び下面よりも
外側に出ている実装部分を有する。このため、パッケー
ジの上面と下面のどちらの面も実装面とすることができ
る。従って、従来のように実装面の違いによりアウター
リードの形状を変える必要がなく、１種類のもので対応
することができるので、アウターリードの曲げ加工にお
いて正曲げと逆曲げとを間違えて行うようなことは起こ
らない。次にパーケージの上面と下面のどちらの面も実
装面とすることができるこの発明の第２ないし第４の各
実施例を説明する。The surface-mounting type semiconductor device as in the above-mentioned embodiment has the mounting portion on the outer lead, which is outside the upper and lower surfaces of the package. Therefore, both the upper surface and the lower surface of the package can be the mounting surface. Therefore, it is not necessary to change the shape of the outer lead due to the difference in mounting surface as in the conventional case, and one type can be used. Nothing happens. Next, second to fourth embodiments of the present invention in which both the upper surface and the lower surface of the package can be used as mounting surfaces will be described.
【００１３】図３（ａ）はこの発明の第２の実施例に係
る表面実装型半導体装置のアウターリード部の断面形状
を示している。この実施例のアウターリードには第１実
施例のアウターリード25，25，…の第２の平坦な実装部
27の端部からパッケージ24のアウターリード25，25，…
の導出部分に延びる立上がり部32がさらに設けられてい
る。FIG. 3A shows a sectional shape of an outer lead portion of a surface mount semiconductor device according to a second embodiment of the present invention. The outer leads of this embodiment include the second flat mounting portions of the outer leads 25, 25, ... Of the first embodiment.
From the end of 27, the outer leads 25, 25 of the package 24, ...
Further provided is a rising portion 32 extending to the lead-out portion.
【００１４】図３（ｂ）はこの発明の第３の実施例に係
る表面実装型半導体装置のアウターリード部の断面形状
を示している。この実施例のアウターリードは第１実施
例のアウターリード25，25，…の第２連結部29の一部が
半円状に折曲げ加工されたものである。FIG. 3B shows a sectional shape of the outer lead portion of the surface mount semiconductor device according to the third embodiment of the present invention. In the outer lead of this embodiment, a part of the second connecting portion 29 of the outer leads 25, 25, ... Of the first embodiment is bent into a semicircular shape.
【００１５】図３（ｃ）はこの発明の第４の実施例に係
る表面実装型半導体装置のアウターリード部の断面形状
を示している。この発明のアウターリードは第１実施例
のアウターリード25，25，…の第２連結部29に対する第
２の平坦な実装部27の曲げ方向を第１実施例とほぼ逆に
したものである。上記第２ないし第４の各実施例の半導
体装置においても、１種類のものでプリント基板のおも
て面と裏面の両方に実装することができる。なお、上記
各実施例において、第１、第２の実装部は平坦に形成し
たが、必ずしも平坦である必要はなく湾曲又は屈曲して
も良い。FIG. 3C shows a cross-sectional shape of the outer lead portion of the surface mount semiconductor device according to the fourth embodiment of the present invention. In the outer lead of the present invention, the bending direction of the second flat mounting portion 27 with respect to the second connecting portion 29 of the outer leads 25, 25, ... Of the first embodiment is substantially the same as that of the first embodiment. Also in the semiconductor devices of the second to fourth embodiments, one type can be mounted on both the front surface and the back surface of the printed circuit board. In each of the above embodiments, the first and second mounting parts are formed flat, but they are not necessarily flat and may be curved or bent.
【００１６】[0016]
【発明の効果】以上説明したように、この発明によれば
プリント基板のおもて面及び裏面の両方に実装すること
が出来る表面実装型半導体装置を提供することが出来
る。As described above, according to the present invention, it is possible to provide a surface mount type semiconductor device which can be mounted on both the front surface and the back surface of a printed circuit board.
【図１】この発明による第１の実施例に係る表面実装型
半導体装置の断面図。FIG. 1 is a sectional view of a surface mount semiconductor device according to a first embodiment of the present invention.
【図２】この発明による第１の実施例に係る表面実装型
半導体装置の断面図。FIG. 2 is a cross-sectional view of the surface mount semiconductor device according to the first embodiment of the present invention.
【図３】この発明による第２、第３、第４の実施例に係
る表面実装型半導体装置のアウターリード部の断面図。FIG. 3 is a sectional view of an outer lead portion of a surface mount semiconductor device according to second, third and fourth embodiments of the present invention.
【図４】従来の表面実装型半導体装置の断面図。FIG. 4 is a cross-sectional view of a conventional surface mount semiconductor device.
【図５】従来の表面実装型半導体装置の断面図。FIG. 5 is a cross-sectional view of a conventional surface mount semiconductor device.
20…半導体チップ、24…パッケージ、25…アウターリー
ド。20… Semiconductor chip, 24… Package, 25… Outer lead.
Claims (1)
パッケージと、 上記パッケージの側面から導出され、このパッケージの
上面よりも上部に位置する第１の実装部及びこのパッケ
ージの下面よりも下部に位置する第２の実装部を有する
形状に折曲げ形成されたアウターリードとを具備したこ
とを特徴とする表面実装型半導体装置。1. A resin-sealed package having an upper surface, a lower surface and a side surface, a first mounting portion which is led out from a side surface of the package and is located above the upper surface of the package, and a lower surface of the lower surface of the package. A surface mounting type semiconductor device comprising: an outer lead bent to a shape having a second mounting portion located at
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3304345A JPH05144996A (en) | 1991-11-20 | 1991-11-20 | Surface mounting semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3304345A JPH05144996A (en) | 1991-11-20 | 1991-11-20 | Surface mounting semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05144996A true JPH05144996A (en) | 1993-06-11 |
Family
ID=17931898
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3304345A Pending JPH05144996A (en) | 1991-11-20 | 1991-11-20 | Surface mounting semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05144996A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19507573A1 (en) * | 1994-03-30 | 1995-10-05 | Gold Star Electronics | Conductor structure for semiconductor housing |
| US5723903A (en) * | 1992-05-25 | 1998-03-03 | Hitachi, Ltd. | Thin type semiconductor device, module structure using the device and method of mounting the device on board |
| US6114759A (en) * | 1998-04-23 | 2000-09-05 | Nec Corporation | Semiconductor package |
-
1991
- 1991-11-20 JP JP3304345A patent/JPH05144996A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5723903A (en) * | 1992-05-25 | 1998-03-03 | Hitachi, Ltd. | Thin type semiconductor device, module structure using the device and method of mounting the device on board |
| US5895969A (en) * | 1992-05-25 | 1999-04-20 | Hitachi, Ltd. And Hitachi Vlsi Engineering Corp. | Thin type semiconductor device, module structure using the device and method of mounting the device on board |
| DE19507573A1 (en) * | 1994-03-30 | 1995-10-05 | Gold Star Electronics | Conductor structure for semiconductor housing |
| DE19507573C2 (en) * | 1994-03-30 | 2002-11-21 | Gold Star Electronics | Conductor structure for a semiconductor package and semiconductor package with such a conductor structure |
| US6114759A (en) * | 1998-04-23 | 2000-09-05 | Nec Corporation | Semiconductor package |
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