JPH04179211A - Chip-type capacitor - Google Patents
Chip-type capacitorInfo
- Publication number
- JPH04179211A JPH04179211A JP2307659A JP30765990A JPH04179211A JP H04179211 A JPH04179211 A JP H04179211A JP 2307659 A JP2307659 A JP 2307659A JP 30765990 A JP30765990 A JP 30765990A JP H04179211 A JPH04179211 A JP H04179211A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- capacitor
- package
- type capacitor
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 31
- 238000005476 soldering Methods 0.000 abstract description 6
- 238000005452 bending Methods 0.000 abstract description 2
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000007667 floating Methods 0.000 description 2
- 210000004899 c-terminal region Anatomy 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/301—Assembling printed circuits with electric components, e.g. with resistor by means of a mounting structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、チップ型コンデンサに関し、特にI、S■パ
ッケージに実装するチップ型コンデンサに関する1、
1従来の技(A:j i
1χ来の−1−・ノブ型コンデンザは第4図に示すよう
に、コンテンザ本体1の両端に容量電極と接続して設り
た端子2を有して構成され、第5図に示すように、1.
S Iパッケージ・1に設けたパラ1へ電極7にチッ
プ型コンデンサの端子2を半田8て接合し、実装してい
た。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to chip-type capacitors, and particularly to chip-type capacitors mounted in I, S ■ packages. -1- As shown in FIG. 4, the knob-type capacitor is constructed with terminals 2 provided at both ends of a condenser body 1 connected to capacitive electrodes, and as shown in FIG.
The terminal 2 of the chip type capacitor was connected to the electrode 7 of the SI package 1 by soldering 8 and was mounted.
し発明か解決しようとする課題〕
この従来のチップ型コンデンサは、LSIパッケージの
パッド電極に端子を半田付けする際に、端子がパッド電
極からずれたり、チップ型コンデンサが浮上って逆立ち
したり、チップ型コンデンサの下面に半田の層かつなか
ってブリッジ状になり、チップ型コンデンサの端子間を
短絡させる等の事故を発生させるという問題点があった
。[Problems to be Solved by the Invention] This conventional chip-type capacitor has problems such as when the terminal is soldered to the pad electrode of the LSI package, the terminal shifts from the pad electrode, the chip-type capacitor floats up, and stands on end. There is a problem in that the solder layer is not formed on the bottom surface of the chip capacitor, creating a bridge-like shape, which can cause accidents such as short circuits between the terminals of the chip capacitor.
また、このような事故は半田付作業時の半田の質・量に
深く関係しており、これを安定に保つには高度な半田付
(・す技術を必要とする。これにより、チップ部品を実
装しないl、 S Iパッケージに比べてチップ部品を
実装するり、、 S Iパッケージはその製造工程にお
いて技術的に高度な半田付は工程を必要とするという問
題点かあった。In addition, such accidents are deeply related to the quality and quantity of solder during soldering work, and in order to keep it stable, advanced soldering technology is required. Compared to an SI package that does not require mounting, there are problems in that the SI package requires a technically advanced soldering process to mount chip components in its manufacturing process.
本発明のチップ型=1ンデンザは、外部回路接続用σ)
端子を右するチップ型コンデンサにおいて、前記チ・ツ
ブ型コ〉テンサを実装するパッケージのリーI〜に対応
し、て前記端子に設けたカイI・を備えている4、
[実施例]
次に、本発明についてに1面を参叩し2て説明する、。The chip type = 1 ndenza of the present invention is for external circuit connection σ)
A chip type capacitor having terminals on the right side is provided with a chi I provided on the terminal in correspondence with a chip I of the package in which the chip type capacitor is mounted.4. [Example] Next , the present invention will be explained by referring to page 1 and page 2.
第1図は+、発明の第1σ)実施例を示す斜視図である
。FIG. 1 is a perspective view showing a first σ) embodiment of the invention.
第1図に示すよう(1こ、容量電極を禽むコンデンサ本
体1と、容量電極に接続してコンデンサ本体] (7’
1両端に設けた端子2と、実装するパッケージθ゛)リ
ードの位置、形状に対応し゛C端子2の夫/Zの側面に
設げた樋状の凹部からなるガイド3とを有して構成され
る、。As shown in FIG.
1, and a guide 3 consisting of a gutter-like recess provided on the side surface of the C terminal 2 corresponding to the position and shape of the package θ') lead to be mounted. Ru,.
第2[4は本発明の第1の実施例のチップ型コンデンサ
の実装状!ルを示す模式的平面図である。2nd [4 is the mounting state of the chip type capacitor of the first embodiment of the present invention! FIG.
第2図に示すように、I C1: ”/−ツブを搭載し
てA−ヤ・ツブ5により封正し、ICチップと電気的に
接続しなり一部6を有するLSIパッケージ4のリード
6にガイド3を嵌込んでチップ型コンデンサを装着しリ
ート6と端子2を半田により接合する。As shown in FIG. 2, the lead 6 of the LSI package 4 is mounted with an IC1/- lug and sealed with an A-ya lug 5, and is electrically connected to the IC chip and has a bent portion 6. The guide 3 is fitted into the chip capacitor, and the chip capacitor is attached, and the lead 6 and the terminal 2 are joined by soldering.
ここでチップ型コンデンサはガイド3により2本のリー
ト6の間に位置決めされて固定でき、ずれや浮−Eりを
防止でき、また、リード6を折曲げることにより、機械
的にも確実な固定か可能である。Here, the chip type capacitor can be positioned and fixed between the two leads 6 by the guide 3, preventing it from shifting or floating, and by bending the leads 6, it can be fixed mechanically. It is possible.
第3図は本発明の第2の実施例を示す斜視図である。FIG. 3 is a perspective view showing a second embodiment of the invention.
第3図に示すように、ガイド3が端子2に設けた筒状の
貫通孔からなる以外は第1の実施例と同様の構成を有し
ており、実装時にはパッケージのリードをガイド3に挿
入して半田付(すする。As shown in FIG. 3, the guide 3 has the same structure as the first embodiment except that it consists of a cylindrical through hole provided in the terminal 2, and the leads of the package are inserted into the guide 3 during mounting. and solder.
以上説明したように本発明は、チ・ツブ型コンデンザの
端子にLSIパッケージのり一1’に対応するガイドを
設けることにより、LSIパッケージに実装する際の位
置ずれや、浮上りを防止してL3lパツケージへの接続
不良を防止することができるという効果を有する。As explained above, the present invention provides guides corresponding to the LSI package glue 1' on the terminals of the chip type capacitor, thereby preventing positional shift and floating when mounting on the LSI package. This has the effect of preventing poor connection to the package.
第1図は本発明の第1の実施例を示す斜視図、第2国は
本発明の第1の実施例のチップ型コンデンサの実装状態
を示す模式的平面図、第3図は本発明の第2の実施例を
示す斜視図、第4(21は従来のチップ型コンデンサの
一例を示す斜視図、第5図は従来のチップ型コンデンサ
の実装状態を示す一部切欠側面図である。
]・・・コンデンサ本体、2・・・端子、3・・・ガイ
ド、4・・・LSIパッケージ、5・・・キャップ、6
・・リード、7・・パッド電極、8・・半田。FIG. 1 is a perspective view showing the first embodiment of the present invention, FIG. 2 is a schematic plan view showing the mounting state of the chip capacitor of the first embodiment of the present invention, and FIG. 21 is a perspective view showing an example of a conventional chip-type capacitor, and FIG. 5 is a partially cutaway side view showing a mounting state of the conventional chip-type capacitor.] ...Capacitor body, 2...Terminal, 3...Guide, 4...LSI package, 5...Cap, 6
...Lead, 7..Pad electrode, 8..Solder.
Claims (1)
において、前記チップ型コンデンサを実装するパッケー
ジのリードに対応して前記端子に設けたガイドを備えた
ことを特徴とするチップ型コンデンサ。A chip-type capacitor having a terminal for external circuitry and connection, characterized in that the chip-type capacitor is provided with a guide provided on the terminal in correspondence with a lead of a package in which the chip-type capacitor is mounted.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2307659A JPH04179211A (en) | 1990-11-14 | 1990-11-14 | Chip-type capacitor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2307659A JPH04179211A (en) | 1990-11-14 | 1990-11-14 | Chip-type capacitor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04179211A true JPH04179211A (en) | 1992-06-25 |
Family
ID=17971707
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2307659A Pending JPH04179211A (en) | 1990-11-14 | 1990-11-14 | Chip-type capacitor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04179211A (en) |
-
1990
- 1990-11-14 JP JP2307659A patent/JPH04179211A/en active Pending
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