JPS6240442Y2 - - Google Patents
Info
- Publication number
- JPS6240442Y2 JPS6240442Y2 JP1274380U JP1274380U JPS6240442Y2 JP S6240442 Y2 JPS6240442 Y2 JP S6240442Y2 JP 1274380 U JP1274380 U JP 1274380U JP 1274380 U JP1274380 U JP 1274380U JP S6240442 Y2 JPS6240442 Y2 JP S6240442Y2
- Authority
- JP
- Japan
- Prior art keywords
- package
- terminal
- solder
- terminal portion
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000011347 resin Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 description 21
- 239000011888 foil Substances 0.000 description 8
- 238000005476 soldering Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
【考案の詳細な説明】 この考案は半導体装置に関する。[Detailed explanation of the idea] This invention relates to a semiconductor device.
トランジスタ、ダイオード、IC回路などの半
導体装置において、樹脂製のパツケージを使用す
ることが行なわれており、この場合引出された端
子はパツケージの側面と裏面とにまたがつて形成
され、リードレスとしたものがある。そしてこの
半導体装置をプリント基板に装填するとき、パツ
ケージの裏面に形成された端子部をプリント基板
上の導体箔に直接接触させ、パツケージの側面に
形成された端子部と前記導体箔とを半田づけする
ようにしている。 Resin packages are used in semiconductor devices such as transistors, diodes, and IC circuits, and in this case, the pulled out terminals are formed across the sides and back of the package, making it leadless. There is something. When loading this semiconductor device onto a printed circuit board, the terminal section formed on the back side of the package is brought into direct contact with the conductive foil on the printed circuit board, and the terminal section formed on the side surface of the package and the conductive foil are soldered. I try to do that.
第3図は上記した半田づけの状態を示すもの
で、1はプリント基板、2は導体箔、3はパツケ
ージ、4は端子である。端子4はパツケージ3の
ひとつの面(たとえばこれを正面とする。)3a
及び裏面3bとにまたがつて沿うように形成され
てある。半田づけの際は裏面3bに沿う端子部分
が導体箔2に接するようにパツケージ3をプリン
ト基板1の表面に接着剤などで仮止めし、図のよ
うにプリント基板1を裏返してパツケージ3の表
面3cを下向けとし、このまま半田5内に浸漬け
するようにしている。 FIG. 3 shows the soldering state described above, where 1 is a printed circuit board, 2 is a conductor foil, 3 is a package, and 4 is a terminal. The terminal 4 is connected to one surface of the package cage 3 (for example, this is the front surface) 3a
and the back surface 3b. When soldering, temporarily attach the package 3 to the surface of the printed circuit board 1 with adhesive so that the terminal portion along the back surface 3b is in contact with the conductor foil 2, and then turn the printed circuit board 1 over as shown in the figure and attach the package 3 to the surface of the package 3. 3c is facing downward and is immersed in the solder 5 as it is.
ところが上記のように半田5内に浸漬けすると
き、パツケージ3を構成している樹脂はその種類
の如何を問わず半田に対してぬれにくいのでパツ
ケージ3の表面3cは半田5に押しつけられて接
触するものの、周囲の各面ではプリント基板1に
近づく程半田が近づきにくくなり、半田が附着し
ない空間6が存在するようになる。そのため端子
4の位置がパツケージ3の正面3a中央に近づけ
ば近づく程、その端子4には半田が近づくことが
なく、そのため端子4と導体箔2との半田づけが
極めて困難となる。このような現象はパツケージ
3が極めて小さい場合(たとえば幅2〜3mm、高
さ1〜2mm程度)に顕著に現われる。 However, when dipping into the solder 5 as described above, the surface 3c of the package 3 is pressed against the solder 5 and comes into contact with the solder 5 because the resin that makes up the package 3 is difficult to wet with solder regardless of its type. However, on each of the surrounding surfaces, the closer the printed circuit board 1 is, the more difficult it is for the solder to approach the printed circuit board 1, and there are spaces 6 where no solder adheres. Therefore, the closer the position of the terminal 4 is to the center of the front surface 3a of the package 3, the less the solder approaches the terminal 4, which makes it extremely difficult to solder the terminal 4 and the conductor foil 2. Such a phenomenon appears conspicuously when the package 3 is extremely small (for example, about 2 to 3 mm in width and 1 to 2 mm in height).
この考案は端子と導体箔との半田づけが確実に
なるようにすることを目的とする。 The purpose of this invention is to ensure reliable soldering between the terminal and the conductive foil.
この考案の実施例を図によつて説明すると、1
1は半導体装置の樹脂製のパツケージ、12はパ
ツケージ11の正面11a側の端子、13は同じ
く背面側の端子である。端子12はパツケージ1
1の正面11aに沿う端子部12aと、パツケー
ジ11の裏面11bに沿う端子部12bとによつ
て形成されてある。端子12の上記した形成は従
来のものと大差はないが、この考案では端子部1
2aから、パツケージ11の正面からみて横方向
に延長する端子部12cが形成されてある。 An example of this invention will be explained with the help of diagrams: 1
1 is a resin package of a semiconductor device, 12 is a terminal on the front side 11a of the package 11, and 13 is a terminal on the back side. Terminal 12 is package 1
1 and a terminal portion 12b along the back surface 11b of the package 11. The above-described formation of the terminal 12 is not much different from the conventional one, but in this invention, the terminal portion 1
A terminal portion 12c is formed from 2a to extend laterally when viewed from the front of the package 11.
半田づけに際しては、プリント基板1に接着剤
などにより、パツケージ11をその裏面11bを
接着して仮止めし、その際端子部12bが導体箔
2と直接接するようにし、このプリント基板1を
裏返してパツケージ11の表面11cを下向けと
し、半田5内に浸漬けする。これらのことは従来
の場合と何ら異なるところはない。 When soldering, the package 11 is temporarily attached to the printed circuit board 1 by gluing its back surface 11b with an adhesive or the like, so that the terminal portion 12b is in direct contact with the conductor foil 2, and the printed circuit board 1 is turned over. The package 11 is immersed in the solder 5 with the surface 11c facing downward. These things are no different from the conventional case.
しかしながらこのとき表面11cは半田5に押
しつれられることによつて、第2図に示すように
端子部12cの端部が半田5に接するようにな
る。端子12は金属製であるから、パツケージ1
1を構成している樹脂に比較すれば遥かに半田に
対してぬれやすいため、半田5は端子部12cか
ら端子部12aに沿つて容易に流れていくように
なる。これによつて端子部12aに全面的に半田
5が接するようになる。以上によつて端子部12
aと導体箔2とが確実に半田づけされることにな
るのである。 However, at this time, the surface 11c is pressed against the solder 5, so that the end of the terminal portion 12c comes into contact with the solder 5, as shown in FIG. Since the terminal 12 is made of metal, the package 1
Since the solder 5 is much more easily wetted by solder than the resin composing the solder 1, the solder 5 easily flows from the terminal portion 12c to the terminal portion 12a. As a result, the solder 5 comes into full contact with the terminal portion 12a. As a result of the above, the terminal portion 12
This ensures that a and the conductive foil 2 are soldered together.
この場合第1図に示すように端子部12cをパ
ツケージ11の端面11cに近い個所に設けるほ
ど半田55に接しやすくなつて都合がよい。又端
子部12cはパツケージ11の端面11dの近く
まで延長させておくのが望ましい。上記の説明は
端子12について説明したが、背面側の端子13
についても同じように横方向に延長させておくと
よい。13cはその延長した端子部を示す。更に
端子12に、パツケージ11の表面11cにまで
またがるように端子部12dを形成しておくと、
端子部12dが半田5に接することによつてこの
端子部12dに沿つて半田が流れて端子部12a
に附着するようになつて都合がよい。 In this case, as shown in FIG. 1, the closer the terminal portion 12c is to the end surface 11c of the package 11, the more convenient it will be to contact the solder 55. Further, it is desirable that the terminal portion 12c extend close to the end surface 11d of the package 11. The above explanation was about the terminal 12, but the terminal 13 on the back side
It is also a good idea to extend it horizontally in the same way. 13c shows the extended terminal portion. Furthermore, if a terminal portion 12d is formed on the terminal 12 so as to extend over the surface 11c of the package 11,
When the terminal portion 12d comes into contact with the solder 5, the solder flows along the terminal portion 12d, and the solder flows to the terminal portion 12a.
It is convenient that it has become attached to .
以上詳述したようにこの考案によれば、パツケ
ージの正面に形成される端子を横方向に延長して
形成するといつた簡単な構成によつてプリント基
板への半田づけを確実にすることができる効果を
奏する。 As detailed above, according to this invention, soldering to the printed circuit board can be ensured through a simple configuration in which the terminals formed on the front of the package are extended laterally. be effective.
第1図はこの考案の実施例を示す斜視図、第2
図は半田づけ状態を示す断面図、第3図は従来例
の半田づけ状態を示す断面図である。
11……パツケージ、11a……正面、11b
……裏面、11c……表面、12……端子部、1
2a,12b……端子部、12c……延長された
端子部。
Figure 1 is a perspective view showing an embodiment of this invention;
The figure is a sectional view showing a soldered state, and FIG. 3 is a sectional view showing a conventional soldering state. 11...Package, 11a...Front, 11b
... Back side, 11c... Front side, 12... Terminal section, 1
2a, 12b...terminal part, 12c...extended terminal part.
Claims (1)
たがる端子を形成するとともに、前記端子をその
正面において横方向に延長せしめてなる半導体装
置。 A semiconductor device comprising a resin package, in which terminals are formed across the front and back surfaces of the package, and the terminals are extended laterally on the front surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1274380U JPS6240442Y2 (en) | 1980-02-04 | 1980-02-04 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1274380U JPS6240442Y2 (en) | 1980-02-04 | 1980-02-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56114550U JPS56114550U (en) | 1981-09-03 |
JPS6240442Y2 true JPS6240442Y2 (en) | 1987-10-16 |
Family
ID=29609306
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1274380U Expired JPS6240442Y2 (en) | 1980-02-04 | 1980-02-04 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6240442Y2 (en) |
-
1980
- 1980-02-04 JP JP1274380U patent/JPS6240442Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS56114550U (en) | 1981-09-03 |
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