JPS5810366Y2 - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPS5810366Y2 JPS5810366Y2 JP1976095047U JP9504776U JPS5810366Y2 JP S5810366 Y2 JPS5810366 Y2 JP S5810366Y2 JP 1976095047 U JP1976095047 U JP 1976095047U JP 9504776 U JP9504776 U JP 9504776U JP S5810366 Y2 JPS5810366 Y2 JP S5810366Y2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit device
- hybrid integrated
- soldering
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Multi-Conductor Connections (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
本考案は外部リードの半田付ショートを無くす混成集積
回路装置の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a hybrid integrated circuit device that eliminates soldering short circuits of external leads.
第１図は従来の混成集積回路装置の構造を示し、１は絶
縁基板で該基板上には導体、抵抗等を印刷、焼成により
形成しである。FIG. 1 shows the structure of a conventional hybrid integrated circuit device. Reference numeral 1 denotes an insulating substrate on which conductors, resistors, etc. are formed by printing and firing.
２は半田レジストで半田付導体部３を除いた部分に印刷
等により形成される。2 is a solder resist, which is formed by printing or the like on a portion other than the soldered conductor portion 3.
４は外部リードで半田付導体部３にて半田ディツプ等の
方法により半田付して取付けられている。Reference numeral 4 denotes an external lead which is attached to the soldered conductor portion 3 by soldering by a method such as solder dipping.
しかしながら第１図に示すものにおいては外部）−ド４
を半田デ゛イツプ等により半田付する場合、半田レジス
ト２の半田付導体部３側のレジスト辺５が直線で形成さ
れているので、隣り合う半田付導体部３，３′間におい
てレジスト辺５と基板１との境界部に微量の半田が付着
する場合があり、このときには隣接した導体部３，３′
をショートさせてしまうという欠点があった。However, in the case shown in FIG.
When soldering with a solder dip or the like, the resist side 5 on the soldering conductor portion 3 side of the solder resist 2 is formed in a straight line, so the resist side 5 is formed between the adjacent soldering conductor portions 3 and 3'. A small amount of solder may adhere to the boundary between the board 1 and the adjacent conductor parts 3, 3'.
It had the disadvantage of shorting out the .
本考案は上記した従来技術の欠点を解決し、半田ショー
トを無くし歩留りを向上させた混成集積回路装置を提供
するにある。The present invention solves the above-mentioned drawbacks of the prior art, and provides a hybrid integrated circuit device that eliminates solder shorts and improves yield.
以下本考案の具体的実施例について第２図に従い説明す
る。A specific embodiment of the present invention will be described below with reference to FIG.
第２図において、１は絶縁基板で基板上には導体、抵抗
等が印刷、焼成により形成されている。In FIG. 2, reference numeral 1 denotes an insulating substrate on which conductors, resistors, etc. are formed by printing and firing.
２′は抵抗の保護を兼ねた半田レジストでガラス、樹脂
等により印刷乾燥あるいは焼成により形成される。2' is a solder resist which also serves to protect the resistor, and is formed of glass, resin, etc. by printing and drying or baking.
３は基板１上に形成された外部リード接続用の半田付導
体部、４は外部リード、６は半田レジスト２′の一部で
半田付導体部３，３′の間に形成される。Reference numeral 3 denotes a soldered conductor portion for connecting an external lead formed on the substrate 1, 4 an external lead, and 6 a part of a solder resist 2' formed between the soldered conductor portions 3 and 3'.
このような本考案の構成において、外部リード４を半田
付する場合を考えると半田レジスト６が半田付導体部３
の側面まで設けて隣接した半田付導体部３，３′を分離
しており、導体部３の周辺の半田レジストの形状が凹凸
状であるので半田槽にディップして半田付を行っても半
田レジストと基板との境界部の全面に微量の半田が付着
することがなくなり隣接導体部３，３′間をショートす
るということは全く生じなくなる。In such a configuration of the present invention, when considering the case where the external lead 4 is soldered, the solder resist 6 is attached to the soldered conductor portion 3.
Since the solder resist around the conductor part 3 has an uneven shape, even when soldering is performed by dipping it into a solder bath, the soldering resist is separated from the adjacent soldering conductor parts 3 and 3'. A trace amount of solder does not adhere to the entire surface of the boundary between the resist and the substrate, and short-circuiting between adjacent conductor parts 3 and 3' does not occur at all.
本考案は以上の説明の如く隣接した半田付導体部の間に
レジストを行なっているので半田付ショートを無くすこ
とが出来、混成集積回路装置の歩留りを向上させる効果
がある。As described above, in the present invention, since a resist is applied between adjacent soldered conductor parts, soldering short circuits can be eliminated, and the yield of hybrid integrated circuit devices can be improved.
第１図は従来の混成集積回路装置の一例を示す平面図、
第２図は本考案の混成集積回路装置の一実施例を示す平
面図である。
１・・・・・・絶縁基板、２，２′・・・・・・半田レ
ジスト、３・・・・・・半田付導体部、４・・・・・・
外部リード、５・・・・・・レジスト辺、６・・・・・
・半田レジスト。FIG. 1 is a plan view showing an example of a conventional hybrid integrated circuit device;
FIG. 2 is a plan view showing an embodiment of the hybrid integrated circuit device of the present invention. 1... Insulated board, 2, 2'... Solder resist, 3... Soldered conductor part, 4...
External lead, 5...Resist side, 6...
・Solder resist.
Claims (1)
おいて、隣接する外部リードの半田付導体部の間に半田
レジストを設けたことを特徴とする混成集積回路装置。1. A hybrid integrated circuit device formed by soldering external leads, characterized in that a solder resist is provided between soldered conductor portions of adjacent external leads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1976095047U JPS5810366Y2 (en) | 1976-07-19 | 1976-07-19 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1976095047U JPS5810366Y2 (en) | 1976-07-19 | 1976-07-19 | Hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5314148U JPS5314148U (en) | 1978-02-06 |
| JPS5810366Y2 true JPS5810366Y2 (en) | 1983-02-25 |
Family
ID=28705532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1976095047U Expired JPS5810366Y2 (en) | 1976-07-19 | 1976-07-19 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5810366Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS445818Y1 (en) * | 1966-09-13 | 1969-03-03 | ||
| JPS4978170A (en) * | 1972-12-06 | 1974-07-27 |
-
1976
- 1976-07-19 JP JP1976095047U patent/JPS5810366Y2/en not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS445818Y1 (en) * | 1966-09-13 | 1969-03-03 | ||
| JPS4978170A (en) * | 1972-12-06 | 1974-07-27 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5314148U (en) | 1978-02-06 |
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