JPS62136096A - Chip mounting substrate - Google Patents
Chip mounting substrateInfo
- Publication number
- JPS62136096A JPS62136096A JP27751585A JP27751585A JPS62136096A JP S62136096 A JPS62136096 A JP S62136096A JP 27751585 A JP27751585 A JP 27751585A JP 27751585 A JP27751585 A JP 27751585A JP S62136096 A JPS62136096 A JP S62136096A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- chip mounting
- electrodes
- mounting substrate
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（イ）発明の分野
この発明は、抵抗チップやコンデンサチップ等を基板上
の電極間に半田付けするチップ実装用基板に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of the Invention The present invention relates to a chip mounting board on which resistor chips, capacitor chips, etc. are soldered between electrodes on the board.
（ロ）発明の背沿
従来、この種のチップ実装用基板として第６図に示す構
造のものがあった。(b) Backstory of the Invention Conventionally, there has been a structure as shown in FIG. 6 as this type of chip mounting board.
この構造のものは、基板ａ上に２対の方形電極ｂ・・・
とリード線Ｃ・・・をプリント形成したもので、この電
極ｂ・・・上に第３図に示すようなデツプｄをリフロー
で実装する場合、実装機の実装のばらつきによってチッ
プｄの位置がずれた時、リフローの中で溶けたクリーム
半田の表面張力により第７図さらに第８図に示１ように
一方の電極側に引かれ、他方の電極とは導電しない状態
に固着される欠点があった。This structure has two pairs of rectangular electrodes b...
and lead wire C... are printed, and when mounting a depth d as shown in Figure 3 on this electrode b... by reflow, the position of the chip d may vary due to variations in the mounting of the mounting machine. When the electrode is misaligned, the surface tension of the cream solder melted during reflow causes it to be pulled toward one electrode as shown in Figure 7 and Figure 8, and it is fixed in a state where it is not conductive to the other electrode. there were.
このような実装もれがあった場合、抵抗や時定数用のコ
ンデンサなどの回路定数に関係する部品については、そ
の動作に関係するＩＣめ不良品は発見できたが、ノイズ
吸収用コンデンサや回路定数に関係しないものの場合は
、発見できない問題点があった。If there was such a packaging omission, we could find defective ICs related to the operation of components related to circuit constants such as resistors and time constant capacitors, but we could find defective ICs related to the operation of the components, such as resistors and time constant capacitors. In the case of items not related to constants, there were problems that could not be discovered.
（ハ）発明の目的
この発明は、チップ部品がずれて実装された場合におい
て、半田の影響も少なく、両方の電極と確実に導通する
ことのできるチップ実装用基板の提供を目的とする。(C) Purpose of the Invention The object of the present invention is to provide a chip mounting board that is less affected by solder and can be reliably electrically connected to both electrodes when a chip component is mounted out of alignment.
（ニ）発明の要約 この発明は、基板上にプリント形成されるｍ ４Ｅ。(d) Summary of the invention This invention is an m4E which is printed on a substrate.
間の対向間隔を傾斜状に形成したチップ実装基板である
ことを特徴とする。The chip mounting board is characterized in that the facing interval between the two sides is formed in an inclined shape.
（ホ）発明の効果
この発明によれば、基板上にプリント形成されるＦｚ
［ｉ間の対向間隔（スリン１へ）を傾斜状に形成したの
で、チップ部品がずれて実装された場合でも接触率が高
くなり、しかも半田の影響も少なく、両方の電極に確実
に導通することがでさ、さらに実装もれも確実に発見す
ることができる。(e) Effect of the invention According to this invention, the Fz printed on the substrate
[Since the facing interval between i (towards Surin 1) is formed in an inclined manner, even if the chip components are mounted out of alignment, the contact rate is high, and the influence of solder is also small, ensuring continuity between both electrodes. In addition, it is possible to reliably discover implementation omissions.
くべ）発明の実施例 この発明の一実施例を、以下図面に基づいて訂述する。Kube) Examples of the invention An embodiment of the present invention will be described below based on the drawings.
図面はチップ実装用基板を示し、第１図において、この
基板１は、基板１上に２対の電極２ａ。The drawing shows a substrate for chip mounting, and in FIG. 1, this substrate 1 has two pairs of electrodes 2a on the substrate 1.
２ｂ、２ａ、２ｂとその各リード線３をプリント形成し
ている。2b, 2a, 2b and their respective lead wires 3 are printed.
上述の８対の電極２ａ、２ｂは直角三角形状に形成され
、その斜辺２Ｇ、２Ｃを間隔を置いて対向させている。The eight pairs of electrodes 2a and 2b described above are formed in the shape of a right triangle, with their hypotenuses 2G and 2C facing each other with an interval between them.
すなわち、各斜辺２Ｃ，２Ｃ間は傾斜状のスリット４が
形成された状態となっている。That is, an inclined slit 4 is formed between each oblique side 2C, 2C.
そうして、上述の各電ｉｆ；２ａ、２ｂ、２ａ、２ｂ上
に、第３図に示づような４極チツプ５の４隅の電極５ａ
、６ｂ、６ａ、６ｂを載量して半田付すするのである。Then, on each of the above-mentioned electrodes 2a, 2b, 2a, 2b, electrodes 5a at the four corners of the quadrupole chip 5 as shown in FIG.
, 6b, 6a, and 6b are loaded and soldered.
この半田付（プは通常リフローで実装するが、この場合
実装機の実装位置のばらつきにＪ：ってチップ５の位［
ｄがずれることがある。This soldering (P) is usually mounted by reflow, but in this case J: is the place of chip 5 due to variations in the mounting position of the mounting machine.
d may shift.
この位置ずれ時に、リフローの中で溶けたクリーム半田
の表面張力によりチップ５の位置がさらにずらされる場
合があるが、上述のように電極２ａ、２ｂ間を傾斜状の
間隔を有するように、図では電極を三角形状にしている
ので、表面張力による引張りが弱くなり、しかもチップ
５がずれても電極間の接触率が高いので、第２図に示す
ように両方の電極２ａ、２ｂに確実に導通するのである
。At the time of this positional shift, the position of the chip 5 may be further shifted due to the surface tension of the cream solder melted during reflow. Since the electrodes are triangular in shape, the tension caused by surface tension is weaker, and even if the tip 5 is misaligned, the contact rate between the electrodes is high, so as shown in FIG. It is conductive.
さらに、チップ５の電極６ｂが基板１、電極２ｂと完全
に位置ずれをする時はデツプ５の移動量が大となるので
、実装もれを視覚により容易に発見することができる。Further, when the electrode 6b of the chip 5 is completely misaligned with the substrate 1 and the electrode 2b, the amount of movement of the depth 5 becomes large, so that mounting leakage can be easily detected visually.
上述の実施例は、第３図に示す４極チツプについて述べ
たが、第４図に示す２極デツプ５′の場合は、第５図に
示す基板１′を用いるものであり、その他の点は、前例
（第１〜第３図参照）と同様なので、相当部分に同一符
号を付して省略する。In the above embodiment, the four-pole chip shown in FIG. 3 was described, but in the case of the two-pole deep chip 5' shown in FIG. 4, the substrate 1' shown in FIG. 5 is used, and other points are Since this is the same as the previous example (see FIGS. 1 to 3), corresponding parts are given the same reference numerals and omitted.
図面は、この発明の一実施例を示し、
第１図はチップ実装用基板の要部の平面図、第２図は同
説明のための平面図、
第３図は４極チツプの斜視図、
第４図は２極チツプの斜視図、
第５図は他の実施例を示す平面図、
第６図乃至第８図は従来例を示す平面図である。
１・・・基 板 ２ａ、 ２ｂ
・・・電 極４・・・斜め方向のスリットThe drawings show an embodiment of the present invention, FIG. 1 is a plan view of the main parts of a chip mounting board, FIG. 2 is a plan view for explaining the same, FIG. 3 is a perspective view of a 4-pole chip, FIG. 4 is a perspective view of a bipolar chip, FIG. 5 is a plan view showing another embodiment, and FIGS. 6 to 8 are plan views showing a conventional example. 1... Board 2a, 2b
...Electrode 4...Diagonal slit
Claims (1)
斜状に形成したチップ実装用基板。1. A chip mounting board in which the facing distance between electrodes printed on the board is formed in an inclined manner.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27751585A JPS62136096A (en) | 1985-12-09 | 1985-12-09 | Chip mounting substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27751585A JPS62136096A (en) | 1985-12-09 | 1985-12-09 | Chip mounting substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62136096A true JPS62136096A (en) | 1987-06-19 |
Family
ID=17584672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27751585A Pending JPS62136096A (en) | 1985-12-09 | 1985-12-09 | Chip mounting substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62136096A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006104032A1 (en) * | 2005-03-29 | 2006-10-05 | Murata Manufacturing Co., Ltd. | Electronic part mounting structure |
| JP2015037182A (en) * | 2013-08-14 | 2015-02-23 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Mounting board for multilayer ceramic capacitor |
-
1985
- 1985-12-09 JP JP27751585A patent/JPS62136096A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006104032A1 (en) * | 2005-03-29 | 2006-10-05 | Murata Manufacturing Co., Ltd. | Electronic part mounting structure |
| JPWO2006104032A1 (en) * | 2005-03-29 | 2008-09-04 | 株式会社村田製作所 | Electronic component mounting structure |
| JP4618298B2 (en) * | 2005-03-29 | 2011-01-26 | 株式会社村田製作所 | Electronic component mounting structure |
| US8039758B2 (en) | 2005-03-29 | 2011-10-18 | Murata Manufacturing Co., Ltd. | Mounting structure for electronic component |
| JP2015037182A (en) * | 2013-08-14 | 2015-02-23 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Mounting board for multilayer ceramic capacitor |
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