JPS59178536A - System for judging zero value of plural data - Google Patents

System for judging zero value of plural data

Info

Publication number
JPS59178536A
JPS59178536A JP58054581A JP5458183A JPS59178536A JP S59178536 A JPS59178536 A JP S59178536A JP 58054581 A JP58054581 A JP 58054581A JP 5458183 A JP5458183 A JP 5458183A JP S59178536 A JPS59178536 A JP S59178536A
Authority
JP
Japan
Prior art keywords
zero value
data
zero
carry
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58054581A
Other languages
Japanese (ja)
Inventor
Hisajiro Sagara
相良　久次郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58054581A priority Critical patent/JPS59178536A/en
Publication of JPS59178536A publication Critical patent/JPS59178536A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To judge the zero value of plural data in a short time with less quantity of hardware, by judging that, when calculated results of plural data are zero value and no carry is detected, all the plural data are zero value. CONSTITUTION:When all data A-C set in registers 15-17 are zero value, the adding result of a logical adder 10 is zero value and ''1'' is outputted from a zero-value detecting circuit 11. Since no carry is generated in the process of addition of the adder 10, a carry detecting circuit 12 outputs ''0'' and an inverter 13 outputs ''1''. Therefore, when all the data A-C are zero value, ''1'' is outputted from an AND gate 14. Moreover, when any one of the data A-C is not zero value, the output of the adder 10 does not become zero and ''0'' is outputted from the detecting circuit 11. When carry is generated and ''1'' is outputted from the detecting circuit 12 and ''0'' is outputted from the inverter 13 even though a calculated result is zero value, the gate 14 outputs ''0''. Therefore, when ''0'' is outputted from the gate 14, at least one of the data A-C is not zero value.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は複数のデータがいずれも零値であるということ
を検出する零値判定方式に係り、特にこの複数のデータ
を１つずつ零であるかどうかを検出せずに少なくとも２
つのデータを加算してその加算結果を判定することによ
り、短時間に複数のデータがすべて零値であることを検
出するようにしたものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a zero value determination method for detecting that a plurality of data are all zero values, and particularly relates to a zero value determination method for detecting that each of the plurality of data is zero. at least 2 without detecting whether
By adding two pieces of data and determining the result of the addition, it is possible to detect in a short time that all the pieces of data are zero values.

〔従来技術と問題点〕[Conventional technology and problems]

データ処理装置ではデータ処理効率を上げるだめにデー
タが零判定回路等により零値であるかどうかを判定して
いる。ところでデータによってはデータ長が長くなり２
例えば２ワード長のデータの場合には、第１図に示す如
く、初め■により倍ワードのデータの半分をレジスタ２
を経由して加算器３をスルーさせて零判定回路４に導き
零値か否かを判定し９次に■により残りのデータをこれ
またレジスタ２を経由して加算器６をスルーさせ零イ１
μか否かを判定させていた。勿論レジスタ２に零判定回
路を接続することもある。In order to improve data processing efficiency, a data processing device uses a zero determination circuit or the like to determine whether or not data has a zero value. By the way, depending on the data, the data length may be long2.
For example, in the case of data with a length of 2 words, as shown in Figure 1, half of the double word data is transferred to the register 2 as shown in Figure 1.
The remaining data is passed through the adder 6 via the register 2 and passed through the adder 6 to be passed through the adder 6 to determine whether it is a zero value or not. 1
It was determined whether it was μ or not. Of course, a zero determination circuit may be connected to the register 2.

複数データがすべて零値か否かを判定するだめの他の例
として、第２図に示す如く、自系のプロセッサ５に他系
の装置６，７．８等が接続され。As another example of determining whether or not a plurality of data are all zero values, as shown in FIG. 2, devices 6, 7, 8, etc. of other systems are connected to the processor 5 of the own system.

プロセッサ５が他系の装Ｗ６　、７　、８に対しコマン
ドを送出し、これに対して他系の装置６．７゜８が正常
に動作しているとき、システムによっては、オール「０
」、つまり零値のレスポンスを送出する。７′ロセツサ
５はこのレスポンス状態をみて装置６，７．Ｂが正常に
動作しているか否か判断するために、これらのレスポン
スが零値か否かをチェックすることが必要となる。When the processor 5 sends a command to the devices W6, 7, and 8 of other systems, and the devices 6,7, and 8 of the other systems are operating normally, depending on the system, all "0" is sent.
'', that is, a zero-value response is sent. 7' The processor 5 sees this response state and sends the devices 6, 7 . In order to determine whether B is operating normally, it is necessary to check whether these responses are zero values.

従来、複数めデータ（倍ワード・データも含む）がすべ
て零値か否かを判定する手段としては、（１）１個の零
値検出回路に順次データを入力して零値か否かを判定す
る直列型方式と、ｔ２１ｉ数個の零値検出回路を設けて
おき、各零値検出回路に同時にデータを入力して零値か
否かを判定する並列型方式との２ｆ！Ｊ類がある。Conventionally, methods for determining whether or not all of the plurality of data (including double word data) are zero values include (1) sequentially inputting the data to one zero value detection circuit and determining whether or not the data are zero values; 2f! of a serial type method that makes a determination and a parallel type method that provides several zero value detection circuits and simultaneously inputs data to each zero value detection circuit to determine whether or not it is a zero value! There is class J.

しかし、上記（１）は複数回の判定処理制御を必要とす
るため全判定処理時間が長くなるという欠点を有し、ま
た上記（２）は複数個の零値検出回路を必要とするため
、ハードｔが多くなるという欠点が存在する。However, the above (1) has the disadvantage that the total judgment processing time becomes long because it requires judgment processing control multiple times, and the above (2) requires a plurality of zero value detection circuits. There is a drawback that the number of hard t increases.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記各欠点を改善するために判定時間
が短かくしかもハード弼・をあまり多くする必要のない
複数データの零値判定方式を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for determining zero values of multiple data, which requires a short determination time and does not require a large amount of hardware, in order to improve the above-mentioned drawbacks.

〔発明の構成〕[Structure of the invention]

この目的を達成するために本発明の複数データの零値判
定方式では、複数のデータがすべて零値か否かを判定す
る零値判定装置において、データを加算する論理加算手
段と、該論理加算手段の演算結果が零値であることを判
定する零値判定手段と、上記加算過程におけるキャリイ
を検出するキャリイ検出手段を設け、演算結果が零値で
しかもキャリイが検出されないときに複数のデータをす
べて零値であると判定することを特徴とする。In order to achieve this object, in the zero value determination method for multiple data of the present invention, in a zero value determination device that determines whether or not all of the multiple data are zero values, a logical addition means for adding data, and a logical addition means for adding data; A zero value determination means for determining whether the calculation result of the means is a zero value and a carry detection means for detecting a carry in the addition process are provided, and when the calculation result is a zero value and no carry is detected, a plurality of data is It is characterized by determining that all values are zero.

〔発明の実施例〕[Embodiments of the invention]

本発明の一実施例を第６図により説明する。 An embodiment of the present invention will be explained with reference to FIG.

図中、１０は論理加算器、１１は零値検出回路であって
論理加算器１０の演算出力結果が零値であることを検出
するもの、１２はキャリイ検出回路であシデータＡ、Ｂ
、Ｃの加算過程においてキヤリイが発生したときこれを
検出するもの、１３はインバータでキャリイ検出回路１
２からキャリイ検出にもとづき「１」が出力されたとき
にこのインバータ１５は「０」を出力しキャリイ検出回
路１２がキャリイを検出せずに「０」を出力していると
きインバータ１３より「１」が出力されることになる。In the figure, 10 is a logic adder, 11 is a zero value detection circuit that detects that the calculation output result of the logic adder 10 is a zero value, and 12 is a carry detection circuit for data A, B.
, a carry detection circuit 1 which detects when a carry occurs in the addition process of C; 13 is an inverter;
When the inverter 15 outputs "1" based on the carry detection from the inverter 12, the inverter 15 outputs "0", and when the carry detection circuit 12 does not detect a carry and outputs "0", the inverter 13 outputs "1". ' will be output.

アンド中ゲート１４はキャリイ検出回路１２がキャリイ
を検出しないときのインノ（−夕１４からの出力「１」
と、零値検出回路１１が零１１＾９を検出したときの出
力「１」により「１」を出力するものである。The AND middle gate 14 is an output "1" from the IN (-) gate 14 when the carry detection circuit 12 does not detect a carry.
When the zero value detection circuit 11 detects zero 11^9, it outputs "1".

１５〜１７はデータＡ〜Ｃがセットされるレジスタであ
り、これらのデータＡ−Ｃが論理加算器１０により絶対
値加算されるものである。そして１８は論理加′ｎ、器
１０による演算結果がセットされるレジスタである。15 to 17 are registers in which data A to C are set, and the absolute values of these data A to C are added by the logical adder 10. 18 is a register in which the result of the operation by the logic adder 10 is set.

したがって、レジスタ１５〜１７にセットされたデータ
Ａ〜Ｃがすべて零値の場合には、論理加算器１０の加算
結果は勿論、零値であるので零値検出回路１１から「１
」が出力される。そして論理加算器１０での加算過程に
おいてキャリイは発生されないのでキャリイ検出回路１
２は「０」を出力し。Therefore, when the data A to C set in the registers 15 to 17 are all zero values, the addition result of the logical adder 10 is of course a zero value, so the zero value detection circuit 11 outputs "1".
" is output. Since no carry is generated during the addition process in the logic adder 10, the carry detection circuit 1
2 outputs "0".

インバータ１３は「１」を出力している。それ故。Inverter 13 is outputting "1". Therefore.

データＡ〜Ｃがすべて零値の場合にはアンド◆ゲート１
４より「１」が出力されることになる。If data A to C are all zero values, AND◆gate 1
4 will output "1".

しかるにデータＡ−Ｃのいずれかが零値でない場合には
、論理加算器１０の加算出力が零にならず零値検出回路
１１から「０」が出力されるか、論理加算器１０の演算
結果は零値であっても演算過程ではキャリイが発生して
キャリイ検出回路１２カラ１１」が出力されインノく一
夕１３か「０」を出力するかになり、アンド・ゲート１
４は「０．１を出力することになる。However, if any of the data A-C is not a zero value, either the addition output of the logic adder 10 does not become zero and "0" is output from the zero value detection circuit 11, or the calculation result of the logic adder 10 Even if is a zero value, a carry occurs during the calculation process, and the carry detection circuit 12 outputs ``color 11'', which instantly outputs either 13 or ``0'', and the AND gate 1
4 will output 0.1.

それ故、アンド・ゲート１４より零が出力されたときは
データＡ〜Ｃの少くとも１つは零値でないことが表示さ
れる。Therefore, when the AND gate 14 outputs zero, it is displayed that at least one of the data A to C is not a zero value.

このようにしてアンド・ゲート１４から「１」が出力さ
れたときデータＡ〜Ｃはすべて零値であり。In this way, when "1" is output from the AND gate 14, data A to C are all zero values.

アンド・ゲート１４から「０」が出力されたときデータ
に、Ｃの少くとも１つは非零値であることがわかる。When "0" is output from the AND gate 14, it can be seen that at least one of the C values is a non-zero value.

このようにして本発明では、複数の零値を論理加算した
場合、加算結果もやはり零値でかつキャリイがなく、非
零値を含む複数データを論理加算した場合、加算結果が
非零値となるかキャリイがあるという論理加算器の特徴
に看目し、１個の論理加ｑ、器に入力可能なデータ数ま
での複数データの即時の零値判定を可能にする。In this way, in the present invention, when a plurality of zero values are logically added, the addition result is also a zero value and there is no carry, and when a plurality of data including non-zero values are logically added, the addition result is a non-zero value. Considering the feature of a logical adder that there is a carry or a carry, it is possible to immediately determine the zero value of a plurality of data up to the number of data that can be input to a single logical adder.

勿論加算器としてアドレス計算や論理加算を行うことが
できる汎用加算器（最小２人力）によっても実現できる
。更に加算器の入力数を６．４・・・と増加すればそれ
だけ零値判定効率を向上させることができる。Of course, it can also be realized by a general-purpose adder (minimum 2-manpower) that can perform address calculation and logical addition. Furthermore, if the number of inputs to the adder is increased to 6.4, etc., the zero value determination efficiency can be improved accordingly.

〔発明の効果〕〔Effect of the invention〕

本発明によれば１％別な加算器を使用することなく７通
常のデータ処理装置が保持している論理加算器（汎用加
算器を論理加算させる場合も含む）を用いて、ハード量
をあまり大きくすることなく。According to the present invention, the amount of hardware can be reduced by using the logic adder (including the case where a general-purpose adder is used for logic addition) that is held in 7 normal data processing devices without using a separate adder. without making it bigger.

複数データをきわめて短時間にそれらが零値であるかど
うかを判定することが可能となる。It becomes possible to determine whether a plurality of pieces of data have a zero value in a very short time.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の零値判定方法説明図、第２図は自系と他
系のコマンド応答説明図、第３図は本発明の一実施例構
成図である。 図中、１０は論理加算器、１１は零値検出回路。 １２はキャリイ検出回路、１３はインバータ。 １４はアンド・ゲート、１５〜１８はレジスタを示す。 特許出願人　富士通株式会社 代理人弁理士　山　谷　晧　榮FIG. 1 is an explanatory diagram of a conventional zero value determination method, FIG. 2 is an explanatory diagram of command responses of the own system and other systems, and FIG. 3 is a configuration diagram of an embodiment of the present invention. In the figure, 10 is a logic adder, and 11 is a zero value detection circuit. 12 is a carry detection circuit, and 13 is an inverter. 14 is an AND gate, and 15 to 18 are registers. Patent applicant Fujitsu Ltd. Representative Patent Attorney Akira Yamatani

Claims (1)

【特許請求の範囲】[Claims] 複数のデータがすべて零値か否かを判定する零値判定装
置において、データを加算する論理加算手段と、該論理
加算手段の演ｐ結果が零値でろることを判定する零値判
定手段と、上記加算過程におけるキャリイを検出するキ
ャリイ検出手段を設け、演算結果が零値でしかもキャリ
イが検出されないときに複数のデータをすべて零値であ
ると判定することを特徴とする複数データの零値判定方
式。A zero value determination device that determines whether all of a plurality of data are zero values, comprising: logical addition means for adding data; and zero value determination means for determining whether the result of an operation of the logical addition means is a zero value. , a carry detection means for detecting a carry in the addition process, and when the calculation result is a zero value and no carry is detected, the plurality of data are all determined to be zero values. Judgment method.
JP58054581A 1983-03-30 1983-03-30 System for judging zero value of plural data Pending JPS59178536A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58054581A JPS59178536A (en) 1983-03-30 1983-03-30 System for judging zero value of plural data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58054581A JPS59178536A (en) 1983-03-30 1983-03-30 System for judging zero value of plural data

Publications (1)

Publication Number Publication Date
JPS59178536A true JPS59178536A (en) 1984-10-09

Family

ID=12974662

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58054581A Pending JPS59178536A (en) 1983-03-30 1983-03-30 System for judging zero value of plural data

Country Status (1)

Country Link
JP (1) JPS59178536A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0287217U (en) * 1988-12-26 1990-07-10

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0287217U (en) * 1988-12-26 1990-07-10
JPH0511534Y2 (en) * 1988-12-26 1993-03-23

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