JP2929975B2 - Fault Diagnosis Method for Bus Interface Circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface circuit fault diagnosis method, and more particularly to a bus interface circuit fault diagnosis method suitable for diagnosing a bus interface circuit fault mounted in a semiconductor integrated circuit device. About.

[0002]

2. Description of the Related Art Conventionally, when a bus interface circuit is constituted by an 8-bit circuit, one semiconductor integrated circuit 50 is provided with bidirectional buffers 51 to 58 and the other semiconductor integrated circuit 60 as shown in FIG. Bidirectional buffer 61
To 68, and the bidirectional buffers 51 to 58 are connected to the bidirectional buffers 61 to 6 via data buses 71 to 78, respectively.
8 is adopted.

When diagnosing a fault in the bus interface circuit, a test data sending circuit 80 is provided in the semiconductor integrated circuit 50, a fault detecting circuit 81 is provided in the other semiconductor integrated circuit 60, and the test data sending circuit 80 and the fault detecting The circuit 81 is connected via a failure notification signal line 82.

Next, a method of diagnosing a bus fault in the bus interface circuit will be described. First, test data is input from the test data transmission circuit 80 to the inside of the bidirectional buffers 51 to 58, and the test data is transmitted to the bidirectional buffers 61 to 68 via the bidirectional buffers 51 to 58 and the data buses 71 to 78. Transmit. As a test on test data output from the bidirectional buffers 61 to 68, a parity check or the like is performed by the failure detection circuit 81. If there is an error in the data, the failure notification signal line 8
2, the contents of the fault are transmitted to the test data transmission circuit 80.

[0005] Further, as described in Japanese Patent Application Laid-Open No. 2-41540, data is transmitted from a receiving side to a transmitting side.
A method for holding a data at a transmitting side, inverting the held data, transmitting the inverted data to a receiving side, and determining whether a failure has occurred based on whether or not the receiving side has received the inverted data. Has been proposed.

[0006]

However, in the conventional fault diagnosis method, it is possible to determine whether the test data transmitted from the transmission side has been correctly received by the reception side.
When a failure occurs, it is difficult to specify where the failure has occurred.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a bus interface circuit fault diagnosis method which can determine the location of a fault using test data when a fault occurs in the bus interface circuit.

[0008]

According to the first aspect of the present invention, (a) when a data bus connecting one bidirectional buffer and the other bidirectional buffer is abnormal, a test is performed inside the one bidirectional buffer. (B) comparing the test data with the test data output from the data bus side of one bidirectional buffer, and (c) further comparing the test data with the other bidirectional buffer at a timing different from the test data generation timing. Input test data into the buffer, and (d)
This test data is compared with the test data output from the data bus side of the other bidirectional buffer, (e) each comparison result is determined, and (f) all these comparison results are normal.
In some cases, the data bus is diagnosed as disconnected and the ratio
If all the comparison results are abnormal, it is diagnosed that the data bus is short-circuited.
The failure diagnosis method of the bus interface circuit to be disconnected is adopted.

In other words, according to the first aspect of the present invention, when an abnormality occurs in the data bus, test data is input to the inside of one of the two-way buffers and the other of the two-way buffers at different timings. comparing the test data of the internal side test data and the data bus side of the buffer, to determine the result of the comparison, the determination result is all positive
If normal, diagnose that the data bus is disconnected and
Diagnose data bus short if all results are abnormal
It is characterized in that.

[0010]

[0011]

[0012]

[0013]

[0014]

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 is an overall configuration diagram of a bus interface circuit according to an embodiment of the present invention. In FIG. 1, 8
The bus interface circuit composed of bits includes bidirectional buffers 11 to 18 mounted on the semiconductor integrated circuit 10,
Bidirectional buffers 21 to 21 mounted on semiconductor integrated circuit 20
28, and each bidirectional 11 to 18 is connected to the data bus 3
They are connected to bidirectional buffers 21 to 28 via 1 to 38, respectively. Further, the semiconductor integrated circuit 10 is provided with a direction control circuit 40 and a failure detection circuit 41, and the semiconductor integrated circuit 20 is provided with a direction control circuit 42 and a failure detection circuit 4.
4 are provided. The direction control circuit 40 controls the directionality of the bidirectional buffers 11 to 18, and the direction control circuit 42 controls the directionality of the bidirectional buffers 21 to 28.

The failure detection circuit 41 includes two-way buffers 11 to
The test data is transmitted to the internal side of the bidirectional buffers 11 to 18 or to the data bus side, the contents of the transmitted data are compared, and the comparison result is determined. The failure location is diagnosed from the result of this determination. The fault detection circuit 44 is connected to the inside of the bidirectional bachs 21 to 28 and to the data bus side, sends test data to the inside or the data bus side, and compares the sent data with the received data. , A comparison result is determined, and a failure point is diagnosed from the determination result. Further, the failure detection circuit 41 and the failure detection circuit 44 are connected via a failure notification signal line 45, and when data is not transmitted from one bidirectional buffer to the other bidirectional buffer via the data buses 31 to 38. The fact that an abnormality has occurred in the data buses 31 to 38 is transmitted via the fault notification signal line 45.

Next, a method for diagnosing a fault in the bus interface circuit shown in FIG. 1 will be described.

Here, an example will be described in which accurate data is not transmitted via the data buses 31 to 38 when a failure occurs in the data buses 31 to 38, for example. That is, when the data buses 31 to 38 are abnormal, the failure detection circuit 41 sends test data to the internal sides of the bidirectional buffers 11 to 18 and transmits the test data output from the data buses of the bidirectional buffers 11 to 18. The input and transmitted data is compared with the input data.

Next, the test data is transmitted from the failure detection circuit 44 to the inside of the bidirectional buffers 21 to 28 at a timing different from the timing at which the test data is transmitted from the failure detection circuit 41, and the bidirectional buffers 21 to 28 are transmitted. The test data output from the data bus side of is input. Then, the transmitted data is compared with the input data. Then, the failure detection circuits 41 and 44 determine the comparison result, respectively, and transmit one determination result to the other signal detection circuit via the failure notification signal line 45, and diagnose a failure location from each determination result. At this time, if the determination results of the failure detection circuits 41 and 44 are all normal, it can be diagnosed that the data buses 31 to 38 are disconnected. Fault detection circuit 4
When all the comparison results of Nos. 1 and 44 become abnormal, it can be diagnosed that the data buses 31 to 38 are short-circuited.

On the other hand, when the data buses 31 to 38 are normal,
Bidirectional buffers 11-18 and bidirectional buffers 21-28
When data cannot be exchanged accurately between the bidirectional buffers 11 to 18 and 21 to 21 in the same manner as described above.
Test data is input to each of the test data, and data determination is performed based on the input test data. When the results of the determination by the failure detection circuits 41 and 44 are determined to be abnormal, it can be diagnosed that the two-way buffer has been determined to have failed.

When the data buses 31 to 38 are normal, the test data is transmitted from the data buses of the bidirectional buffers 11 to 18 and 21 to 28 to the internal side at different timings from the failure detection circuits 41 and 44, respectively. Is compared with the test data transmitted to the internal side, each comparison result is determined, and when any of the determination results becomes abnormal,
It can be diagnosed that there is a failure inside the bidirectional buffer determined to be abnormal.

[0023]

As described above, according to the first aspect of the present invention, when an abnormality occurs in the data bus, the test is performed with the timing shifted to the internal side of one bidirectional buffer and the internal side of the other bidirectional buffer. enter the data, compared with the test data of the internal side test data and the data bus side of each bidirectional buffers, to determine the result of the comparison, the
If all judgment results are normal, disconnect the data bus
Is diagnosed, and when all the judgment results are abnormal,
Since it is determined that the bus is short-circuited, it is possible to diagnose a faulty portion of the interface circuit when the data bus is abnormal.

[0024]

[0025]

[0026]

[0027]

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a bus interface circuit according to an embodiment of the present invention.

FIG. 2 is an overall configuration diagram of a conventional bus interface circuit.

[Explanation of symbols]

 10, 20 Semiconductor integrated circuit 11 to 18, 21 to 28 Bidirectional buffer 31 to 38 Data bus 40, 42 Direction control circuit 41, 44 Fault detection circuit

Claims (1)

(57) [Claims] When an error occurs in a data bus connecting one of the two-way buffers to another one of the two-way buffers, test data is input to the inside of the one-way buffer, and the test data is input to the one-way buffer. Comparing the test data output from the data bus side of the buffer with the test data and inputting the test data to the internal side of the other bidirectional buffer at a timing different from the test data generation timing; The test data output from the data bus side of the bidirectional buffer is compared with each other, and the respective comparison results are determined. When all the comparison results are normal, the data
Diagnosis of disconnection of tabus, all of these comparison results are abnormal
A method for diagnosing a fault in a bus interface circuit, comprising diagnosing a short circuit of the data bus at some time .