JPS63274873A - Oscillation detection circuit - Google Patents

Oscillation detection circuit

Info

Publication number
JPS63274873A
JPS63274873A JP62111250A JP11125087A JPS63274873A JP S63274873 A JPS63274873 A JP S63274873A JP 62111250 A JP62111250 A JP 62111250A JP 11125087 A JP11125087 A JP 11125087A JP S63274873 A JPS63274873 A JP S63274873A
Authority
JP
Japan
Prior art keywords
circuit
oscillation
output
potential
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62111250A
Other languages
Japanese (ja)
Inventor
Kuniyuki Goto
後藤 邦之
Hisashi Mori
森 久司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP62111250A priority Critical patent/JPS63274873A/en
Publication of JPS63274873A publication Critical patent/JPS63274873A/en
Pending legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To obtain easy circuit constitution by deciding whether or not the integral value of the oscillation output of an oscillation circuit is within a reference voltage range, and inputting the decision result to a storage circuit. CONSTITUTION:The oscillation output 101 of the oscillation circuit 1 is passed through the parallel circuit of the series circuit of an inverter 2 and a resistance 3, and a capacitor 4 to become an integral signal 104, which is inputted to the inversion input terminal of a comparator 5 and an input terminal of a comparator 6. A reference potential 102 is supplied to the input terminal of the comparator 5 and a reference potential 103 is supplied to the inversion input terminal of the comparator 6. Here, when the output 101 is not outputted by the circuit 1, a fixed potential is supplied to the inverter 2 and its output is fixed at an H or L potential. The input potentials of the comparators 5 and 6 are not within the level ranges of the potentials 102 and 103 and one of the comparators 5 and 6 outputs an L potential. Consequently, the output 105 of an AND circuit 7 is an L potential, which is inputted to an FF circuit 8 together with a decision input signal 106; and a decision signal indicating that there is no oscillation output is outputted as an L potential through a terminal 54, so that the oscillation is detected.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は発振検知回路に関し、特に発振回路の発振の有
無を検知する発振検知回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an oscillation detection circuit, and more particularly to an oscillation detection circuit that detects the presence or absence of oscillation in an oscillation circuit.

〔従来の技術〕[Conventional technology]

一般に、発振回路は電子装置におけるクロック発生源と
して広く利用されているが、その動作が正常であるか否
かを任意に監視することができるようにすることは極め
て重要事である。このために発振回路の動作の正常の有
無を検知し、異常事には特定信号を出力する方法がとら
れている。
In general, oscillation circuits are widely used as clock generation sources in electronic devices, but it is extremely important to be able to arbitrarily monitor whether or not their operation is normal. For this purpose, a method is used to detect whether or not the operation of the oscillation circuit is normal, and to output a specific signal in the event of an abnormality.

従来、この種の発振検知回路においては、第3図にその
一例が示されるように、発振回路9に対応して、周波数
カウンタ10およびマイクロコンピュータ11が備えら
れている。第3図において、発振回路9の発振出力は周
波数カウンタ10に入力されて、その周波数が測定され
る0周波数カウンタによる周波数測定データはマイクロ
コンピュータ11においてあらかじめ設定されている周
波数値と比較照合されて、発振回路9が正常に動作して
いるか否かが検知される。この検知による判定信号は、
端子55を介して出力される。
Conventionally, in this type of oscillation detection circuit, a frequency counter 10 and a microcomputer 11 are provided in correspondence with the oscillation circuit 9, as an example of which is shown in FIG. In FIG. 3, the oscillation output of the oscillation circuit 9 is input to the frequency counter 10, and the frequency measurement data by the 0 frequency counter, which measures the frequency, is compared and verified with a preset frequency value in the microcomputer 11. , it is detected whether the oscillation circuit 9 is operating normally. The judgment signal from this detection is
It is output via terminal 55.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の発振検知回路は、発振回路の発振出力を
周波数・カウンタに入力し、周波数カウンタにより測定
された周波数測定データをマイクロコンピュータに転送
して、マイクロコンピュータにより前記発振回路の動作
の正常の有無を検知している、従って、周波数カウンタ
およびマイクロコンピュータ等の高価な装置類を必要と
するという欠点がある。
The above-mentioned conventional oscillation detection circuit inputs the oscillation output of the oscillation circuit to a frequency counter, transfers the frequency measurement data measured by the frequency counter to a microcomputer, and uses the microcomputer to determine whether the oscillation circuit is operating normally. The drawback is that it requires expensive equipment such as a frequency counter and a microcomputer to detect the presence or absence.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の発振検知回路は、発振回路の発振出力を積分す
る積分回路と、前記積分回路の出力が二つの基準電圧範
囲内にあることを判定する判定回路と、前記判定回路の
判定結果を記憶する回路と、を備えて構成される。
The oscillation detection circuit of the present invention includes an integration circuit that integrates the oscillation output of the oscillation circuit, a determination circuit that determines whether the output of the integration circuit is within two reference voltage ranges, and a memory that stores the determination results of the determination circuit. and a circuit to do so.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の要部を示す回路図である。FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention.

第1図に示されるように、本実施例は、発振回路1に対
応してインバータ2と、抵抗3と、コンデンサ4と、コ
ンパレータ5および6と、AND回路7と、フリップフ
ロップ回路8と、を備えている。
As shown in FIG. 1, this embodiment includes an inverter 2, a resistor 3, a capacitor 4, comparators 5 and 6, an AND circuit 7, a flip-flop circuit 8, corresponding to an oscillation circuit 1. It is equipped with

第1図において、発振回路1の発振出力101は、イン
バータ2と抵抗3の直列回路とコンデンサ4どの並列回
路を経由して積分信号104として出力され、コンパレ
ータ5の反転入力端子とコンパレータ6の入力端子に入
力される。一方、コンパレータ5の入力端子には端子5
1から基準電位102が供給され、コンパレータ6の反
転入力端子には端子52から基準電位103が供給され
ている。
In FIG. 1, an oscillation output 101 of an oscillation circuit 1 is output as an integral signal 104 via a series circuit of an inverter 2 and a resistor 3, and a parallel circuit of a capacitor 4, and is output as an integral signal 104 between an inverting input terminal of a comparator 5 and an input of a comparator 6. input to the terminal. On the other hand, the input terminal of comparator 5 is terminal 5.
A reference potential 102 is supplied from the terminal 1, and a reference potential 103 is supplied from the terminal 52 to the inverting input terminal of the comparator 6.

発振回路1が正常に発振しており、上述のように発振回
路出力101が出力されている時には、コンパレータ5
の反転入力端子とコンパレータ6の入力端子に入力され
る積分信号104は、第2図(b)に示されるように、
基準電位102(High電位)と基準電位1103(
Lo電位)のレベル範囲内にあるため、コンパレータ5
および6からは共にHigh電位が出力される。コンパ
レータ5および6の出力はAND回路7に入力されるが
、上述のように、発振回路1から発振出力1が出力され
ている時には、AND回路7の出力105としては第2
図(C)に示されるようにHigh電位が出力される。
When the oscillation circuit 1 is oscillating normally and the oscillation circuit output 101 is output as described above, the comparator 5
As shown in FIG. 2(b), the integral signal 104 input to the inverting input terminal of the comparator 6 and the input terminal of the comparator 6 is
Reference potential 102 (High potential) and reference potential 1103 (
Since it is within the level range of Lo potential), comparator 5
and 6 both output a high potential. The outputs of the comparators 5 and 6 are input to the AND circuit 7, but as mentioned above, when the oscillation output 1 is output from the oscillation circuit 1, the output 105 of the AND circuit 7 is the second output.
A high potential is output as shown in Figure (C).

AND回路7の出力105はフリップフロップ回路8の
ディレィ入力端子に入力され、端子53から入力される
判定入力信号106によりフリップフロップ回路8内に
取込まれて、端子54を介して発振出力有りの判定信号
が出力される。この場合、判定入力信号106は、発振
回路1がスイッチ・オン後、正常に動作状態に入るまで
の予備時間を設定するための信号で、第2図(a)に示
されるように、常時はHigh電位となっているが、発
振の有無を検知する検°知点においてLow電位となり
、この時点においてAND回路7の出力105はフリ7
17671回路8に取込まれ、発振回路1の発振出力有
りに対応して、High電位の判定信号が端子54を介
して出力される。
The output 105 of the AND circuit 7 is input to the delay input terminal of the flip-flop circuit 8, is taken into the flip-flop circuit 8 by the judgment input signal 106 input from the terminal 53, and is output via the terminal 54 to determine whether there is an oscillation output. A determination signal is output. In this case, the judgment input signal 106 is a signal for setting a preliminary time until the oscillation circuit 1 enters a normal operating state after being switched on, and as shown in FIG. However, at the detection point that detects the presence or absence of oscillation, it becomes a low potential, and at this point, the output 105 of the AND circuit 7 becomes a low potential.
The signal is taken into the 17671 circuit 8, and a high potential determination signal is outputted via the terminal 54 in response to the presence of oscillation output from the oscillation circuit 1.

また、発振回路1から発振出力101が出力されていな
い場合には、固定の電位がインバータ2に与えられ、イ
ンバータ2の出力は旧gh電位かまたはLow電位に固
定される。この場合には、コンパレータ5および6の入
力段階において、入力電位が第2図(b)に示される基
準電位10102(Hi電位)および基準電位1103
(Lo電位)のレベル範囲内に入らず、コンパレータ5
および6の内の一方のコンパレータからは必ずLow電
位が出力される。従って、AND回路7の出力105は
Low電位にて出力され、フリップフロップ回路8のデ
ィレィ入力端子に入力される。前述の場合と同様に、出
力105は端子53から入力される判定入力信号106
を介してフリップフロップ回路8内に取込まれ、端子5
4を介して発振出力無しの判定信号がLow電位にて出
力される。
Further, when the oscillation output 101 is not output from the oscillation circuit 1, a fixed potential is applied to the inverter 2, and the output of the inverter 2 is fixed to the old gh potential or the Low potential. In this case, at the input stage of comparators 5 and 6, the input potentials are the reference potential 10102 (Hi potential) and the reference potential 1103 shown in FIG. 2(b).
(Lo potential) does not fall within the level range, and comparator 5
A low potential is always output from one of the comparators 6 and 6. Therefore, the output 105 of the AND circuit 7 is output at a low potential and is input to the delay input terminal of the flip-flop circuit 8. As in the previous case, the output 105 is the judgment input signal 106 input from the terminal 53.
is taken into the flip-flop circuit 8 via the terminal 5.
4, a determination signal indicating no oscillation output is output at a low potential.

なお、フリップフロップ回路8が発振出力有無の判定結
果の記憶回路として作用することは言うまでもない。
It goes without saying that the flip-flop circuit 8 functions as a storage circuit for the determination result of whether or not there is an oscillation output.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、発振回路の発振出力積
分値と所定の基準電圧との比較照合結果の論理積をとり
、所定の記憶回路に取込むことにより、周波数カウンタ
およびマイクロコンピュータ等の高価な装置類を必要と
せず、極めて箔易な回路構成にて形成される発振検知回
路を提供することができるという効果がある。
As explained above, the present invention calculates the logical product of the comparison result between the oscillation output integral value of the oscillation circuit and a predetermined reference voltage, and stores the result in a predetermined storage circuit. The present invention has the advantage that it is possible to provide an oscillation detection circuit that does not require expensive equipment and is formed with an extremely simple circuit configuration.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の要部を示す回路図、第2図
(a)、(b)および(c)は、前記一実施例における
各部の動作信号波形図、第3図は、従来の発振検知回路
の要部を示す回路図である。 図において、1.9・・・発振回路、2・・・インバー
タ、3・・・抵抗、4・・・コンデンサ、5,6・・・
コンパレータ、7・・・AND回路、8・・・フリップ
フロップ回路、10・・・周波数カウンタ、11・・・
マイクロコンピュータ。 竿 l 凹 $ 3 面
FIG. 1 is a circuit diagram showing the main parts of an embodiment of the present invention, FIGS. 2(a), (b) and (c) are operation signal waveform diagrams of each part in the embodiment, and FIG. 3 is a circuit diagram showing main parts of an embodiment of the present invention. , is a circuit diagram showing a main part of a conventional oscillation detection circuit. In the figure, 1.9... Oscillation circuit, 2... Inverter, 3... Resistor, 4... Capacitor, 5, 6...
Comparator, 7...AND circuit, 8...Flip-flop circuit, 10...Frequency counter, 11...
microcomputer. Rod l concave $ 3 sides

Claims (1)

【特許請求の範囲】[Claims] 発振回路の発振出力を積分する積分回路と、前記積分回
路の出力が二つの基準電圧範囲内にあることを判定する
判定回路と、前記判定回路の判定結果を記憶する回路と
、を備えることを特徴とする発振検知回路。
The method further comprises: an integrating circuit that integrates the oscillation output of the oscillator circuit, a determination circuit that determines whether the output of the integrating circuit is within two reference voltage ranges, and a circuit that stores the determination result of the determination circuit. Characteristic oscillation detection circuit.
JP62111250A 1987-05-06 1987-05-06 Oscillation detection circuit Pending JPS63274873A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62111250A JPS63274873A (en) 1987-05-06 1987-05-06 Oscillation detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62111250A JPS63274873A (en) 1987-05-06 1987-05-06 Oscillation detection circuit

Publications (1)

Publication Number Publication Date
JPS63274873A true JPS63274873A (en) 1988-11-11

Family

ID=14556410

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62111250A Pending JPS63274873A (en) 1987-05-06 1987-05-06 Oscillation detection circuit

Country Status (1)

Country Link
JP (1) JPS63274873A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2005111639A1 (en) * 2004-05-19 2008-03-27 株式会社アドバンテスト Oscillation detection device and test device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2005111639A1 (en) * 2004-05-19 2008-03-27 株式会社アドバンテスト Oscillation detection device and test device

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