JP3220995B2 - Input impedance measurement circuit for IC circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for measuring whether an input impedance of an IC circuit is open or not.

[0002]

2. Description of the Related Art Next, the configuration of a conventional impedance measuring instrument will be described with reference to FIG. In FIG. 4, 11 is an oscillator, 12 is a variable resistor, and 13 is an impedance to be measured. FIG. 4 shows a case where the voltage at both ends of the variable resistor 12 and the voltage at both ends of the impedance 13 to be measured are made the same, and replacement measurement is performed.

[0003]

When the input of an IC circuit is used in an open state, the IC circuit becomes unstable, and in the worst case, the IC is damaged. Therefore, it is necessary to know whether the impedance of the IC circuit is open or not. In this case, it is not necessary to obtain a numerical value as in a conventional impedance measuring instrument.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an input impedance measuring circuit for an IC circuit which determines that the IC circuit is not in an open state when the impedance of the IC circuit to ground is too low and when the impedance to power supply is too low.

[0005]

In order to achieve this object, the present invention relates to a counter circuit formed in an IC circuit under test 1.
Between the source impedance 1A and the ground impedance 1B.
The connection point is the measurement terminal 1C, and the first measurement voltage is the measurement terminal
A measurement terminal 2B applied to 1C and a first measurement voltage
Is divided by the ground impedance 1B and the internal resistance.
And an output terminal 2C for measuring the first measurement voltage.
When applied to the constant terminal 1C, the impedance to ground 1B
A high-level measurement circuit 2 for measuring a level change of a first measurement voltage based on a change in the voltage, and a second measurement voltage is applied to a measurement terminal 1C
And a second measuring voltage applied to the measuring terminal 3B.
Divided by power supply impedance 1A and internal resistance and output
And an output terminal 3C for supplying a second measured voltage to the measuring terminal.
When applied to the power supply 1C, the impedance of the power supply 1A changes.
Low-level measurement circuit 3 for measuring the level change of the second measurement voltage based on the conversion, clock circuit 4 for generating clock signal 4A, and IC circuit 1 to be measured by clock signal 4A.
Measurement terminals 1C and the first switch 5 for turning on and off the connection between the high-level measurement terminals 2B of the measuring circuit 2, the clock signal 4A of the measured IC circuit 1 measuring terminal 1C and the low-level
A second switch 6 for turning on and off the connection to the measurement terminal 3B of the measurement circuit 3 and a first measurement voltage to the measurement terminal 1C.
Output from the output terminal 2C of the high-level measurement circuit 2.
The divided level of the first measured voltage to be applied is
Detects that the logic has been inverted from low to low
First comparator 7, the measurement terminal 1C and the second measurement voltage
Is applied to the output terminal 3C of the low-level measurement circuit 3
The divided level of the second measurement voltage output from the
Logically inverted from a low level to a high level
A second comparator 8 for detecting, and a first measuring voltage measuring terminal
1C, the divided voltage level of the first measured voltage
Is logically inverted to the low level by the first comparator 7
If detected, impedance to ground 1B is open
It is determined that it is not in the state, and the second measurement voltage is applied to the measurement terminal 2C.
Is applied, the divided level of the second measurement voltage is
The second comparator 8 detects that the logic has been inverted to the high level.
The power supply impedance 1A is open.
And a judgment circuit 9 for judging that it is not .

[0006]

Next, the configuration of an input impedance measuring device for an IC circuit according to the present invention will be described with reference to FIG. 1 is an IC circuit, 1A is power impedance to ground, 1B is impedance to ground, 1C is a measurement terminal, 2 is a high-level measurement circuit for measuring impedance to ground, and 3 is a low-level measurement circuit for measuring power impedance. 4 is a clock circuit,
5 and 6 are switches, 7 and 8 are comparators, and 9 is a judgment circuit.

The IC circuit 1 has a power source impedance of 1
A and ground impedance 1B. It is determined that both the impedance 1A to the power supply and the impedance 1B to the ground 1M or more are open. When the power supply voltage is 4.5V, the comparators 7.8 threshold 2 to 2.5V. Comparator 7
Is set so that the output of the comparator 7 is inverted when the input voltage of the comparator 8 becomes 2 V or less, and the output of the comparator 8 is inverted when the input voltage of the comparator 8 becomes 3 V or more.

In FIG. 1, in the case of a MOS type IC, it is detected that it is in an open state when it is about 1 MΩ or more, and it is detected that it is not open when it is 100 kΩ or less. In the case of a TTL-type IC, it is assumed that about 47 kΩ or more is open, and 10 kΩ or less is not open.

Next, an embodiment of the high-level measurement circuit 2 will be described with reference to FIG. 2A is a power supply terminal, 2B is a measurement terminal, and 2C is an output terminal. FIG. 2 shows that the impedance to power supply 1A is infinite and the impedance to ground 1B is 1
This is an example in the case of 00 kΩ. When 4.5 V is applied to the power supply terminal 2A, the output terminal 2C becomes 3.5V and the output terminal 2C becomes 3V when the measurement terminal 2B is open. When the measurement terminal 2B is connected to the measurement terminal 1C, the voltage of the output terminal 2C becomes about 1.7, and the comparator 7 is inverted.

Next, an embodiment of the low-level measuring circuit 3 will be described with reference to FIG. 3A is a power supply terminal, 3B is a measurement terminal, and 3C is an output terminal. FIG. 3 shows an example in which the power supply impedance 1A is 100 kΩ and the ground impedance 1B is infinite. When 4.5V is applied to the power supply terminal 3A, 0.9V is applied when the measurement terminal 3B is open,
C becomes 1.8V. When the measurement terminal 3B is connected to the measurement terminal 1C, the voltage of the output terminal 3C becomes about 3 V, and the comparator 8 is inverted. The clock circuit 4 alternately connects the high-level measurement circuit 2 and the low-level measurement circuit 3 to the measurement terminal 1C.

When the voltage supplied to the measurement terminal 1C fluctuates between the power supply impedance 1A and the ground impedance 1B of the IC circuit 1, the comparators 7.8 operate to send a signal to the judgment circuit 9. The determination circuit 9 holds the high-level state and the low-level state, and determines that the circuit is open if there is no voltage fluctuation at both the high level and the low level.

[0012]

According to the present invention, when the impedance with respect to the ground of the IC circuit is too low and when the impedance with respect to the power supply is too low, it is determined that the IC circuit is not in the open state.
The input impedance of the C circuit can be measured.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an input impedance measuring device of an IC circuit according to the present invention.

FIG. 2 is a circuit diagram of an embodiment of a high-level measurement circuit 2.

FIG. 3 is a circuit diagram of an embodiment of a low-level measurement circuit 3.

FIG. 4 is a configuration diagram of an impedance measuring device according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 IC circuit 1A Power supply impedance 1B Ground impedance 1C Measurement terminal 2 High level measurement circuit 3 Low level measurement circuit 4 Clock circuit 5 Switch 6 Switch 7 Comparator 8 Comparator 9 Judgment circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 27/02 G01R 31/26 G01R 31/28

Claims (1)

(57) [Claims] An electric circuit formed in an IC circuit to be measured (1).
Source impedance (1A) and impedance to ground (1
B) is a measuring terminal (1C), and the first measuring voltage is applied to the measuring terminal (1C).
Constant terminal (2B) and the first measured voltage
Output that divides the voltage by the impedance (1B) and the internal resistance and outputs
Terminal (2C), and a first measurement voltage is supplied to the measurement terminal (1C).
C), when applied to the ground impedance (1B)
A high-level measurement circuit (2) for measuring a level change of a first measurement voltage based on the change, and a measurement for applying a second measurement voltage to a measurement terminal (1C).
Constant terminal (3B) and the second measured voltage to the power supply impedance
Output that divides the voltage by the impedance (1A) and the internal resistance and outputs
Terminal (3C), and a second measurement voltage is supplied to the measurement terminal (1
C) when applied to the power supply impedance (1A)
A low level measurement circuit (3) for measuring a level change of a second measurement voltage based on the change, and a clock circuit (4) for generating a clock signal (4A )
A first switch (5) for turning on / off a connection between the measurement terminal (1C ) of the IC circuit under test (1) and the measurement terminal (2B) of the high-level measurement circuit (2 ) by a clock signal (4A ).
A second switch (6) for turning on / off the connection between the measurement terminal (1C ) of the IC circuit under test (1) and the measurement terminal (3B) of the low-level measurement circuit (3 ) by a clock signal (4A ).
And when the first measurement voltage is applied to the measurement terminal (1C),
Output from the output terminal (2C) of the level measurement circuit (2)
The divided level of the first measured voltage is a high level which is a reference.
And a first comparator (7) for detecting that the logic has been inverted to a low level and a second measurement voltage is applied to a measurement terminal (1C).
Output from the output terminal (3C) of the level measurement circuit (3)
The divided level of the second measured voltage is a reference low level.
And a second comparator (8) for detecting that the logic is inverted to a high level, and when a first measurement voltage is applied to the measurement terminal (1C),
The division level of the first measurement voltage is logically opposite to the low level.
Is detected by the first comparator (7)
Indicates that the impedance to ground (1B) is not open
And apply the second measurement voltage to the measurement terminal (2C).
The divided level of the second measurement voltage is higher than the high level.
Is detected by the second comparator (8)
The power supply impedance (1A) is open
And a determination circuit (9) for determining that the input impedance is not the input circuit.