JPH09113564A - Delay capacitor withstand voltage checking method and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To check withstand voltage while realizing correct delay time in a circuit for comparing voltage, delayed by a delay capacitor, with reference voltage by a comparator and outputting an output signal according to the compared result. SOLUTION: A withstand voltage checking pad 17 is connected to a terminal, provided on the side to be supplied with reference voltage VREF, of a comparator 16 for comparing the charge potential VCHARG of a delay capacitor with the reference voltage VREF and outputting a signal according to the compared result. In checking the withstand voltage of the delay capacitor C, voltage sufficiently larger than the reference voltage VREF is supplied from the withstand voltage checking pad 17. Time until the inversion of output of the compartor 16 is clocked, and the leakage current of the delay capacitor C is detected according to the clocked time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for checking withstand voltage of a delay capacitor and a semiconductor integrated circuit, and more particularly, it compares a voltage delayed by the delay capacitor with a reference voltage by a comparator and responds to the magnitude relation. The present invention relates to a withstand voltage check method for a delay capacitor and a semiconductor integrated circuit used when checking the withstand voltage of a delay capacitor in a circuit that outputs an output signal.

[0002]

2. Description of the Related Art In a system reset circuit that generates a reset signal that gives a reset instruction to a system when the power is turned on, the reset signal is delayed after a time from when the voltage is turned on until the voltage is stabilized. It is configured to output.

FIG. 5 shows a circuit of a conventional system reset circuit.
A block diagram is shown. The conventional system reset circuit 1 is a constant voltage
Source 2a and Zener diode D1
Voltage V_REFGenerating a reference voltage source 2, resistors R1 and R
2 and the input voltage V _CCVoltage dividing circuit 3 for dividing
Reference voltage V generated by the reference voltage source 2_REFAnd partial pressure times
Input voltage V on path 3_CCVoltage V obtained by dividing_DIVAnd
Compare and divide voltage V_{DI V}Is the reference voltage V_REFLess than
Becomes high level and the divided voltage V_DIVIs the reference voltage V
_REFOutputs an output signal that becomes low level when larger
Comparator 4, input voltage V_CCGenerate more constant current
Constant current source 5 and the current supplied from the constant current source 5
From the delay capacitor C and NPN transistor
When the output signal of the comparator 4 is high level,
To discharge the delay capacitor C,
Turns off when the output signal is at low level and delay capacitor
Charging control transistor Q that makes C chargeable
1. Charge potential of delay capacitor C and reference voltage source 2
Reference voltage V generated by_REFAnd compare the delay capacitor
The charging potential of the sensor C is the reference voltage V_REFWhen smaller
It becomes low level, and the charging potential of the delay capacitor C is
Sub-voltage V_REFOutput that becomes high level when larger
Comparator 6 that outputs a signal, NPN transistor
When the output signal of comparator 6 is high level
Is turned on and the output signal of the comparator 6 is low level.
Output transistor Q2, which turns off when
It is connected to the connection point between Densa C and constant current source 5,
Pad for pressure resistance check to check the pressure resistance of capacitor C
It is composed of 7.

To increase the delay time, it is necessary to reduce the charging current and increase the capacitance of the capacitor.
Since the delay time greatly changes due to the leak current of the delay capacitor, it is important to check the withstand voltage of the delay capacitor. In order to check the withstand voltage of the delay capacitor C in the circuit of FIG. 5, a voltage is applied to the withstand voltage check pad 7 and a voltage is directly applied to the delay capacitor C to check the withstand voltage of the delay capacitor C. Was going on.

[0005]

However, in the conventional method of checking the delay capacitor, the voltage for checking the withstand voltage is directly supplied to the delay capacitor to check the leak current and so on. When mounted, the withstand voltage check pad is directly connected to the delay capacitor, and it is important to manage the leak current from the pad. However, since the pad needs to be exposed on the surface of the chip, there is a problem that it is easily affected by moisture absorption from the package after packaging and a leak current is likely to occur.

The present invention has been made in view of the above points, and an object of the present invention is to provide a method for checking the withstand voltage of a delay capacitor and a semiconductor integrated circuit which can check the withstand voltage while realizing an accurate delay time. .

[0007]

According to a first aspect of the present invention, a delay capacitor for delaying an input voltage, the delay capacitor is connected to a first input terminal, and a reference voltage is applied to a second input terminal. In a delay capacitor withstand voltage checking method for checking the withstand voltage of the delay capacitor with a circuit having a comparator that outputs the output signal that is supplied and that compares the input voltage with the reference voltage and inverts according to the magnitude relation When checking the withstand voltage of the delay capacitor, a voltage corresponding to the withstand voltage of the delay capacitor is supplied to the second input terminal of the comparator, and the output signal of the comparator is supplied after the input voltage is supplied. Is measured, and the withstand voltage of the delay capacitor is checked according to the delay time.

According to the first aspect, a voltage corresponding to the withstand voltage of the delay capacitor is supplied to the second input terminal of the comparator, and the charging potential of the delay capacitor becomes a voltage according to the withstand voltage of the delay capacitor. , The time until the output of the comparator is inverted, that is, the delay time is measured,
The presence or absence of leak current can be checked by the measured delay time. That is, if there is a leak current in the capacitor, it takes a long time to charge the capacitor. Therefore, the leak current of the capacitor can be detected by detecting the delay time of the capacitor. At this time, by setting the voltage supplied to the second input terminal of the comparator high, the delay time of the capacitor can be lengthened, the influence of the leakage current of the capacitor can be increased, and the leakage current can be easily detected. Therefore, according to the first aspect, by setting the voltage supplied to the second input terminal of the comparator high at the time of checking the withstand voltage of the capacitor, the withstand voltage check of the capacitor can be performed without providing a pad directly connected to the capacitor. Therefore, even if a leak current occurs in the pad during use, the delay capacitor is not affected by the leak current, and the delay time is not changed.

According to a second aspect of the present invention, a delay capacitor for delaying an input voltage, the delay capacitor is connected to a first input terminal, and a reference voltage is supplied to a second input terminal. In a semiconductor integrated circuit having a comparator that compares a voltage and outputs an output signal that is inverted according to the magnitude relationship, the delay is connected when the withstand voltage of the delay capacitor is checked, which is connected to the second input terminal of the comparator. It has a withstand voltage check pad for supplying a voltage according to the withstand voltage of the for-use capacitor.

According to the second aspect, by providing the check pad on the second input terminal of the comparator, the leak current of the delay capacitor can be checked by the method of the first aspect, and the pad is directly connected to the capacitor. Therefore, even if a leak current occurs in the pad after the withstand voltage of the capacitor is checked, the influence of the leak current does not directly affect the charging of the capacitor, and the operation can be performed with a normal delay time.

According to a third aspect of the present invention, a constant voltage generating circuit which is provided between the withstand voltage checking pad and the second input terminal of the comparator and which generates a constant voltage, and a constant voltage generated by the constant voltage generating circuit are provided. And an amplifier circuit that amplifies and generates the reference voltage to be supplied to the second input terminal of the comparator.

According to the third aspect, since the voltage is supplied to the second input terminal of the comparator after being amplified by the amplifier circuit, the voltage supplied to the second input terminal of the comparator can be increased.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of the present invention will be described with reference to the drawings. In this embodiment, a method of checking the withstand voltage of the delay capacitor of the system reset circuit will be described. FIG. 1 shows a circuit configuration diagram of an embodiment of the present invention. The semiconductor integrated circuit 11 of this embodiment includes a reference voltage generation source 12 that generates a reference voltage V _REF , a voltage dividing circuit 13 that divides the applied voltage V _CC , and a reference voltage V that is generated by the reference voltage generation source 12.
_REF is compared with the _divided voltage V _DIV obtained by dividing the input voltage V _CC by the voltage dividing circuit 13, and the divided voltage V _DIV is the reference voltage V _DIV.
When it is smaller than _REF , it becomes high level and the divided voltage V
Comparator _{14 DIV} outputs an output signal at a low level when is greater than the reference voltage V _{RE F,} charged voltage V _CC
A constant current source 15 that generates a more constant current, a delay capacitor C that is charged by the current supplied from the constant current source 15,
It is composed of an NPN transistor, and is turned on when the output signal of the comparator 14 is high level to discharge the delay capacitor C, and is turned off when the output signal of the comparator 14 is low level to make the delay capacitor C chargeable. The charge potential of the charge control transistor Q11 and the delay capacitor C and the reference voltage V generated by the reference voltage source 12.
_REF is compared, and when the charging potential of the delay capacitor C is lower than the reference voltage V _REF , it is low level, and when the charging potential of the delay capacitor C is higher than the reference voltage V _REF, a comparator that outputs an output signal that is high level is output. 16, an NPN transistor, which is turned on when the output signal of the comparator 16 is at a high level and turned off when the output signal of the comparator 16 is at a low level, and a delay capacitor at the reference voltage input terminal of the comparator 16. It is composed of a withstand voltage check pad 17 which supplies a voltage for checking the withstand voltage of C.

The reference voltage source 12 is configured such that a constant current source 18 and a Zener diode D11 are connected in series, and is connected between a terminal T1 supplied with a _closing voltage V _CC and a ground terminal T _GND. The reference voltage V _REF is output from the connection point between the zener diode D11 and the Zener diode D11. Voltage dividing circuit 13
Has a configuration in which resistors R11 and R12 are connected in series and connected between a terminal T1 and a ground terminal T _GND , and a divided voltage V _{DI V obtained} by dividing the input voltage V _CC is connected between the resistors R11 and R12. Output from the point.

The non-inverting terminal of the comparator 14 is supplied with the reference voltage V _REF from the reference voltage source 12, and the inverting terminal of the comparator 14 is supplied with the input voltage V _CC from the voltage dividing circuit 13.
The _divided voltage V _{DIV obtained} by dividing the voltage is supplied. The comparator 14 receives the reference voltage V _REF supplied from the reference voltage source 12.
And compares the divided voltage V _DIV supplied from the voltage dividing circuit 13, when the divided voltage V _DIV is less than the reference voltage V _REF is low level, when the divided voltage V _DIV is greater than the reference voltage V _REF is , A high level output is generated and supplied to the base of the discharge control transistor Q11.

On the other hand, one end of the delay capacitor C is connected to the ground terminal T _GND and the other end is connected to the closing voltage supply terminal T1 via the constant current source 15. Delay capacitor C
Is connected to the inverting terminal of the comparator 16 and the discharge control transistor Q11 is connected.
Connected to the collector.

Further, the discharge control transistor Q11 is
The emitter is the ground terminal T_GNDConnected to. For discharge control
The output signal of the comparator 14 of the transistor Q11 is high.
Level, that is, input voltage V_CCIs the reference voltage V_REFYo
When it is less than the threshold, it is turned on and the delay capacitor C is discharged.
However, the output signal of the comparator 14 is low level, that is,
The input voltage V_CCIs the reference voltage V_REFWhen greater than
Is turned off so that the delay capacitor C can be charged. Late
The extension capacitor C has a supply voltage V_CCWhen turning on,
Pressure V_CCDivided voltage V_DIVIs the reference voltage V_REFLess than
The discharge control transistor Q11
Input voltage V_CCDivided voltage V_DIVIs the reference voltage V_REFYo
When it becomes larger, it is charged by the constant current source 15.
Charging potential V _CHARGIs configured to gradually increase
You.

Further, to the non-inverting terminal of the comparator 16, the reference voltage V _{RE F} from the reference voltage source 18 is supplied, a comparator 16 compares the reference voltage V _REF and the charge potential V _CHARG delay capacitor C , Delay capacitor C
When the charging potential V _CHARG of the delay capacitor C is lower than the reference voltage V _REF , it becomes a high level, and when the charging potential V _CHARG of the delay capacitor C becomes higher than the reference voltage V _REF , an output signal of a low level is output and the output transistor Q12.
Supply to the base.

The output transistor Q12 is an NPN transistor, the collector of which is connected to the output terminal T _OUT and the emitter of which is connected to the ground terminal T _GND .
Configures open collector output. In the output transistor Q12, the output of the comparator 16 is at a high level, that is, the discharge control transistor Q11 is turned off after the applied voltage V _CC is applied, and the constant current source 15 starts charging the delay capacitor C to delay the delay capacitor. When C is not sufficiently charged, it turns on and the output terminal T _OUT
Hold at low level. Also, the output transistor Q1
In No. 2, the output of the comparator 16 is at a low level, that is, the discharge control transistor Q11 is turned off after the applied voltage V _CC is applied, the constant current source 15 starts charging the delay capacitor C, and the delay capacitor C becomes fully charged, when the charge potential V _CHARG delay capacitor C is greater than the reference voltage V _REF is turned off, the output terminal T _{OU T} to the high level.

The withstand voltage check pad 17 is connected to the connection point between the reference voltage source 12 and the non-inverting terminal of the comparator 16, and a voltage is applied from the tester when the withstand voltage of the delay capacitor C is checked. The voltage of the non-inverting terminal is made twice the reference voltage V _REF .

Here, the normal operation of the system reset circuit 1 will be described. FIG. 2 shows an operation waveform diagram at the time of the reset operation of the embodiment of the present invention. FIG. 2A shows the applied voltage V
The waveform of _CC , (B) shows the waveform of the reference voltage V _REF , the broken line _shows the waveform of the charging potential V _CHARG , and (C) shows the waveform of the output voltage V _OUT .

The input voltage V _CC increases and its divided voltage V
_{When DIV} becomes higher than the reference voltage V _REF at time t1, the constant current source 15 starts charging the delay capacitor C. Charging the delay capacitor C is started, the charge potential V _CHARG at time t2 is the reference voltage V _{RE F} from as large as the output voltage V _CC becomes a high level. That is, the output voltage V _OUT is set to a high level after a lapse of a predetermined delay time T0 determined by the time constant of the delay capacitor C after the application of the predetermined voltage V _CC at time t1.

The operation of the delay capacitor C of the system reset circuit 1 at the time of checking the withstand voltage will be described below. FIG. 3 shows an operation explanatory diagram at the time of withstanding voltage check according to an embodiment of the present invention. 3A shows a waveform of the applied voltage V _CC , FIG. 3B shows a solid line of the reference voltage V _REF , and a broken line of the charging potential V _CHARG .
(C) shows the waveform of the output voltage V _OUT .

The withstand voltage check of the delay capacitor C is carried out in the state of the chip before packaging. The withstand voltage check pad 17 is formed so as to be exposed on the chip surface in the state of the chip, and the electrodes of the tester come into contact with the withstand voltage check. The withstand voltage check pad 17 is supplied with a check voltage 2V _{REF, which} is twice the reference voltage V _REF , from the tester during the withstand voltage check.

At the time of withstanding voltage check, the applied voltage V at time t3
_CC is increased, the _divided voltage V _DIV thereof is made larger than the reference voltage V _REF at time t3, and the delay capacitor C is charged from the constant current source 15. If there is no leak current in the delay capacitor C, the charging potential V _CHARG becomes larger than the reference voltage V _REF and the output voltage V _CC becomes high level at time t4 as shown in FIG. 3B.

However, if there is a leak current in the delay capacitor C, it takes time for the charging potential V _CHARG to _{reach the} withstand voltage check voltage 2V _REF . For example, the output voltage V _OUT becomes high level at time t5 which is longer than time t4. Or if the leakage current is large, the charging potential V _CHARG
Output voltage V _OU without breakdown voltage up to 2V _REF
T is fixed at low level. Therefore, the leak current of the delay capacitor C can be detected by measuring the time from when the applied voltage V _CC is applied to when the output voltage V _OUT becomes high level by the tester.

As described above, since the leak current of the delay capacitor C can be detected without directly supplying the voltage to the delay capacitor C, it is not necessary to provide a pad directly connected to the delay capacitor C, and therefore the delay is delayed. The capacitor C for use is not affected by the leak current of the pad.
In this case, the breakdown voltage check voltage 2V _REF is the reference voltage V _{RE F}
Since it is sufficiently larger, even a small leak current can be detected.

FIG. 4 shows a circuit configuration diagram of another embodiment of the present invention. In the figure, the same components as those of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In this embodiment, an amplifier circuit 21 is connected between the connection point between the withstand voltage check pad 17 and the reference voltage source 12 and the inverting input terminal of the comparator 16. The amplifier circuit 21 includes a constant current source 22, PN
It is composed of P-transistors Q13, Q15, Q16, NPN transistor Q14, and resistors R13, R14. The reference voltage V _REF is doubled and supplied to the inverting input terminal of the comparator 16 and also supplied to the withstand voltage checking pad 17. The withstand voltage check voltage is amplified twice and supplied to the inverting input terminal of the comparator 16.

For this reason, the pad 17 for pressure resistance check is used.
2V for supplied voltage for voltage check _REFAnd compa
4V to the inverting input terminal of the converter 16_REFCan be supplied.
Therefore, the voltage supplied to the inverting input terminal of the comparator 16 is
The pressure can be higher voltage.

[0030]

As described above, according to claim 1 of the present invention, the second comparator
By setting the voltage supplied to the input terminal of
Without providing a pad directly connected to the capacitor,
Since the withstand voltage of the capacitor can be checked, the delay capacitor is not affected by the leak current even if a leak current occurs in the pad during use, and the delay time does not change.

According to the second aspect, by providing the check pad on the second input terminal of the comparator, the leak current of the delay capacitor can be checked by the method of the first aspect, and the pad is directly connected to the capacitor. Therefore, even if a leak current occurs in the pad after checking the withstand voltage of the capacitor, the influence of the leak current does not directly affect the charging of the capacitor, and it is possible to operate with a normal delay time. Have.

According to the third aspect, since the voltage is supplied to the second input terminal of the comparator by being amplified by the amplifier circuit, the voltage supplied to the second input terminal of the comparator can be increased. Have.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is an operation waveform diagram in a normal operation according to the embodiment of the present invention.

FIG. 3 is an operation waveform diagram during a withstand voltage check according to an embodiment of the present invention.

FIG. 4 is a circuit configuration diagram of another embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of an example of the related art.

[Explanation of symbols]

 11, 20 System reset circuit 12 Reference voltage generation source 13 Voltage dividing circuit 14, 16 Comparator 15 Constant current source 17 Withstand voltage check pad 21 Amplification circuit

Claims (3)

[Claims] 1. A delay capacitor for delaying an input voltage, and the delay capacitor is connected to a first input terminal,
A reference voltage is supplied to the second input terminal, and a circuit having a comparator that compares the input voltage with the reference voltage and outputs an output signal that is inverted according to the magnitude relationship is used. In the delay capacitor withstand voltage checking method for checking, a voltage corresponding to the withstand voltage of the delay capacitor is supplied to the second input terminal of the comparator when the withstand voltage of the delay capacitor is checked, and the input voltage is A method for checking the withstand voltage of a delay capacitor, which comprises measuring a delay time from when the signal is supplied to when the output signal of the comparator is inverted, and checking the withstand voltage of the delay capacitor according to the delay time. 2. A delay capacitor for delaying an input voltage, and the delay capacitor is connected to a first input terminal,
A semiconductor integrated circuit having a comparator which is supplied with a reference voltage to a second input terminal, compares the input voltage with the reference voltage, and outputs an output signal which is inverted according to the magnitude relation, 2. A semiconductor integrated circuit having a withstand voltage check pad connected to two input terminals and supplying a voltage according to the withstand voltage of the delay capacitor when the withstand voltage of the delay capacitor is checked. 3. A constant voltage generating circuit, which is provided between the withstand voltage checking pad and the second input terminal of the comparator, and which generates a constant voltage, and amplifies the constant voltage generated by the constant voltage generating circuit. 3. The semiconductor integrated circuit according to claim 2, further comprising an amplifier circuit that generates the reference voltage to be supplied to the second input terminal of the comparator.