JPH11353036A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH11353036A JPH11353036A JP10158261A JP15826198A JPH11353036A JP H11353036 A JPH11353036 A JP H11353036A JP 10158261 A JP10158261 A JP 10158261A JP 15826198 A JP15826198 A JP 15826198A JP H11353036 A JPH11353036 A JP H11353036A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- circuit
- power supply
- internal
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Tests Of Electronic Circuits (AREA)
- Control Of Voltage And Current In General (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、内部電圧発生回路
を有する半導体装置に関するものである。The present invention relates to a semiconductor device having an internal voltage generating circuit.
【0002】[0002]
【従来の技術】従来の上記半導体装置を図面に基づいて
説明する。図4は従来の半導体装置のブロック図であ
る。2. Description of the Related Art A conventional semiconductor device will be described with reference to the drawings. FIG. 4 is a block diagram of a conventional semiconductor device.
【0003】図4において、1は、高精度の一定電圧値
の直流電圧を発生する外部電圧印加装置(図示せず)に
接続される外部端子、2は半導体装置5用の電源装置
(図示せず)に接続される外部電源端子であり、外部電
源端子2を介して供給される電源電圧VDDにより半導
体装置5用の内部電圧VGを発生する内部電圧発生回路
3が設けられている。この内部電圧発生回路3により発
生された内部電圧VGと外部端子1を介して印加された
一定電圧値の外部入力電圧EVPIの一方が選択回路4
により選択され、内部電源電圧VPIとして出力され
る。In FIG. 4, reference numeral 1 denotes an external terminal connected to an external voltage applying device (not shown) for generating a DC voltage having a high accuracy and a constant voltage value, and 2 denotes a power supply device for a semiconductor device 5 (not shown). And an internal voltage generating circuit 3 for generating an internal voltage VG for the semiconductor device 5 from a power supply voltage VDD supplied via the external power supply terminal 2. One of the internal voltage VG generated by the internal voltage generating circuit 3 and the external input voltage EVPI having a constant voltage value applied via the external terminal 1 is selected by the selection circuit 4.
And output as the internal power supply voltage VPI.
【0004】上記構成による作用を説明する。半導体装
置5の通常動作時は外部電源端子2に電源電圧VDDが
供給され、内部電圧発生回路3の出力電圧VGが選択回
路4で選択され、内部電源電圧VPIとして使用され
る。しかし内部電源電圧VPIの電圧値は内部電圧発生
回路3の電源電圧特性、温度特性や半導体装置5の生産
ばらつきなどにより一定値にはならない。そこで半導体
装置内部回路の試験時には、外部端子1から入力した高
精度の一定電圧値の入力電圧EVPIを選択回路4で選
択し内部電源電圧VPIとして使用する。The operation of the above configuration will be described. During the normal operation of the semiconductor device 5, the power supply voltage VDD is supplied to the external power supply terminal 2, and the output voltage VG of the internal voltage generation circuit 3 is selected by the selection circuit 4 and used as the internal power supply voltage VPI. However, the voltage value of the internal power supply voltage VPI does not become a constant value due to power supply voltage characteristics and temperature characteristics of the internal voltage generation circuit 3, production variations of the semiconductor device 5, and the like. Therefore, when testing the internal circuit of the semiconductor device, the selection circuit 4 selects the input voltage EVPI of a high-precision constant voltage input from the external terminal 1 and uses it as the internal power supply voltage VPI.
【0005】このように、外部から供給する高精度の一
定電圧値の入力電圧EVPIを内部電源電圧VPIとす
ることにより、高精度の試験を実施することができる。
図5に上記内部電圧発生回路3のブロック図を示す。As described above, a highly accurate test can be performed by using the internal power supply voltage VPI as the high-precision input voltage EVPI supplied from the outside and having a constant voltage value.
FIG. 5 is a block diagram of the internal voltage generation circuit 3.
【0006】内部電圧発生回路3は、内部電源電圧設定
値VKを発生する基準電圧発生回路13と、この基準電圧
発生回路13により発生される内部電源電圧設定値VK
と、選択回路4へ出力される内部電源電圧VGとの電圧
比較結果を出力する電圧比較回路16と、電圧比較回路16
からの出力に応じて内部電源電圧VGを発生する電圧発
生回路17から構成されている。The internal voltage generation circuit 3 includes a reference voltage generation circuit 13 for generating an internal power supply voltage set value VK, and an internal power supply voltage set value VK generated by the reference voltage generation circuit 13.
A voltage comparison circuit 16 for outputting a result of voltage comparison with the internal power supply voltage VG output to the selection circuit 4;
And a voltage generation circuit 17 for generating an internal power supply voltage VG according to the output from the power supply.
【0007】上記構成により、基準電圧発生回路13が発
生する内部電源電圧設定値VKと内部電源電圧VGとが
電圧比較回路16で比較され、内部電源電圧VGと内部電
源電圧設定値との電圧比較結果が電圧発生回路17へ出力
され、電圧発生回路17は入力した電圧比較結果に応じて
出力電圧(内部電源電圧VG)を上昇あるいは下降させ
る。その結果、内部電源電圧VGは基準電圧発生回路13
が発生する内部電源電圧設定値に一致する。With the above configuration, the internal power supply voltage set value VK generated by the reference voltage generation circuit 13 and the internal power supply voltage VG are compared by the voltage comparison circuit 16, and the voltage comparison between the internal power supply voltage VG and the internal power supply voltage set value is performed. The result is output to the voltage generation circuit 17, and the voltage generation circuit 17 raises or lowers the output voltage (internal power supply voltage VG) according to the input voltage comparison result. As a result, the internal power supply voltage VG is
Coincides with the set value of the internal power supply voltage at which the error occurs.
【0008】上述の内部電圧発生回路3により発生され
る出力電圧VGが一定値にはならないのは主に基準電圧
発生回路13の出力値がばらつくことによるものである。The reason why the output voltage VG generated by the internal voltage generating circuit 3 does not become a constant value is mainly because the output value of the reference voltage generating circuit 13 varies.
【0009】[0009]
【発明が解決しようとする課題】従来の半導体装置で
は、通常動作時は電源電圧VDDを外部電源端子2に供
給することにより、内部電圧発生回路3が動作し電圧が
出力されるため、図6(a)に示すように電源電圧VD
Dの入力に対して内部電源電圧VPIの立ち上がりは鈍
った波形になる。しかし、試験時に外部端子1の入力電
圧EVPIを内部電源電圧VPIとする場合は、図6
(b)に示すように外部端子1の入力電圧EVPIが外
部電圧印加装置から供給される急峻な波形であるため内
部電源電圧VPIの立ち上がりも急峻となる。このよう
に内部電源電圧VPIの立ち上がりが通常動作時と異な
り急峻であると、半導体装置内部回路に対して通常動作
時よりも過剰なストレスを与えることになり正しい試験
が実施できないという問題があった。In a conventional semiconductor device, the power supply voltage VDD is supplied to the external power supply terminal 2 during normal operation, whereby the internal voltage generating circuit 3 operates and a voltage is output. As shown in FIG.
The rise of the internal power supply voltage VPI with respect to the input of D has a dull waveform. However, when the input voltage EVPI of the external terminal 1 is set to the internal power supply voltage VPI during the test, FIG.
As shown in (b), since the input voltage EVPI of the external terminal 1 has a steep waveform supplied from the external voltage applying device, the rise of the internal power supply voltage VPI also becomes steep. If the rise of the internal power supply voltage VPI is steep unlike the normal operation, an excessive stress is applied to the internal circuit of the semiconductor device as compared with the normal operation, and there is a problem that a correct test cannot be performed. .
【0010】本発明は、このような半導体装置におい
て、試験時に高精度の内部電源電圧供給ができ、かつ半
導体装置内部回路に対して与えるストレスを通常動作時
と同等に抑えることができることを目的とする。[0010] It is an object of the present invention to provide a semiconductor device capable of supplying an internal power supply voltage with high accuracy during a test and suppressing a stress applied to an internal circuit of the semiconductor device to the same level as in a normal operation. I do.
【0011】[0011]
【課題を解決するための手段】本発明の半導体装置にお
いては、外部端子からの入力経路上に積分回路を挿入し
たものである。In a semiconductor device according to the present invention, an integrating circuit is inserted on an input path from an external terminal.
【0012】この本発明によれば、試験時に高精度の内
部電源電圧供給ができ、かつ半導体装置内部回路に対し
て与えるストレスを通常動作時と同等に抑えることがで
きる半導体装置が得られる。According to the present invention, it is possible to obtain a semiconductor device capable of supplying a highly accurate internal power supply voltage during a test and suppressing a stress applied to an internal circuit of the semiconductor device to the same level as in a normal operation.
【0013】[0013]
【発明の実施の形態】本発明の請求項1記載の発明は、
内部電圧発生回路を有する半導体装置であって、一定電
圧値の電圧を発生する外部電圧印加装置に接続される外
部端子と、前記外部端子を介して印加された外部入力電
圧を積分する積分回路と、前記積分回路の出力電圧と前
記内部電圧発生回路の出力電圧の一方を選択し、内部電
源電圧として出力する選択回路を備えたものであり、半
導体装置内部回路の試験時に、外部端子に供給される入
力電圧が急峻な波形であっても積分回路の出力は鈍った
波形になり、よって半導体装置内部回路に対しては通常
動作時と同等ストレスを実現でき、かつ高精度の一定電
圧値の内部電源電圧供給を実現できるという作用を有す
る。BEST MODE FOR CARRYING OUT THE INVENTION
A semiconductor device having an internal voltage generation circuit, comprising: an external terminal connected to an external voltage application device that generates a voltage having a constant voltage value; and an integration circuit that integrates an external input voltage applied via the external terminal. A selection circuit that selects one of the output voltage of the integration circuit and the output voltage of the internal voltage generation circuit and outputs the selected output voltage as an internal power supply voltage. Even if the input voltage has a steep waveform, the output of the integrator circuit becomes a dull waveform, so that the same stress can be realized in the internal circuit of the semiconductor device as in the normal operation, and the internal circuit of the constant voltage value with high accuracy can be realized. It has the effect of being able to supply power supply voltage.
【0014】請求項2記載の発明は、一定電圧値の電圧
を発生する外部電圧印加装置に接続される外部端子と、
基準電圧発生回路と、前記基準電圧発生回路の出力基準
電圧と前記外部端子を介して印加される一定電圧値の外
部基準電圧の一方を選択し、出力する選択回路と、前記
選択回路の出力電圧と内部電源電圧との電圧比較結果を
出力する電圧比較回路と、前記電圧比較回路の出力に応
じて前記内部電源電圧を発生する電圧発生回路を備えた
ものであり、半導体装置内部回路の試験時に基準電圧と
して外部より印加される高精度の一定電圧値の外部基準
電圧が選択されることにより、基準電圧は一定値とな
り、よって内部電源電圧を一定にでき、半導体装置内部
回路に対しては通常動作時と異なるストレスはかからな
いという作用を有する。According to a second aspect of the present invention, there is provided an external terminal connected to an external voltage applying device for generating a voltage having a constant voltage value,
A reference voltage generation circuit, a selection circuit that selects and outputs one of an output reference voltage of the reference voltage generation circuit and an external reference voltage having a constant voltage value applied through the external terminal, and an output voltage of the selection circuit. A voltage comparison circuit that outputs a voltage comparison result between the internal power supply voltage and the internal power supply voltage, and a voltage generation circuit that generates the internal power supply voltage in accordance with the output of the voltage comparison circuit. By selecting an external reference voltage having a high-precision constant voltage value applied from the outside as a reference voltage, the reference voltage becomes a constant value, so that the internal power supply voltage can be kept constant. This has the effect that no stress different from that during operation is applied.
【0015】以下、本発明の実施の形態を図面に基づい
て説明する。なお、従来例の図4と図5の構成と同一の
構成には同一の符号を付して説明を省略する。 (実施の形態1)図1は実施の形態1における半導体装
置のブロック図である。An embodiment of the present invention will be described below with reference to the drawings. The same components as those of the conventional example shown in FIGS. 4 and 5 are denoted by the same reference numerals, and description thereof is omitted. (First Embodiment) FIG. 1 is a block diagram of a semiconductor device according to a first embodiment.
【0016】本実施の形態1では、外部端子1にこの外
部端子1を介して印加された高精度の一定電圧値の外部
入力電圧を積分する積分回路6を接続しており、選択回
路4はこの積分回路6の出力電圧VSと内部電圧発生回
路3の出力電圧VGの一方を選択し、内部電源電圧VP
Iとして出力している。In the first embodiment, the external terminal 1 is connected to an integrating circuit 6 for integrating an external input voltage having a constant voltage value with high precision applied through the external terminal 1. One of output voltage VS of integrating circuit 6 and output voltage VG of internal voltage generating circuit 3 is selected, and internal power supply voltage VP
It is output as I.
【0017】上記構成による作用を説明する。半導体装
置5の通常動作時は外部電源端子2に電源電圧VDDが
供給され、内部電圧発生回路3の出力電圧VGが選択回
路4で選択され内部電源電圧VPIとして使用される。
しかし内部電源電圧VPIの電圧値は内部電圧発生回路
3の電源電圧特性、温度特性や半導体装置5の生産ばら
つきなどにより一定値にはならない。そこで半導体装置
内部回路の試験時には、外部端子1に印加される高精度
の一定電圧値の入力電圧EVPIを積分回路6で積分し
てその出力電圧VSを選択回路4で選択し内部電源電圧
VPIとして使用する。The operation of the above configuration will be described. During normal operation of the semiconductor device 5, the power supply voltage VDD is supplied to the external power supply terminal 2, and the output voltage VG of the internal voltage generation circuit 3 is selected by the selection circuit 4 and used as the internal power supply voltage VPI.
However, the voltage value of the internal power supply voltage VPI does not become a constant value due to power supply voltage characteristics and temperature characteristics of the internal voltage generation circuit 3, production variations of the semiconductor device 5, and the like. Therefore, when testing the internal circuit of the semiconductor device, the integration circuit 6 integrates the input voltage EVPI of a high-precision constant voltage applied to the external terminal 1, selects the output voltage VS by the selection circuit 4, and sets the output voltage VS as the internal power supply voltage VPI. use.
【0018】このように、半導体装置内部回路の試験時
には外部から供給される高精度の一定電圧値の入力電圧
EVPIが内部電源電圧VPIとなることにより、高精
度の試験を実施でき、かつ外部端子1に供給される入力
電圧EVPIが急峻な波形をしていても積分回路6の出
力電圧VS(内部電源電圧VPI)は、図2に示すよう
に、鈍った波形になることにより、半導体装置内部回路
に対しては通常動作時と同等のストレスを実現できる。As described above, when the internal circuit of the semiconductor device is tested, a highly accurate input voltage EVPI supplied from the outside and having a constant voltage value becomes the internal power supply voltage VPI. Even if the input voltage EVPI supplied to 1 has a steep waveform, the output voltage VS (internal power supply voltage VPI) of the integration circuit 6 becomes blunt, as shown in FIG. The same stress as in normal operation can be realized for the circuit.
【0019】(実施の形態2)図3は実施の形態2にお
ける半導体装置のブロック図である。従来の内部電圧発
生回路3に代えて、内部電源電圧設定値として基準電圧
を発生する基準電圧発生回路13を設け、選択回路4は、
この基準電圧発生回路13の出力電圧(内部電源電圧設定
値)VKと外部端子1を介して印加される高精度の一定
電圧値の外部入力電圧(外部から入力された内部電源電
圧設定値)EXTの一方を選択し、出力している。Second Embodiment FIG. 3 is a block diagram of a semiconductor device according to a second embodiment. Instead of the conventional internal voltage generating circuit 3, a reference voltage generating circuit 13 for generating a reference voltage as an internal power supply voltage set value is provided.
The output voltage (internal power supply voltage setting value) VK of this reference voltage generating circuit 13 and the external input voltage (internal power supply voltage setting value input from outside) of a high-precision constant voltage value applied via external terminal 1 EXT Is selected and output.
【0020】そして、選択回路4の出力電圧(選択され
た内部電源電圧設定値)と内部電源電圧VPIとの電圧
比較結果を出力する電圧比較回路16と、電圧比較回路16
の出力に応じて内部電源電圧VPIを発生する電圧発生
回路17が設けられている。A voltage comparison circuit 16 for outputting a voltage comparison result between the output voltage of the selection circuit 4 (the set value of the selected internal power supply voltage) and the internal power supply voltage VPI, and a voltage comparison circuit 16
Is provided with a voltage generating circuit 17 for generating an internal power supply voltage VPI in accordance with the output of.
【0021】上記構成による作用を説明する。通常動作
時には基準電圧発生回路13が出力する内部電源電圧設定
値VKが選択回路14から出力され、この内部電源電圧設
定値と内部電源電圧VPIが電圧比較回路16で比較さ
れ、内部電源電圧VPIと内部電源電圧設定値との電圧
比較結果が電圧発生回路17へ出力され、電圧発生回路17
は入力した電圧比較結果に応じて出力電圧(内部電源電
圧VPI)を上昇あるいは下降させる。この結果、内部
電源電圧VPIが基準電圧発生回路13が出力する内部電
源電圧設定値と一致する。The operation of the above configuration will be described. During normal operation, the internal power supply voltage set value VK output from the reference voltage generation circuit 13 is output from the selection circuit 14, and the internal power supply voltage set value and the internal power supply voltage VPI are compared by the voltage comparison circuit 16, and the internal power supply voltage VPI is The result of the voltage comparison with the set value of the internal power supply voltage is output to the voltage generation circuit 17, and the voltage generation circuit 17
Raises or lowers the output voltage (internal power supply voltage VPI) according to the input voltage comparison result. As a result, internal power supply voltage VPI matches the internal power supply voltage set value output by reference voltage generation circuit 13.
【0022】また半導体装置内部回路の試験時には外部
端子1からの高精度の一定電圧値の内部電源電圧設定値
EXTが選択回路4から出力され、内部電源電圧VPI
と電圧比較回路16で比較され、内部電源電圧VPIと
内部電源電圧設定値EXTとの電圧比較結果が電圧発生
回路17へ出力され、電圧発生回路17は入力した電圧比較
結果に応じて出力電圧(内部電源電圧VPI)を上昇あ
るいは下降させる。この結果、内部電源電圧VPIが外
部端子1からの高精度の一定電圧値の内部電源電圧設定
値EXTと一致する。During the test of the internal circuit of the semiconductor device, the internal power supply voltage set value EXT of a high-precision constant voltage value from the external terminal 1 is output from the selection circuit 4, and the internal power supply voltage VPI
Is compared by the voltage comparison circuit 16, and the result of the voltage comparison between the internal power supply voltage VPI and the internal power supply voltage set value EXT is output to the voltage generation circuit 17. The voltage generation circuit 17 outputs the output voltage ( The internal power supply voltage VPI is increased or decreased. As a result, the internal power supply voltage VPI matches the internal power supply voltage set value EXT of a constant voltage value with high accuracy from the external terminal 1.
【0023】このように、半導体装置内部回路の試験時
には外部から供給される高精度の一定電圧値の内部電源
電圧設定値EXTが内部電源電圧VPIの基準電圧とな
ることにより、基準電圧が一定値となり、内部電源電圧
VPIを高精度の一定電圧値とすることができ、よって
高精度の試験を実施できる。さらに、外部端子1に供給
される内部電源電圧設定値EXTが急峻な波形をしてい
ても半導体装置内部回路に対しては通常動作時と異なる
ストレスはかからず、半導体装置内部回路に対しては通
常動作時と同等ストレスを実現できる。As described above, when the internal circuit of the semiconductor device is tested, the internal power supply voltage set value EXT having a high precision and constant voltage supplied from the outside becomes the reference voltage of the internal power supply voltage VPI, so that the reference voltage becomes constant. Thus, the internal power supply voltage VPI can be set to a high-precision constant voltage value, so that a high-precision test can be performed. Further, even if the internal power supply voltage set value EXT supplied to the external terminal 1 has a steep waveform, no stress different from that in the normal operation is applied to the internal circuit of the semiconductor device, and the internal circuit of the semiconductor device is not applied to the internal circuit. Can achieve the same stress as in normal operation.
【0024】[0024]
【発明の効果】以上のように本発明によれば、外部端子
に急峻な波形を入力しても半導体装置内部回路に対して
は通常動作時と同等ストレスを実現でき、かつ高精度の
内部電源電圧供給を実現できるという有利な効果が得ら
れる。As described above, according to the present invention, even when a steep waveform is input to the external terminal, the same stress as in the normal operation can be realized in the internal circuit of the semiconductor device, and the internal power supply with high accuracy can be realized. An advantageous effect that voltage supply can be realized is obtained.
【図1】本発明の実施の形態1における半導体装置のブ
ロック図である。FIG. 1 is a block diagram of a semiconductor device according to a first embodiment of the present invention.
【図2】同半導体装置の外部端子電圧入力による内部電
源電圧の発生波形図である。FIG. 2 is a generation waveform diagram of an internal power supply voltage due to an external terminal voltage input of the semiconductor device.
【図3】本発明の実施の形態2における半導体装置のブ
ロック図である。FIG. 3 is a block diagram of a semiconductor device according to a second embodiment of the present invention.
【図4】従来の半導体装置のブロック図である。FIG. 4 is a block diagram of a conventional semiconductor device.
【図5】従来の半導体装置の内部電圧発生回路のブロッ
ク図である。FIG. 5 is a block diagram of an internal voltage generation circuit of a conventional semiconductor device.
【図6】従来の半導体装置の内部電圧発生回路による内
部電源電圧の発生波形と外部端子電圧入力による内部電
源電圧の発生波形図である。FIG. 6 is a diagram showing a waveform of an internal power supply voltage generated by an internal voltage generation circuit of a conventional semiconductor device and a waveform of an internal power supply voltage generated by input of an external terminal voltage.
1 外部端子 2 外部電源端子 3 内部電圧発生回路 4 選択回路 5 半導体装置 6 積分回路 13 基準電圧発生回路 16 電圧比較回路 17 電圧発生回路 EVPI 外部電圧印加装置からの入力電圧 EXT 内部電源電圧設定値(基準電圧) VG 内部電圧発生回路の出力電圧 VK 内部電源電圧設定値(基準電圧) VPI 内部電源電圧 VS 積分回路の出力電圧 DESCRIPTION OF SYMBOLS 1 External terminal 2 External power supply terminal 3 Internal voltage generation circuit 4 Selection circuit 5 Semiconductor device 6 Integrator circuit 13 Reference voltage generation circuit 16 Voltage comparison circuit 17 Voltage generation circuit EVPI Input voltage from external voltage application device EXT Internal power supply voltage set value ( Reference voltage) VG Output voltage of internal voltage generation circuit VK Internal power supply voltage set value (reference voltage) VPI Internal power supply voltage VS Output voltage of integration circuit
Claims (2)
あって、 一定電圧値の電圧を発生する外部電圧印加装置に接続さ
れる外部端子と、 前記外部端子を介して印加された外部入力電圧を積分す
る積分回路と、 前記積分回路の出力電圧と前記内部電圧発生回路の出力
電圧の一方を選択し、内部電源電圧として出力する選択
回路を備えたことを特徴とする半導体装置。1. A semiconductor device having an internal voltage generating circuit, comprising: an external terminal connected to an external voltage applying device for generating a voltage having a constant voltage value; and an external input voltage applied via the external terminal. A semiconductor device comprising: an integration circuit for integrating; and a selection circuit for selecting one of an output voltage of the integration circuit and an output voltage of the internal voltage generation circuit and outputting the selected voltage as an internal power supply voltage.
加装置に接続される外部端子と、 基準電圧発生回路と、 前記基準電圧発生回路の出力基準電圧と前記外部端子を
介して印加される外部基準電圧の一方を選択し、出力す
る選択回路と、 前記選択回路の出力電圧と内部電源電圧との電圧比較結
果を出力する電圧比較回路と、 前記電圧比較回路の出力に応じて前記内部電源電圧を発
生する電圧発生回路を備えたことを特徴とする半導体装
置。2. An external terminal connected to an external voltage applying device for generating a voltage having a constant voltage value, a reference voltage generating circuit, an output reference voltage of the reference voltage generating circuit, and an external terminal. A selection circuit that selects and outputs one of the external reference voltages, a voltage comparison circuit that outputs a voltage comparison result between an output voltage of the selection circuit and an internal power supply voltage, and an internal power supply that responds to an output of the voltage comparison circuit A semiconductor device comprising a voltage generating circuit for generating a voltage.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10158261A JPH11353036A (en) | 1998-06-08 | 1998-06-08 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10158261A JPH11353036A (en) | 1998-06-08 | 1998-06-08 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH11353036A true JPH11353036A (en) | 1999-12-24 |
Family
ID=15667764
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10158261A Pending JPH11353036A (en) | 1998-06-08 | 1998-06-08 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH11353036A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6836104B2 (en) | 2002-05-14 | 2004-12-28 | Nec Electronics Corporation | Internal power supply voltage control apparatus having two internal power supply reference voltage generating circuits |
JP2010139243A (en) * | 2008-12-09 | 2010-06-24 | Seiko Epson Corp | Test method of semiconductor device, test system therefor, and the semiconductor device |
-
1998
- 1998-06-08 JP JP10158261A patent/JPH11353036A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6836104B2 (en) | 2002-05-14 | 2004-12-28 | Nec Electronics Corporation | Internal power supply voltage control apparatus having two internal power supply reference voltage generating circuits |
JP2010139243A (en) * | 2008-12-09 | 2010-06-24 | Seiko Epson Corp | Test method of semiconductor device, test system therefor, and the semiconductor device |
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