JPH07141041A - Trimming method and circuit therefor - Google Patents

Abstract

PURPOSE:To enable redundancy measurement in the same state as the case of trimming while breaking a fuse by controlling the ON/OFF of a switching element such as an MOS transistor arranged in series to the fuse at the trimming circuit of a reference voltage based on a test mode signal. CONSTITUTION:In the trimming circuit for controlling the output voltage of a coefficient circuit at the coefficient circuit consisting of a differential amplifier 1 and a feedback circuit 2, MOS transistors M1-M6 are inserted in series to fuses F1-F6 of the feedback circuit 2. Then, the MOS transistors M1-M6 are controlled by the test mode signal generated by a test mode discriminating circuit 3 and a latch circuit 4. In this case, a reference voltage Vref can be controlled by controlling the ON/OFF of switching elements such as MOS transistors M1-M6 arranged in series to the fuses F1-F6. Therefore, the reference voltage can be controlled at high speed in comparison with the case of actually breaking the fuses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a trimming circuit and a trimming method for a reference voltage generated in the semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor device, an internal power supply having a voltage lower than that of an external power supply is required for reasons such as reduction of breakdown voltage of transistors and capacitors due to fine process, reduction of noise, and reduction of power consumption.

The internal step-down power supply circuit is generally composed of a reference voltage generating circuit and a differential amplifier. In order to stabilize the operation of the semiconductor device using the internal step-down power supply, it is necessary to stabilize the reference voltage.

On the other hand, since the manufacturing variation occurs in the manufacturing process, the reference voltage also varies. Therefore, the trimming circuit as shown in FIG. 8 is used to adjust the reference voltage.

A conventional trimming circuit will be described below with reference to FIG. As shown in the figure, the trimming circuit includes a differential amplifier 1, resistors R _{1 to} R ₆ and fuses F ₁ to.
The feedback circuit 2 is composed of F ₆ .

As the differential amplifier 1, for example, a current mirror type amplifier having a large gain (open loop gain) as shown in FIG. 3 is often used.

In FIG. 3, NMOS transistors M31 and M32 whose source electrodes are commonly connected form a differential pair, and the drain electrode of the NMOS transistor M31 is PM.
The NMOS transistor M3 is connected to the input terminal of the current mirror circuit composed of the OS transistors 33 and 34.
The drain electrode of 2 is connected to the connection point of the output terminal of the current mirror circuit and the gate electrode of the transistor 35, and the difference voltage between the signals input to the non-inverting input terminal Vin1 and the inverting input terminal Vin2 is amplified and output to the terminal Vout. It

In FIG. 8, the input voltage Vr is input to the non-inverting input terminal Vin1 of the differential amplifier 1, and assuming that the amplification factor of the differential amplifier 1 is sufficiently large, the reference voltage Vref is given by the following equation (1). To be

[0009]

[Equation 1]

Here, Ra and Rb are 2a and 2b, respectively.
Is the combined resistance of. For example, when the fuses F ₁ and F ₅ are cut, Ra = R ₁ + R ₃ Rb = R ₄ + R ₅ .

Therefore, when the reference voltage Vref is lower than the desired voltage, the fuses F ₁ and F ₂ are blown, and when the reference voltage Vref is high, the fuses F ₅ and F ₆ are blown to adjust the reference voltage Vref.

Further, as a conventional trimming circuit, Japanese Patent Laid-Open No. 172906/1993 discloses a switch means provided between n terminals which divide an output voltage of a differential amplifier and an input terminal of the differential amplifier. By programming through a decoder, a trimming circuit that operates stably with a small number of fuses, that is, a small area has been proposed.

FIG. 9 shows a flowchart of the trimming process in the semiconductor memory. As shown in the figure,
First, in a first wafer test (hereinafter referred to as “Pri P / W”), a reference voltage is measured and calculated based on the result to determine a fuse to be cut in the trimming circuit. Note that P / W is an abbreviation for Pass Wafer, and represents how many non-defective products per wafer are tested by, for example, a wafer prober and a tester.

After P / W, the fuse F of the trimming circuit
A fuse designated from _{1 to} F ₆ is cut and trimming is performed.

Next, a wafer test for redundancy replacement of defective memory cells (hereinafter referred to as "redundancy P / W") is performed to determine a fuse indicating an address of the defective memory and output fuse data.

The redundancy replacement of a defective memory cell will now be described. The memory circuit includes a redundant cell,
This means that when a defective memory cell is detected, the fuse corresponding to the address of the defective memory cell is blown and the defective memory cell is replaced with a redundant cell. When the defective memory cell is accessed after the redundancy replacement, the address of the defective memory cell is switched to the redundant cell.

Further, in the redundancy P / W, in order to detect a defect in a memory cell, various tests such as a refresh test for testing how long data can be retained without refreshing are performed on a wafer. Here, the refresh test will be described in detail. After writing data in a memory cell and waiting for a predetermined time, the memory cell is read to test whether or not the data is correctly held.

2 based on the fuse data output next
Trimming for the second time. In the second trimming, the fuse indicating the address of the defective memory is cut off. After that, a final wafer test (hereinafter referred to as "P / W") is performed.

Therefore, the trimming process in the conventional semiconductor memory requires a total of 5 processes as described above.

[0020]

This conventional trimming method has a problem that the number of steps is increased because the trimming is performed twice.

Further, if the trimming process is forcibly performed once, the test conditions in the redundancy P / W are different, and the redundancy replacement cannot be effectively performed.

More specifically, for example, the reference voltage V
If ref is lower than the desired value, the reference voltage Vref
Since the internal voltage generated by the substrate voltage is lowered and the frequency of the oscillator of the substrate voltage generation circuit is lowered, the substrate voltage Vsub supplied via the pumping circuit becomes shallow (that is, becomes small on the negative side), and the voltage from the memory cell to the substrate is reduced. Leakage current is reduced. Therefore, the reference voltage Vre is not trimmed.
If a refresh test or the like is performed while f is low, the test conditions become unsatisfactory, and memory cells that are close to the test margin do not become defective, and replacement of defective memory cells with redundant cells is not performed correctly. I can't test.

On the contrary, when the reference voltage Vref is higher than the desired value, the internal voltage increases, the frequency of the oscillator of the substrate voltage generating circuit increases, and the substrate voltage Vsub becomes deep (that is, becomes large on the negative side). , The leakage current from the memory cell to the substrate increases. Therefore, if a refresh test or the like is performed while the reference voltage Vref is high without trimming, the test conditions become strict, and a non-defective memory cell may be replaced with a redundant cell, so that an effective test cannot be performed.

Therefore, in order to effectively perform the redundancy replacement, it is necessary to perform the redundancy P / W after trimming the reference voltage Vref. Trimming was required twice for the reasons described above.

Therefore, it is an object of the present invention to provide a trimming circuit and a trimming method which solve the above problems and reduce the trimming process.

[0026]

In order to achieve the above object, the present invention comprises a coefficient circuit including a differential amplifier and a feedback circuit, and the fuse circuit of the feedback circuit is trimmed by trimming the fuse element of the feedback circuit. In the trimming circuit that is designed to adjust the output voltage,
A trimming circuit comprising: a switching element arranged in series with the fuse element; and means for controlling ON / OFF of the switching element according to a test mode signal.

Further, the present invention is a trimming circuit which is composed of a coefficient circuit composed of a differential amplifier and a feedback circuit, and which adjusts the output voltage of the coefficient circuit by trimming the fuse element of the feedback circuit. A trimming method for a semiconductor memory having redundant cells, comprising a switching element in series with the fuse element, and a trimming circuit configured to control ON / OFF of the switching element according to a test mode signal. (a) measuring a reference voltage, (b) calculating a fuse to be blown based on the measured voltage,
(c) outputting the fuse data, and (d) entering the test mode and setting the switching element arranged in series with the fuse element to be cut based on the fuse data to the off state to measure the reference voltage. Adjusting the reference voltage, (e) measuring the redundancy in the test mode, and (f) outputting fuse data including information on the fuse to be cut in the trimming circuit and the fuse to be cut for redundancy replacement. Of the above, (a) ~ (f) the redundancy wafer test step consisting of each step, the trimming step of cutting the fuse based on the fuse data output in the step (f), and the final wafer test step. Provide a trimming method.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

[0029]

Embodiment 1 FIG. 1 shows a trimming circuit according to an embodiment of the present invention. Reference numeral 1 is a differential amplifier, reference numeral 2 is a feedback circuit, reference numeral 3 is a test mode determination circuit, reference numeral 4 is a latch circuit, R _{1 to} R ₆ are resistors, F _{1 to} F ₆ are fuses, and M ₁ to.
M ₅ is a MOS transistor.

The fuses F _{1 to} F ₆ of the feedback circuit 2
The reference voltage Vref is adjusted by changing the feedback ratio by disconnecting the same as in the conventional example.

In the trimming circuit of this embodiment, MOS is connected in series with the fuses F _{1 to} F ₆ of the feedback circuit 2.
Transistors M _{1 to} M ₆ are inserted, and these MOS transistors M _{1 to} M ₆ are controlled by the test mode signal generated by the test mode determination circuit 3 and the latch circuit 4.

The differential amplifier 1 is similar to the conventional example shown in FIG.
A current mirror type amplifier is used.

The latch circuit 4 for controlling the MOS transistors M _{1 to} M ₆ is composed of, for example, the circuit shown in FIG. As shown in the figure, the latch circuit 4 includes a D-F / F (D-type flip-flop) for storing and holding the on / off states of the MOS transistors M _{1 to} M ₆ , and a D-F in the test mode. / F state is set to the MOS transistors M _{1 to} M ₆
To the MOS transistor M ₁ in the normal operation mode.
Composed of NAND gates to the ~M ₆ is turned on.

Fuse data to be cut is input to the data input terminals D _{1 to} D ₄ of the D-F / F, and is fetched and held in the D-F / F in synchronization with the clock φ. The test mode signal TEST from the test mode determination circuit 3 is set to "H" level in the test mode. For example, when the fuse to be cut is F ₁ in FIG. 1, the terminal D ₁ is applied with "H" level and latched. output r1 of the circuit 4 becomes "L" level, MOS transistor M ₁ is turned off. Also,
In the normal operation mode, the test mode signal TEST is at "L" level, and the outputs r1 to r4 of the NAND circuit are all at "H" level.

The test mode determination circuit 3 is constructed as shown in FIG. 5, for example. In FIG. 5, by applying a high voltage (for example, about 10 V) to the terminal SV, the PMO
The S-transistor M41 is turned on to charge the capacitor C1, the test mode signal TEST is set to the “H” level, and the test mode can be entered.

In FIG. 1, the input voltage Vr is input to the non-inverting input terminal Vin1 of the differential amplifier 1 and the reference voltage Vre.
If the amplification factor of the differential amplifier 1 is sufficiently large, f is given by the following equation (2).

[0037]

[Equation 2]

Here, Raa 'and Rbb' are synthetic resistances between aa 'and bb', respectively, but normally the resistance R
_{1 to} R ₆ are several tens kΩ to several hundred kΩ, the resistance of the fuse is several Ω, and the on resistance of the transistor is several Ω to several tens Ω, the resistance of the fuse and the on resistance of the transistor can be ignored.

Therefore, when the fuses F ₁ and F ₅ are blown, for example, Raa '= R ₁ + R ₃ Rbb' = R ₄ + R ₅ is expressed.

FIG. 2 shows a flow chart of the trimming process of the semiconductor memory in which the trimming circuit of this embodiment is mounted.

As shown in FIG. 2, first, the redundancy P /
At W (in this case, Pri P / W is not necessary), the reference voltage Vref is first measured, and the fuse to be cut is calculated from the result.

At this time, since the MOS transistors M _{1 to} M ₆ connected in series with the fuses F _{1 to} F ₆ are in the off state, if the reference voltage Vref is lower than the desired voltage as in the prior art example, the fuse F 1 _{If 1} and F ₂ are higher than the desired voltage, the fuses F ₅ and F ₆ are blown.

As shown in FIG. 7, for example, when four resistors and four fuses are set, the fuses to be cut are calculated according to Table 1. The circles in the fuse column of Table 1 indicate fuses to be cut.

The reference voltage Vref is measured by using a test mode which is already known, or the reference voltage Vref is measured.
This is done by providing a dedicated pad on f.

Next, in the trimming process of FIG. 2, after outputting the fuse data to be cut, the fuse mode is entered by entering the test mode and turning off the MOS transistor connected in series with the fuse to be cut. Make it the same as when it was cut. Then, in this state, it is measured again whether the reference voltage Vref has a desired value.

If the measured reference voltage Vref deviates from the desired value, calculate the fuse to be cut again,
After entering the test mode, the above process of measuring the reference voltage Vref is repeated until the desired voltage is reached.

When the reference voltage Vref reaches a desired value, a test for replacement of a defective memory cell is performed with redundancy P / W while the reference voltage Vref is kept at a desired value in a state where the test mode is entered, and a defect occurs. Fuse data including fuse cut information indicating the address of the memory cell is output.

In the next trimming process, the reference voltage Vref
The trimming circuit fuse and the redundancy replacement fuse are trimmed at the same time. in this way,
By simultaneously trimming the fuse of the trimming circuit of the reference voltage Vref and the fuse for replacing the redundancy cell, the conventional Pri P / W and the trimming step, that is, two steps in total can be omitted.

[0049]

Second Embodiment FIG. 6 shows a circuit configuration of a second embodiment of the present invention. Even if the resistors of the feedback circuit 2 are arranged in this way, the same effect as that of the first embodiment can be obtained.

Although the present invention has been described with reference to the first and second embodiments, the present invention is a test mode for turning on / off a switching element such as a MOS transistor arranged in series with a fuse in a trimming circuit for a reference voltage Vref in a test mode. It is characterized by the configuration that is controlled based on the signal so that a state equivalent to that when the fuse is cut can be created by turning off the switching element, for this reason, the redundancy measurement is performed in the same state as when trimming by cutting the fuse. Is assured to be performed accurately, and the trimming process is reduced to one time.

In this embodiment, in the trimming circuit for the reference voltage Vref, the reference voltage Vref can be adjusted by controlling on / off of the switching element such as a MOS transistor arranged in series with the fuse, and the fuse is actually blown. The reference voltage Vref can be adjusted at higher speed than in the case of performing. Further, since the switching element can be switched on / off many times, the reference voltage Vr
It is possible to adjust ef repeatedly until the desired voltage value is reached.

In this embodiment, four fuses are used, but it goes without saying that more fuses may be used so that the reference voltage can be finely adjusted.

The test mode determination circuit of the present embodiment,
The circuit configurations of the latch circuit, the differential amplifier and the like are merely examples of the configurations, and the present invention is not limited to the configurations of these examples, and various embodiments according to the principle of the present invention are possible. It includes.

[0054]

[Table 1]

[0055]

As described above, according to the present invention, a switching element such as a MOS transistor is arranged in series with a fuse element and ON / OFF of the switching element is controlled by a test mode signal. Since the feedback rate can be changed in the same state as when the fuse is blown in the adjustment of the reference voltage Vref without actually blowing the fuse, for example, the trimming step of the semiconductor memory can be performed once.

When the present invention is applied to a semiconductor memory having redundant cells, it is possible to cut the fuse of the trimming circuit for adjusting the reference voltage and the fuse for redundancy replacement in one trimming step. Therefore, the trimming process of the semiconductor memory is greatly reduced.

Further, according to the present invention, in the test mode, since the ON / OFF of the switching element is controlled to adjust the reference voltage Vref, the reference voltage Vref is adjusted as compared with the case where the fuse is actually cut. In addition, since the switching element can be turned on and off as many times as desired, the reference voltage Vref can be repeatedly adjusted until a desired voltage value is reached, and the fuse to be cut can be determined. Therefore, the trimming can be reliably performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing a trimming process in the present invention.

FIG. 3 is a circuit diagram of the differential amplifier in the embodiment of the present invention shown in FIG.

FIG. 4 is a diagram showing a latch circuit in the embodiment of the present invention shown in FIG.

5 is a diagram showing a test mode determination circuit in the embodiment of the present invention shown in FIG.

FIG. 6 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 7 is a diagram showing a specific example of element constants in the trimming circuit of the present invention.

FIG. 8 is a block diagram of a conventional trimming circuit.

FIG. 9 is a flowchart of a conventional trimming method.

[Explanation of symbols]

 1 differential amplifier 2 feedback circuit 3 test mode determination circuit 4 latch circuit

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/04 21/822 8832-4M H01L 27/04 T 8832-4MV

Claims (2)

[Claims] 1. A trimming circuit comprising a coefficient circuit comprising a differential amplifier and a feedback circuit, wherein the output voltage of the coefficient circuit is adjusted by trimming the fuse element of the feedback circuit. A switching element arranged in series with
A trimming circuit comprising: means for controlling ON / OFF of the switching element by a test mode signal. 2. A trimming circuit comprising a coefficient circuit composed of a differential amplifier and a feedback circuit, wherein the output voltage of the coefficient circuit is adjusted by trimming a fuse element of the feedback circuit. A trimming method for a semiconductor memory having redundant cells, comprising: a switching element in series with a fuse element; and a trimming circuit configured to control ON / OFF of the switching element by a test mode signal. Measuring the voltage, (b) calculating the fuse to be cut based on the measured voltage, (c) outputting the fuse data, (d) entering the test mode and cutting based on the fuse data The switching element arranged in series with the fuse element to be set is turned off and the reference voltage is measured. Output the fuse data including information on the fuse to be cut in the trimming circuit and the fuse to be cut for redundancy replacement. Of the steps (a) to (f), a redundancy wafer test step, a trimming step of cutting the fuse based on the fuse data output in the step (f), and a final wafer test step. And a trimming method consisting of.