CN110231557B - Starting circuit reliability verification method of band-gap reference circuit - Google Patents
Starting circuit reliability verification method of band-gap reference circuit Download PDFInfo
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- CN110231557B CN110231557B CN201910597553.2A CN201910597553A CN110231557B CN 110231557 B CN110231557 B CN 110231557B CN 201910597553 A CN201910597553 A CN 201910597553A CN 110231557 B CN110231557 B CN 110231557B
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Abstract
The invention discloses a method for verifying the reliability of a starting circuit of a band-gap reference circuit, which comprises the following steps: adding an ideal voltage source into a key node of the starting circuit, and performing direct current simulation verification to obtain a simulation result; and judging whether the starting circuit works normally or not according to the simulation result. According to the invention, an ideal voltage source is added to a key node of a starting circuit of the bandgap reference circuit, and the direct current simulation verification is carried out by taking the direct current voltage value of the ideal voltage source as a scanning variable, so that whether the starting circuit works normally or not is more fully verified; the direct current simulation verification can more fully verify all possible stable states of the circuit; the circuit design is more pertinently carried out, the production yield is improved, and the product risk is reduced.
Description
Technical Field
The invention relates to the technical field of band-gap reference circuits, in particular to a method for verifying the reliability of a starting circuit of a band-gap reference circuit.
Background
In analog integrated circuits and mixed-signal integrated circuits, a Band-Gap Reference (BGR) circuit is an important component block, and its basic function is to provide a highly stable Reference voltage almost independent of temperature and supply voltage for other functional blocks.
The important problem that a 'degenerate' bias point exists in the bandgap reference circuit is that at least two balanced operating points exist in the bandgap reference circuit, wherein one of the balanced operating points is a zero point, namely, the current of each branch of the core module is zero, and the circuit is turned off and can be kept in an off state indefinitely; one is the normal operating point. Since the circuit can be stabilized in any one of the two working states, a circuit is required to be added, so that the circuit can get rid of an unexpected degenerate working state and work normally after the power supply is powered on, and the circuit is a starting circuit. And after the band-gap reference circuit works normally, the starting circuit is closed. Therefore, the performance of the starting circuit can directly influence the performance of the band-gap reference circuit.
The performance of the starting circuit includes power consumption, power-on overshoot current, reliability and the like, wherein the most important performance is the reliability. There are many factors that affect the reliability of the start-up circuit: the process angle deviation, the power supply voltage magnitude and the temperature change are common influence factors, besides, mismatch (mismatch) of devices is also provided, even if completely same device units in a physical layout are produced through a process, deviation or difference of device parameters (such as the width-length ratio and the threshold voltage of an MOS (metal oxide semiconductor) tube) can be generated, the mismatch is called as mismatch, and the mismatch and the influence thereof are more serious after the size of the device enters a submicron range.
How to fully verify the reliability of the starting circuit before the chip is produced as much as possible so as to ensure that the starting circuit can normally work under various conditions, thereby not influencing the production yield and becoming a technical problem which needs to be solved urgently. At present, the following two common methods are generally used for verifying the reliability of the starting circuit of the bandgap reference circuit: (1) and (3) transient kernel simulation verification: the verification process is as shown in fig. 1, firstly, a circuit is built, verification excitation is set, the simulation excitation includes but is not limited to a device model, a simulation type, a data storage type, a power supply Voltage, temperature and/or variable parameter assignment and the like, and then a pvt (process Voltage temperature) corner is set, and transient corner simulation is performed. And after the simulation is finished, checking the simulation result, and judging whether the starting circuit works normally according to the simulation result. (2) Transient Monte Carlo (Monte Carlo) simulation verification: the verification process is shown in fig. 2, the first two steps are the same as the transient simulation verification step, a circuit is built, excitation is set, and then transient Monte Carlo simulation is carried out (sampling points are at least 1000 times). And after the simulation is finished, checking the simulation result, and judging whether the starting circuit works normally according to the simulation result.
Verification method (1) is simulation verification performed under PVT corner, and method (2) is simulation verification in a typical case when device mismatch is considered. The two verification modes relate to transient simulation, only one is transient kernel simulation, and the other is transient Monte Carlo simulation. The criterion for the transient simulation to determine whether the start-up circuit normally operates is to determine whether the final steady state of the transient output is the steady state in which the circuit normally operates, for example, the band gap reference output dc voltage should be 1.2V, if the final steady value of the transient simulation is also around 1.2V, and the start-up circuit is completely turned off in the steady state, it may be determined that the start-up circuit normally operates, and if the final steady value of the transient simulation is not 1.2V, but has a large deviation, for example, the final steady value is not within the range of 1.2V ± 100mV, or although the deviation is small, the start-up circuit is not completely turned off in the steady state, it may be determined that the start-up circuit cannot normally operate.
Although the transient verification method is simple and intuitive, the following disadvantages exist: the transient simulation is by nature contingent. The setting of simulation stimuli, the operational process of simulation tools, and the imperfect accuracy of device models all bring contingencies. Transient simulation results show that the final stabilization in the normally operating "degenerate" state cannot be equated with the absence of other "degenerate" states of the circuit, without excluding the following cases: the circuit has other one or more degenerate states, only the transient simulation result is just stabilized in the degenerate state of normal operation due to the contingency of the simulation excitation, and the transient simulation result can be stabilized in other incorrect degenerate states if the simulation excitation is changed or the simulation precision is adjusted.
Therefore, the transient simulation is used to verify the reliability of the start-up circuit of the bandgap reference circuit, and the verification process is not sufficient.
Disclosure of Invention
The present invention provides a method for verifying the reliability of a start-up circuit of a bandgap reference circuit, aiming at the above-mentioned defects in the prior art.
The technical scheme adopted by the invention for solving the technical problems is as follows: the method for verifying the reliability of the starting circuit of the bandgap reference circuit is provided, an ideal voltage source is added to a key node of the starting circuit of the bandgap reference circuit, and the method comprises the following steps:
performing direct current simulation verification on the ideal voltage source to obtain a simulation result;
and judging whether the starting circuit works normally or not according to the simulation result.
Preferably, the dc simulation verification is dc corner verification, and dc simulation verification is performed on an ideal voltage source to obtain a simulation result, specifically including the steps of:
s121, adding an ideal voltage source to a key node of the starting circuit;
s122, setting simulation excitation;
s123, setting a PVT corner;
s124, performing direct current corner simulation;
and S125, obtaining a simulation result.
Preferably, the dc simulation verification is dc Monte Carlo verification, and dc simulation verification is performed on an ideal voltage source to obtain a simulation result, and the method specifically includes the steps of:
s131, adding an ideal voltage source to a key node of the starting circuit;
s132, setting simulation excitation;
s133, carrying out direct current Monte Carlo simulation;
and S134, obtaining a simulation result.
Preferably, the dc simulation verification is mismatch dc corner verification, and dc simulation verification is performed on an ideal voltage source to obtain a simulation result, specifically including the steps of:
s141, adding an ideal voltage source at a key node of the starting circuit;
s142, calculating a mismatch value of the threshold voltage VT of the key MOS tube, and adding the mismatch value to the grid electrode of the MOS tube in a voltage source mode;
s143, setting simulation excitation;
s144, setting a PVT corner;
s145, performing direct current corner simulation;
and S146, obtaining a simulation result.
Preferably, the calculation formula of the mismatch value σ of the threshold voltage VT of the MOS transistor is:
w and L are respectively the gate width and gate length of the key MOS tube, AVTIs the original factory process constant of the MOS tube.
Preferably, the simulation stimulus comprises a device model, a simulation type, a data type, a supply voltage, a temperature and/or a variable parameter assignment.
Preferably, the performing dc simulation verification on the ideal voltage source to obtain a simulation result further includes the steps of:
scanning the DC voltage value of the ideal voltage source, and recording the DC current value flowing through the ideal voltage source.
Preferably, the direct current voltage value of the ideal voltage source is variable parameter VX, and the direct current value of the ideal voltage source is IX;
the scanning of the direct current voltage value of the ideal voltage source records the direct current value flowing through the ideal voltage source, and specifically comprises the following steps:
taking the direct current voltage value VX as a parameter to perform direct current simulation scanning, and recording a direct current value IX flowing through an ideal voltage source; the scanning range of the direct current voltage value VX is from zero to the power supply voltage.
Preferably, an IX curve is drawn by taking the direct current voltage value VX as an abscissa and the direct current value IX as an ordinate; the method for judging whether the starting circuit works normally or not according to the simulation result specifically comprises the following steps:
s251, calculating the number of intersection points of the IX curve and the abscissa axis;
s252, if the number of the intersection points of the IX curve and the abscissa axis is 1, judging that the starting circuit can normally work;
and S253, if the number of the intersection points of the IX curves and the abscissa axis is 0 or more than 2, judging that the starting circuit cannot normally work.
The technical scheme for implementing the method for verifying the reliability of the starting circuit of the band-gap reference circuit has the following advantages or beneficial effects: according to the invention, an ideal voltage source is added to a key node of a starting circuit of the bandgap reference circuit, and the direct current simulation verification is carried out by taking the direct current voltage value of the ideal voltage source as a scanning variable, so that whether the starting circuit works normally or not is more fully verified; the direct current simulation verification can more fully verify all possible stable states of the circuit; the circuit design is more pertinently carried out, the production yield is improved, and the product risk is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
FIG. 1 is a flow diagram of a transient kernel simulation for reliability verification of a prior art BGR startup circuit;
FIG. 2 is a transient Monte Carlo simulation flow diagram for reliability verification of a prior art BGR startup circuit;
FIG. 3 is a circuit diagram of a prior art bandgap reference circuit with a start-up circuit;
FIG. 4 is a circuit schematic of an embodiment of the bandgap reference circuit of the present invention with an ideal voltage source added at the critical node;
FIG. 5 is a schematic diagram of a circuit for adding mismatch values to the circuit as voltage sources in accordance with an embodiment of the bandgap reference circuit of the present invention;
FIG. 6 is a simplified flow chart of an embodiment of a method for verifying the reliability of a start-up circuit of a bandgap reference circuit of the present invention;
FIG. 7 is a complete flow chart of an embodiment of a method for verifying the reliability of a start-up circuit of a bandgap reference circuit of the present invention;
FIG. 8 is a DC corner simulation flowchart of an embodiment of a method for verifying the reliability of a start-up circuit of a bandgap reference circuit according to the present invention;
FIG. 9 is a flow chart of a direct current Monte Carlo simulation of an embodiment of a method for verifying the reliability of a start-up circuit of a bandgap reference circuit according to the present invention;
FIG. 10 is a flow chart of the mismatch DC corner simulation of the embodiment of the method for verifying the reliability of the starting circuit of the bandgap reference circuit of the present invention;
fig. 11 is a schematic diagram of a dc simulation result of an embodiment of a method for verifying the reliability of a start-up circuit of a bandgap reference circuit according to the present invention.
Detailed Description
In order that the objects, aspects and advantages of the present invention will become more apparent, various exemplary embodiments will be described below with reference to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration various exemplary embodiments in which the invention may be practiced, and in which like numerals in different drawings represent the same or similar elements, unless otherwise specified. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. It is to be understood that they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims, and that other embodiments may be used, or structural and functional modifications may be made to the embodiments set forth herein, without departing from the scope and spirit of the present disclosure. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. It should be noted that unless expressly specified or limited otherwise, the terms "connected" and "connected" are to be construed broadly, as if they could be electrically connected or could communicate with each other; either directly or indirectly through intervening media, either internally or in any combination thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples. Fig. 3 is a conventional bandgap reference circuit with a start-up circuit, and the basic circuit of fig. 3 is used to illustrate the technical solution of the present invention in detail. Fig. 4-11 are schematic diagrams provided by embodiments of the present invention, and for convenience of illustration, only the portions related to the embodiments of the present invention are shown.
The transient simulation verification of the starting circuit of the band-gap reference circuit has limitations, while the direct current simulation is relatively reliable for the steady-state verification of the circuit, because the direct current simulation is the steady-state simulation per se, and the actual process is the process of carrying out equation solution on the steady state of the circuit. When verifying the reliability of the starting circuit of the bandgap reference circuit, a direct current simulation verification method may be adopted to determine that the circuit has no other degenerate states. If only one steady state exists in the direct current simulation determination circuit, and the transient simulation result is combined, whether the starting circuit works normally or not is judged, so that the verification is more sufficient.
The invention takes the band-gap reference circuit of fig. 3 as an example, the band-gap reference circuit comprises a starting circuit, an amplifier circuit and two core branches which are connected in sequence, and the amplifier circuit is used for ensuring that the voltages of two nodes connected with the input ends of the core branches and the amplifier circuit are equal. As shown in fig. 4-5, the ideal voltage source is added to the critical node of the start-up circuit of the bandgap reference circuit. Specifically, the key node of the start-up circuit is generally the gate of the PMOS transistor of the core circuit. The value of the dc voltage of the ideal voltage source is variable parameter VX and the value of the dc current of the ideal voltage source is IX. More specifically, the method includes scanning a dc voltage value of an ideal voltage source, and recording a dc current value flowing through the ideal voltage source, specifically: and (3) taking the direct current voltage value VX as a parameter to carry out direct current simulation scanning, and recording a direct current value IX flowing through an ideal voltage source, wherein the scanning range of the direct current voltage value VX is from zero to the power voltage.
Specifically, the ideal voltage source is an ideal circuit element, and the terminal voltage of the ideal voltage source is a constant regardless of the magnitude of the current, which is determined by the load resistance. The current-voltage characteristic (also called the external characteristic) of an ideal voltage source is a straight line parallel to the I-axis. From an energy point of view, the ideal voltage source is a purely energy-supplying element, which supplies energy to the external circuit energy-consuming element R, and is an infinite-capacity power source.
As shown in fig. 6 to 7, the present invention provides an embodiment of a method for verifying the reliability of a start-up circuit of a bandgap reference circuit, where an ideal voltage source is added to a key node of the start-up circuit of the bandgap reference circuit, and the method includes the steps of:
performing direct current simulation verification on the ideal voltage source to obtain a simulation result; specifically, the dc simulation verification includes dc corner verification, dc Monte Carlo verification, and mismatch dc corner verification.
And judging whether the starting circuit works normally or not according to the simulation result.
In this embodiment, the method comprises the steps of:
and S100, performing direct current simulation verification on the ideal voltage source to obtain a simulation result. Specifically, S100 may be:
and S120, setting the PVT corner, and performing direct current corner verification on the ideal voltage source to obtain a simulation result.
S130, performing direct current Monte Carlo verification on the ideal voltage source to obtain a simulation result.
And S140, performing mismatch direct current corner verification on the ideal voltage source to obtain a simulation result.
And S200, judging whether the starting circuit works normally or not according to the simulation result.
Specifically, in the method of the present invention, one or two of the steps S120, S130, and S140 may be selected according to actual conditions to perform simulation verification, and all of the steps may be performed under the conditions supported by simulation time and simulation tools.
In the present embodiment, as shown in fig. 8, the dc Corner verification is a dc simulation verification performed in consideration of all possible Process corners (Process Corner), power supply voltage, and ambient temperature variation; as shown in fig. 9, the dc Monte Carlo verification is typically performed after random introduction of device mismatch. As shown in fig. 10, the verification ideas of fig. 8 and fig. 9 are combined, that is, the mismatch value of the threshold voltage VT of the critical MOS transistor (determined according to the magnitude of the influence of the MOS transistor mismatch on the circuit output) is manually calculated, the mismatch value is added to the gate of the MOS transistor in the form of a voltage source, and the mismatch dc corner verification is performed.
As shown in fig. 8, the dc simulation verification is dc corner verification, and dc simulation verification is performed on an ideal voltage source to obtain a simulation result, which specifically includes the steps of:
s121, adding an ideal voltage source to a key node of the starting circuit;
s122, setting simulation excitation;
s123, setting a PVT corner;
s124, performing direct current corner simulation;
and S125, obtaining a simulation result.
As shown in fig. 9, the dc simulation verification is dc Monte Carlo verification, and dc simulation verification is performed on an ideal voltage source to obtain a simulation result, which specifically includes the steps of:
s131, adding an ideal voltage source to a key node of the starting circuit;
s132, setting simulation excitation;
s133, carrying out direct current Monte Carlo simulation;
and S134, obtaining a simulation result.
In this embodiment, a verification concept of dc corner verification and dc Monte Carlo verification is combined, that is, a mismatch value of a threshold voltage VT of a critical MOS transistor (determined according to an influence of a mismatch of the MOS transistor on a circuit output) is calculated, the mismatch value is added to a gate of the MOS transistor in a voltage source form, a PVT corner is set, and the mismatch dc corner verification is performed.
As shown in fig. 10, the dc simulation verification is mismatch dc corner verification, and dc simulation verification is performed on an ideal voltage source to obtain a simulation result, which specifically includes the steps of:
s141, adding an ideal voltage source at a key node of the starting circuit;
s142, calculating a mismatch value of the threshold voltage VT of the key PMOS tube, and adding the mismatch value to the grid electrode of the MOS tube in a voltage source mode; with the mismatch value, the mismatch value is added to the gate of the MOS transistor, so that the dc curve of the mismatched dc verified current can be obtained (see fig. 11). Specifically, it is not necessary to do all the MOS transistors in the start-up circuit, and the selection of which MOS transistors to do these operations may be different according to different circuits. More specifically, the key node of the start-up circuit is generally the gate of the PMOS transistor of the core circuit, and the key nodes of different bandgap reference circuits are also different, and the specific circuit is specifically analyzed.
Specifically, the calculation formula of the mismatch value σ of the threshold voltage VT of the MOS transistor is as follows:
sigma is the mismatch value (one standard deviation) of the threshold voltage of the MOS tube, the unit is volt, W and L are respectively the gate width and the gate length of the MOS tube, AVTIs the original factory process constant of the MOS tube (provided by the manufacturer), and the physical meaning is the mismatch value of the turn-on voltages of two MOS tubes in unit area and A of the MOS tubes of different typesVTAre not the same. The sigma of each MOS tube can be calculated by the formula: the VT mismatch value of the first MOS tube is sigma1The VT mismatch value of the second MOS transistor is sigma2… the nth MOS transistor has VT mismatch value of sigman(n is a natural number).
Then, an ideal voltage source is added to the gate of each MOS transistor, as shown in FIG. 5, and the DC value is set to Kn*ΔVTnWherein Δ VTnTaking 3 standard deviations (corresponding to 99.7% coverage) or 6 standard deviations (corresponding to 99.9% coverage) as the deviation of the VT of the nth MOS tube; kn is a coefficient and is assigned as 1 or-1 during simulation. And finally, performing direct current corner verification, namely scanning VX from zero to VDD and performing direct current steady state analysis on the circuit.
S143, setting simulation excitation;
s144, setting a PVT corner;
s145, performing direct current corner simulation;
and S146, obtaining a simulation result.
After the simulation is finished, checking a direct current simulation result of IX: drawing an IX curve by taking the direct current voltage value VX as an abscissa and the direct current value IX as an ordinate; judging whether the starting circuit works normally according to the simulation result, and specifically comprising the following steps of:
s251, calculating the number of intersection points of the IX curves and the abscissa axis; that is, when IX is 0, the number of VX is counted.
S252, if the number of the intersection points of the IX curve and the abscissa axis is 1 (namely, there is only one intersection point), judging that the starting circuit can normally work;
and S253, if the number of the intersection points of the IX curve and the abscissa axis is 0 (namely, no intersection point) or more than 2 (namely, more than two intersection points), judging that the starting circuit cannot normally work.
As shown in fig. 11, several examples of the results of dc simulation verification are shown, in examples 1 and 2, IX has only one intersection a with the horizontal axis, and it can be determined that the start-up circuit can operate normally, and in example 3, there are two intersections B and C in addition to the intersection a, and it is obvious that there are three stable states, even if the transient simulation verification is finally stable in the normal state a, the chip may be stable in the wrong degenerate state B or C after being produced, and there is a great risk that the start-up circuit may operate normally, and in example 4, IX does not have an intersection with the horizontal axis, and the circuit cannot operate normally. The mismatch direct current corner verification method has more verification times, longer verification time, wide coverage rate and most sufficient verification. Since it takes into account the additive effects of process corner, supply voltage, temperature and device mismatch. In actual operation, one or more of the three verification methods can be selected according to the verification time, the verification tool and the verification requirement.
According to the invention, an ideal voltage source is added to a key node of a starting circuit of the bandgap reference circuit, and the direct current simulation is carried out by taking the direct current voltage value of the ideal voltage source as a scanning variable, so as to more fully verify whether the starting circuit works normally or not; the direct current simulation verification can more fully verify all possible stable states of the circuit; the circuit design is guided more pertinently, the production yield is improved, and the product risk is reduced.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (4)
1. A method for verifying the reliability of a starting circuit of a band-gap reference circuit is characterized in that an ideal voltage source is added to a key node of the starting circuit of the band-gap reference circuit, and comprises the following steps:
performing direct current simulation verification on the ideal voltage source to obtain a simulation result; the direct current simulation verification is mismatch direct current corner verification, and specifically comprises the following steps:
s141, adding the ideal voltage source to a key node of the starting circuit;
s142, calculating a mismatch value of the threshold voltage VT of the key MOS tube, and adding the mismatch value to the grid electrode of the MOS tube in a voltage source mode; the calculation formula of the mismatch value sigma of the threshold voltage VT of the MOS tube is as follows:
w and L are respectively the gate width and gate length of the MOS tube, AVTThe original factory process constant of the MOS tube is obtained;
s143, setting simulation excitation;
s144, setting a PVT corner;
s145, performing direct current corner simulation;
s146, obtaining the simulation result; the method specifically comprises the following steps:
scanning the direct current voltage value of the ideal voltage source, and recording the direct current value flowing through the ideal voltage source; the direct current voltage value of the ideal voltage source is a variable parameter VX, and the direct current value of the ideal voltage source is IX; the method specifically comprises the following steps:
taking the direct current voltage value VX as a parameter to perform direct current simulation scanning, and recording a direct current value IX flowing through the ideal voltage source; the scanning range of VX is from zero to the power supply voltage; drawing an IX curve by taking the direct current voltage value VX as an abscissa and the direct current value IX as an ordinate;
judging whether the starting circuit works normally according to the simulation result, and specifically comprising the following steps:
s251, calculating the number of intersection points of the IX curves and the abscissa axis;
s252, if the number of the intersection points of the IX curve and the abscissa axis is 1, judging that the starting circuit can normally work;
and S253, if the number of the intersection points of the IX curves and the abscissa axis is 0 or more than 2, judging that the starting circuit cannot normally work.
2. The method for verifying the reliability of the starting circuit according to claim 1, wherein the dc simulation verification is a dc corner verification, and the dc simulation verification of the ideal voltage source is performed to obtain a simulation result, specifically comprising the steps of:
s121, adding the ideal voltage source to a key node of the starting circuit;
s122, setting simulation excitation;
s123, setting a PVT corner;
s124, performing direct current corner simulation;
and S125, obtaining the simulation result.
3. The method for verifying the reliability of the starting circuit according to claim 1 or 2, wherein the dc simulation verification is a dc Monte Carlo verification, and the dc simulation verification of the ideal voltage source is performed to obtain a simulation result, specifically comprising the steps of:
s131, adding the ideal voltage source to a key node of the starting circuit;
s132, setting simulation excitation;
s133, carrying out direct current Monte Carlo simulation;
and S134, obtaining the simulation result.
4. A start-up circuit reliability verification method according to claim 1, characterized in that the simulation stimulus comprises a device model, a simulation type, a data type, a supply voltage, a temperature and/or a variable parameter assignment.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101706573A (en) * | 2009-07-06 | 2010-05-12 | 中国科学院长春光学精密机械与物理研究所 | Integration simulation test method of space optical remote sensor |
| CN101750580A (en) * | 2008-12-01 | 2010-06-23 | 豪雅微电子(苏州)有限公司 | Test method of functional module chip in integrated circuit |
| CN105487592A (en) * | 2016-01-21 | 2016-04-13 | 珠海格力电器股份有限公司 | CMOS (commentary metal-oxide-semiconductor) reference voltage source circuit and integrated circuit device |
| CN105699772A (en) * | 2016-01-20 | 2016-06-22 | 北京东方计量测试研究所 | Orthogonal reference phase verification method and device |
| CN105759888A (en) * | 2015-01-07 | 2016-07-13 | 德尔福技术有限公司 | Validation Circuit For Reference Voltage Shifted Data |
| CN109343653A (en) * | 2018-09-19 | 2019-02-15 | 安徽矽磊电子科技有限公司 | A kind of start-up circuit of bandgap voltage reference |
| CN109445508A (en) * | 2018-12-18 | 2019-03-08 | 深圳贝特莱电子科技股份有限公司 | A kind of band-gap reference circuit can produce starting Success Flag signal |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080183443A1 (en) * | 2007-01-31 | 2008-07-31 | David Goren | Statistical simulation of on chip interconnects |
-
2019
- 2019-07-04 CN CN201910597553.2A patent/CN110231557B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101750580A (en) * | 2008-12-01 | 2010-06-23 | 豪雅微电子(苏州)有限公司 | Test method of functional module chip in integrated circuit |
| CN101706573A (en) * | 2009-07-06 | 2010-05-12 | 中国科学院长春光学精密机械与物理研究所 | Integration simulation test method of space optical remote sensor |
| CN105759888A (en) * | 2015-01-07 | 2016-07-13 | 德尔福技术有限公司 | Validation Circuit For Reference Voltage Shifted Data |
| CN105699772A (en) * | 2016-01-20 | 2016-06-22 | 北京东方计量测试研究所 | Orthogonal reference phase verification method and device |
| CN105487592A (en) * | 2016-01-21 | 2016-04-13 | 珠海格力电器股份有限公司 | CMOS (commentary metal-oxide-semiconductor) reference voltage source circuit and integrated circuit device |
| CN109343653A (en) * | 2018-09-19 | 2019-02-15 | 安徽矽磊电子科技有限公司 | A kind of start-up circuit of bandgap voltage reference |
| CN109445508A (en) * | 2018-12-18 | 2019-03-08 | 深圳贝特莱电子科技股份有限公司 | A kind of band-gap reference circuit can produce starting Success Flag signal |
Non-Patent Citations (1)
| Title |
|---|
| 带隙电路的启动电路如何仿真？;silverpuma等;《bbs.eetop.cn/thread-248711-2-1.html》;20120513;1-2 * |
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