JP3605905B2 - Delay capacitor withstand voltage check method and semiconductor integrated circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for checking the withstand voltage of a delay capacitor and a semiconductor integrated circuit, and more particularly to a circuit that compares a voltage delayed by the delay capacitor with a reference voltage and outputs an output signal according to the magnitude relationship. The present invention relates to a method for checking the withstand voltage of a delay capacitor used when checking the withstand voltage of a delay capacitor and a semiconductor integrated circuit.
[0002]
[Prior art]
A system reset circuit that generates a reset signal that instructs the system to reset when power is turned on is configured to output a reset signal after a delay from when the voltage is applied until the applied voltage stabilizes. ing.
[0003]
FIG. 5 shows a circuit configuration diagram of a conventional system reset circuit. A conventional system reset circuit 1 includes a constant current source 2a, a Zener diode D1, a reference voltage generation source 2 for generating a reference voltage V _REF , and resistors R1 and R2, and a voltage divider for dividing an input voltage V _CC. The circuit 3 compares the reference voltage V _REF generated by the reference voltage generation source 2 with the _divided voltage V _DIV obtained by dividing the input voltage V _CC by the voltage dividing circuit 3, and determines the _divided voltage V _DIV as the reference voltage. A comparator 4 that outputs an output signal that goes high when it is lower than V _REF and goes low when the _divided voltage V _DIV is higher than the reference voltage V _REF, and a constant current source 5 that generates a constant current from the input voltage V _CC. And a delay capacitor C charged by the current supplied from the constant current source 5 and an NPN transistor, and are turned on when the output signal of the comparator 4 is at a high level. The charge control transistor Q1 that discharges the delay capacitor C and turns off when the output signal of the comparator 4 is at a low level to make the delay capacitor C chargeable, the charge potential of the delay capacitor C, and a reference voltage generation source 2 is compared with the reference voltage V _REF generated at step 2, and when the charging potential of the delay capacitor C is lower than the reference voltage V _REF , the level is low, and when the charging potential of the delay capacitor C is higher than the reference voltage V _{REF, the} level is high. An output transistor Q2, a delay capacitor, which is turned on when the output signal of the comparator 6 is at a high level, and is turned off when the output signal of the comparator 6 is at a low level. C is connected to the connection point between C and the constant current source 5 and has a withstand voltage of the delay capacitor C. Composed than the withstand voltage check pad 7 to check.
[0004]
To increase the delay time, it is necessary to reduce the charging current and increase the capacitance of the capacitor, and the leakage current of the delay capacitor greatly changes the delay time. become.
In order to check the withstand voltage of the delay capacitor C in the circuit of FIG. 5, the withstand voltage of the delay capacitor C is checked by applying a voltage to the withstand voltage check pad 7 and directly applying a voltage to the delay capacitor C. Had gone.
[0005]
[Problems to be solved by the invention]
However, in the conventional method for checking a delay capacitor, a voltage for checking a withstand voltage is directly supplied to the delay capacitor to check a leak current and the like. The pad is directly connected to the delay capacitor, and it becomes important to control the leakage current from the pad. However, since the pads need to be exposed on the surface of the chip, there has been a problem that the pads are susceptible to moisture absorption from the package after packaging and a leak current is likely to occur.
[0006]
The present invention has been made in view of the above points, and an object of the present invention is to provide a method of checking a withstand voltage of a delay capacitor and a semiconductor integrated circuit capable of checking a withstand voltage while realizing an accurate delay time.
[0007]
[Means for Solving the Problems]
According to the first aspect of the present invention, a current generating circuit to which an input voltage is applied and outputs a current according to the input voltage, and a charging voltage which is charged by the current generated by the current generating circuit and delays the input voltage is generated. A delay capacitor, and a charging voltage of the delay capacitor are supplied to a first input terminal, a reference voltage is supplied to a second input terminal, and the output signal is inverted according to a magnitude relationship between the charging voltage and the reference voltage. in the delay capacitor check method of a circuit having a comparator for outputting, the circuit has a breakdown voltage check pads for connecting said second input terminal of the comparator to an external circuit, checking the breakdown voltage of the delay capacitor to time to, a voltage corresponding to the breakdown voltage the voltage of the delay capacitor in a pressure check pad while supplying from outside, or by applying the input voltage to the current generating circuit Measuring the delay time for the output signal of the comparator is inverted, and wherein checking the breakdown voltage of the delay capacitor according to the delay time.
[0008]
According to the first aspect, a voltage corresponding to the withstand voltage of the delay capacitor is supplied to the second input terminal of the comparator, and the charged potential of the delay capacitor becomes a voltage corresponding to the withstand voltage of the delay capacitor. , The delay time is measured, and the presence or absence of leakage current can be checked based on the measured delay time. That is, if there is a leakage current in the capacitor, the time until the capacitor is charged becomes long. Therefore, the leakage current of the capacitor can be detected by detecting the delay time of the capacitor. At this time, by setting the voltage supplied to the second input terminal of the comparator to be high, the delay time of the capacitor is lengthened, the influence of the leak current of the capacitor is increased, and the leak current can be easily detected. Therefore, according to the first aspect, by setting the voltage supplied to the second input terminal of the comparator high when checking the withstand voltage of the capacitor, the withstand voltage of the capacitor can be checked without providing a pad directly connected to the capacitor. Therefore, even if a leak current occurs in the pad during use, the delay capacitor is not affected by the leak current, and the delay time does not change.
[0009]
A current generating circuit to which an input voltage is applied and generates a current according to the input voltage, and a delay capacitor which is charged by the current generated by the current generating circuit and generates a charging voltage delayed from the input voltage And the charging voltage of the delay capacitor is supplied to the first input terminal, the reference voltage is supplied to the second input terminal, and an output signal that is inverted according to the magnitude relationship between the charging voltage and the reference voltage is output. In a semiconductor integrated circuit having a comparator, the semiconductor integrated circuit includes a withstand voltage check pad that is connected to the second input terminal of the comparator and supplies a voltage corresponding to the withstand voltage of the delay capacitor when checking the withstand voltage of the delay capacitor. .
[0010]
According to the second aspect, by providing a check pad at the second input terminal of the comparator, the leak current of the delay capacitor can be checked by the method of the first aspect, and the pad is not directly connected to the capacitor. Therefore, even if a leak current is generated in the pad after checking the withstand voltage of the capacitor, the operation of the capacitor can be operated with a normal delay time without directly affecting the charging of the capacitor.
[0011]
Claim 3 is a constant voltage generating circuit provided between a withstand voltage check pad and the second input terminal of the comparator and configured to generate a constant voltage.
Amplifying a constant voltage generated by the constant voltage generating circuit to generate the reference voltage to be supplied to the second input terminal of the comparator.
[0012]
According to the third aspect, since the voltage is supplied to the second input terminal of the comparator after being amplified by the amplifier circuit, the voltage supplied to the second input terminal of the comparator can be increased.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, an embodiment of the present invention will be described with reference to the drawings. In this embodiment, a method of checking the withstand voltage of the delay capacitor of the system reset circuit will be described.
FIG. 1 shows a circuit configuration diagram of an embodiment of the present invention. The semiconductor integrated circuit 11 according to the present embodiment includes a reference voltage generation source 12 that generates a reference voltage V _REF , a voltage division circuit 13 that divides a supply voltage V _CC , and a reference voltage V _REF generated by the reference voltage generation source 12. The divided voltage V _DIV obtained by dividing the input voltage V _CC by the voltage circuit 13 is compared with the _divided voltage V _{DIV. When the divided} voltage V _DIV is smaller than the reference voltage V _{REF, the} voltage becomes a high level, and the _divided voltage V _DIV becomes the reference voltage. A comparator 14 that outputs an output signal that goes low when it is larger than V _REF, a constant current source 15 that generates a constant current from the input voltage V _CC, and a delay capacitor C that is charged by a current supplied from the constant current source 15 , NPN transistor, and turns on when the output signal of the comparator 14 is at a high level to discharge the delay capacitor C. The charge control transistor Q11 which turns off when the bell is turned to make the delay capacitor C chargeable, compares the charge potential of the delay capacitor C with the reference voltage V _REF generated by the reference voltage source 12, becomes low level when the charge potential of the use capacitor C is smaller than the reference voltage V _REF, the result from the comparator 16, NPN transistor that outputs an output signal which becomes high level when the charge potential of the delay capacitor C is greater than the reference voltage V _REF, The output transistor Q12, which is turned on when the output signal of the comparator 16 is at a high level and turned off when the output signal of the comparator 16 is at a low level, checks the withstand voltage of the delay capacitor C at the reference voltage input terminal of the comparator 16. It consists of a withstand voltage check pad 17 that supplies It is.
[0014]
The reference voltage source 12 has a configuration in which a constant current source 18 and a Zener diode D11 are connected in series, and connected between a terminal T1 to which the input voltage V _CC is supplied and a ground terminal T _GND. A reference voltage V _REF is output from a connection point with D11. Voltage dividing circuit 13 includes resistors R11, the R12 connected in series, is a terminal T1 and configuration connected between the ground terminal _{T GND,} the poured voltage _{V CC} dividing the divided voltage _{V DIV} and the resistor R11 resistor R12 Output from the connection point with
[0015]
The non-inverting terminal of the comparator 14 is supplied with the reference voltage V _REF from the reference voltage source 12, and the inverting terminal of the comparator 14 is supplied with the _divided voltage V _{DIV obtained} by dividing the input voltage V _CC from the voltage dividing circuit 13. Is done. The comparator 14 compares the reference voltage V _REF supplied from the reference voltage source 12 with the divided voltage V _DIV supplied from the voltage dividing circuit 13, and when the _divided voltage V _DIV is smaller than the reference voltage V _REF , When the low level and the _divided voltage V _DIV are higher than the reference voltage V _REF , an output that becomes a high level is generated and supplied to the base of the discharge control transistor Q11.
[0016]
On the other hand, one end of the delay capacitor C is connected to the ground terminal T _GND , and the other end is connected to the input voltage supply terminal T 1 via the constant current source 15. The connection point between the delay capacitor C and the constant current source 15 is connected to the inverting terminal of the comparator 16 and to the collector of the discharge control transistor Q11.
[0017]
The discharge control transistor Q11 has an emitter connected to the ground terminal T _GND . When the output signal of the comparator 14 is at a high level, that is, when the input voltage V _CC is lower than the reference voltage V _REF , the discharge control transistor Q11 is turned on to discharge the delay capacitor C, and the output signal of the comparator 14 is at a low level. That is, when the input voltage V _CC is higher than the reference voltage V _REF, it is turned off and the delay capacitor C can be charged. Delay capacitor C, at the time charged voltage _{V CC} is turned on, when the divided voltage _{V DIV} of the input voltage _{V CC} is less than the reference voltage _{V REF} is discharged by the discharge control transistors Q11, the divided voltage V of the input voltage _{V CC When the DIV} becomes larger than the reference voltage V _REF , the charging is performed by the constant current source 15 and the charging potential V _CHARG is gradually increased.
[0018]
The reference voltage V _REF is supplied to the non-inverting terminal of the comparator 16 from the reference voltage source 18. The comparator 16 compares the reference voltage V _REF with the charging potential V _CHARG of the delay capacitor C, and when C of the charging potential _{V CHARG} is less than the reference voltage _{V REF} is at a high level, the charging potential _{V CHARG} delay capacitor C is greater than the reference voltage _{V REF} outputs an output signal at a low level, the output transistor Supply to the base of Q12.
[0019]
The output transistor Q12 is formed of an NPN transistor, has a collector connected to the output terminal _TOUT , and has an emitter connected to the ground terminal _TGND , which constitutes a so-called open collector output. In the output transistor Q12, the discharge control transistor Q11 is turned off after the output of the comparator 16 is at a high level, that is, the input voltage _VCC is applied, and the charging of the delay capacitor C is started by the constant current source 15, so that the delay capacitor C is in the state of not being fully charged, turned on to hold the output terminal T _OUT to low level. In addition, the output transistor Q12 turns off the discharge control transistor Q11 after the output of the comparator 16 is at a low level, that is, the input voltage _VCC is applied, and the constant current source 15 starts charging the delay capacitor C, thereby delaying the output transistor Q12. use capacitor C is fully charged, when the charge potential _{V CHARG} delay capacitor C is greater than the reference voltage _{V REF} is turned off, the output terminal _{T OU T} to the high level.
[0020]
The withstand voltage check pad 17 is connected to the connection point between the reference voltage source 12 and the non-inverting terminal of the comparator 16. When checking the withstand voltage of the delay capacitor C, a voltage is applied from a tester. _Is twice the reference voltage V _REF .
[0021]
Here, the normal operation of the system reset circuit 1 will be described.
FIG. 2 is an operation waveform diagram at the time of reset operation according to one embodiment of the present invention. 2A shows the waveform of the applied voltage V _CC , FIG. 2B shows the waveform of the reference voltage V _REF , the broken line _shows the waveform of the charging potential V _CHARG , and _{FIG. 2C shows} the waveform of the output voltage V _OUT .
[0022]
When the input voltage V _CC increases and the _divided voltage V _DIV becomes larger than the reference voltage V _REF at time t1, charging of the delay capacitor C from the constant current source 15 is started. Charging of the delay capacitor C is started, and when the charging potential V _CHARG becomes higher than the reference voltage V _REF at time t2, the output voltage V _CC goes high. In other words, charged voltage V _CC is a predetermined delay time T0 elapses after the output voltage V _OUT which is determined by the time constant of the delay capacitor C from being charged with a predetermined voltage at time t1 is set to the high level.
[0023]
Next, the operation of the system reset circuit 1 when checking the withstand voltage of the delay capacitor C will be described.
FIG. 3 is an explanatory diagram of the operation at the time of the withstand voltage check of one embodiment of the present invention. 3A shows the waveform of the applied voltage V _CC , FIG. 3B shows the waveform of the reference voltage V _REF , the broken line _shows the waveform of the charging potential V _CHARG , and _{FIG. 3C shows} the waveform of the output voltage V _OUT .
[0024]
The withstand voltage check of the delay capacitor C is performed in a state of the chip before packaging. The withstand voltage check pad 17 is formed so as to be exposed on the chip surface in the state of the chip, and the electrode of the tester is in contact with the withstand voltage check. The withstand voltage check pad 17 is supplied with, for example, a check voltage 2V _REF twice the reference voltage V _REF from the tester at the time of the withstand voltage check.
[0025]
At the time of the withstand voltage check, the input voltage _VCC is increased at time t3, the divided voltage _VDIV is made larger than the reference voltage _VREF at time t3, and charging of the delay capacitor C from the constant current source 15 is started. Without leakage current delay capacitor C, the charge potential _{V CHARG} at time t4 as shown in FIG. 3 (B) becomes larger than the reference voltage _{V REF,} the output voltage _{V CC} becomes a high level.
[0026]
However, if there is a leakage current in the delay capacitor C, it takes time for the charging potential V _CHARG to _{reach the} withstand voltage check voltage 2V _REF . For example, the output voltage V _OUT goes high at time t5 longer than time t4, or If the leakage current is large, the charging potential V _CHARG does not reach the withstand voltage check voltage 2V _REF and the output voltage V _OUT is fixed at a low level. Therefore, the leak current of the delay capacitor C can be detected by measuring the time from when the input voltage V _CC is applied to when the output voltage V _OUT becomes high level by the tester.
[0027]
As described above, since the leak current of the delay capacitor C can be detected without directly supplying a voltage to the delay capacitor C, there is no need to provide a pad directly connected to the delay capacitor C. Are not affected by the leak current of the pad. At this time, since the withstand voltage check voltage 2V _REF is sufficiently higher than the reference voltage V _REF , even a slight leak current can be detected.
[0028]
FIG. 4 shows a circuit diagram of another embodiment of the present invention. In the figure, the same components as those of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.
In the present embodiment, an amplifier circuit 21 is connected between a connection point between the withstand voltage check pad 17 and the reference voltage source 12 and an inverting input terminal of the comparator 16. The amplifying circuit 21 includes a constant current source 22, PNP transistors Q13, Q15, and Q16, an NPN transistor Q14, and resistors R13 and R14, amplifies the reference voltage V _REF by a factor of two, and supplies the reference voltage V _REF to an inverting input terminal of the comparator 16. At the same time, the withstand voltage check voltage supplied to the withstand voltage check pad 17 is doubled and supplied to the inverting input terminal of the comparator 16.
[0029]
Therefore, if the withstand voltage check voltage supplied to the withstand voltage check pad 17 is set to 2 V _REF , 4 V _REF can be supplied to the inverting input terminal of the comparator 16. Therefore, the voltage supplied to the inverting input terminal of the comparator 16 can be made higher.
[0030]
【The invention's effect】
As described above, according to the first aspect of the present invention, by setting the voltage supplied to the second input terminal of the comparator high at the time of checking the withstand voltage of the capacitor, the capacitor directly connected to the capacitor is not provided. Since the withstand voltage can be checked, even if a leak current occurs in the pad during use, the delay capacitor is not affected by the leak current, and the delay time is not disturbed.
[0031]
According to the second aspect, by providing a check pad at the second input terminal of the comparator, the leak current of the delay capacitor can be checked by the method of the first aspect, and the pad is not directly connected to the capacitor. Therefore, even if a leak current occurs in the pad after checking the withstand voltage of the capacitor, the effect of the leak current does not directly affect the charging of the capacitor, and the device can be operated with a normal delay time.
[0032]
According to the third aspect, since the voltage is supplied to the second input terminal of the comparator after being amplified by the amplifier circuit, the voltage supplied to the second input terminal of the comparator can be increased.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an embodiment of the present invention.
FIG. 2 is an operation waveform diagram at the time of normal operation of one embodiment of the present invention.
FIG. 3 is an operation waveform diagram at the time of a withstand voltage check according to one embodiment of the present invention.
FIG. 4 is a circuit configuration diagram of another embodiment of the present invention.
FIG. 5 is a circuit configuration diagram of a conventional example.
[Explanation of symbols]
11, 20 System reset circuit 12 Reference voltage generating source 13 Voltage dividing circuit 14, 16 Comparator 15 Constant current source 17 Breakdown voltage checking pad 21 Amplifying circuit

Claims (3)

Input voltage is applied, a current generating circuit for outputting a current in response to the input voltage, is charged by a current generated by said current generating circuit, a delay capacitor for generating a charging voltage obtained by delaying the said input voltage , the charging voltage of the capacitor for the delay is supplied to the first input terminal, a reference voltage is supplied to the second input terminal, an output signal which inverts in accordance with the magnitude relationship between the charge voltage and the reference voltage in the delay capacitor check method of a circuit having a comparator for,
The circuit has a withstand voltage check pad for connecting the second input terminal of the comparator to an external circuit,
When checking the withstand voltage of the delay capacitor, the input voltage is applied to the current generating circuit while a voltage corresponding to the withstand voltage of the delay capacitor is externally supplied to the withstand voltage check pad. A method for checking the withstand voltage of a delay capacitor, comprising measuring a delay time until an output signal of the comparator is inverted, and checking a withstand voltage of the delay capacitor according to the delay time. An input voltage is applied, a current generation circuit that generates a current according to the input voltage, a delay capacitor that is charged by the current generated by the current generation circuit and generates a charging voltage that is a delay of the input voltage , charging voltage of the capacitor for the delay is supplied to the first input terminal, a reference voltage is supplied to the second input terminal, and outputs an output signal which inverts in accordance with the magnitude relationship between the charge voltage and the reference voltage In a semiconductor integrated circuit having a comparator,
A semiconductor integrated circuit, comprising: a withstand voltage check pad connected to the second input terminal of the comparator and supplying a voltage corresponding to the withstand voltage of the delay capacitor when checking the withstand voltage of the delay capacitor. A constant voltage generation circuit that is provided between the withstand voltage check pad and the second input terminal of the comparator and generates a constant voltage;
3. The semiconductor integrated circuit according to claim 2, further comprising: an amplifier circuit for amplifying a constant voltage generated by said constant voltage generation circuit to generate said reference voltage to be supplied to said second input terminal of said comparator. circuit.

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