JPS60103934U - Charge transfer type signal converter - Google Patents
Charge transfer type signal converterInfo
- Publication number
- JPS60103934U JPS60103934U JP15416684U JP15416684U JPS60103934U JP S60103934 U JPS60103934 U JP S60103934U JP 15416684 U JP15416684 U JP 15416684U JP 15416684 U JP15416684 U JP 15416684U JP S60103934 U JPS60103934 U JP S60103934U
- Authority
- JP
- Japan
- Prior art keywords
- charge transfer
- elements
- arithmetic
- delay
- type signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Filters That Use Time-Delay Elements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は電荷転送型コサイン変換装置の動作原理を説明
するための回路系統図、第２図は本考案を適用したコサ
イン変換装置の一実施例構成を示す回路系統図である。
１：入力端子、２：アナログシフトレジスタ、３：フィ
ルタ群、４：出力側アナログスイッチ、Ｓｏ、Ｓｌ、Ｓ
２．Ｓ３．・・・・・・：入力側アナログスイッチ、５
：出力端子、Ｌ□、Ｌ２．Ｌ、３．・・・・・・ＬＮ−
ｔ：遅延用ＣＴＤ０FIG. 1 is a circuit system diagram for explaining the operating principle of a charge transfer type cosine conversion device, and FIG. 2 is a circuit system diagram showing the configuration of an embodiment of a cosine conversion device to which the present invention is applied. 1: Input terminal, 2: Analog shift register, 3: Filter group, 4: Output side analog switch, So, Sl, S
2. S3. ......: Input side analog switch, 5
: Output terminal, L□, L2. L, 3.・・・・・・LN-
t: CTD0 for delay
Claims (1)
機能を有する複数系統の演算用電荷転送素子を平行に配
設して演算部を構成し、かつ前記各演算用電荷転送素子
の入力側に変換すべき入力信号を所定の時間差をもって
並列に供給するためのアナログ遅延素子を接続してなる
構成において、上記アナログ遅延素子が、上記演算用電
荷転送素子対応に接続された互いに転送段数の異なる遅
延用電荷転送素子からなり、かつ該遅延用電荷転送素子
と演算用電荷転送素子の電荷の転送方法が同一になるよ
う配設されていることを特徴とする電荷転送型信号変換
装置。A plurality of systems of arithmetic charge transfer elements, each having a weighting coefficient imparting means and functioning as a filter, are arranged in parallel to constitute an arithmetic section, and the arithmetic charge transfer elements should be converted to the input side of each arithmetic charge transfer element. In a configuration in which analog delay elements are connected for supplying input signals in parallel with a predetermined time difference, the analog delay elements are connected to correspond to the charge transfer elements for calculation and have different numbers of transfer stages for delay charge transfer. What is claimed is: 1. A charge transfer type signal conversion device comprising a delay charge transfer device and a calculation charge transfer device arranged so that the charge transfer method is the same between the delay charge transfer device and the calculation charge transfer device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15416684U JPS60103934U (en) | 1984-10-11 | 1984-10-11 | Charge transfer type signal converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15416684U JPS60103934U (en) | 1984-10-11 | 1984-10-11 | Charge transfer type signal converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60103934U true JPS60103934U (en) | 1985-07-16 |
Family
ID=30340869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15416684U Pending JPS60103934U (en) | 1984-10-11 | 1984-10-11 | Charge transfer type signal converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60103934U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4999453A (en) * | 1973-01-02 | 1974-09-19 |
-
1984
- 1984-10-11 JP JP15416684U patent/JPS60103934U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4999453A (en) * | 1973-01-02 | 1974-09-19 |
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