JPS61601U - Analog signal calculation circuit - Google Patents

Analog signal calculation circuit

Info

Publication number
JPS61601U
JPS61601U JP8263784U JP8263784U JPS61601U JP S61601 U JPS61601 U JP S61601U JP 8263784 U JP8263784 U JP 8263784U JP 8263784 U JP8263784 U JP 8263784U JP S61601 U JPS61601 U JP S61601U
Authority
JP
Japan
Prior art keywords
analog signal
analog
arithmetic
value
calculation circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8263784U
Other languages
Japanese (ja)
Other versions
JPH0418003Y2 (en
Inventor
明彦 大野
元男 野上
弘毅 辻
拓也 篠田
Original Assignee
横河電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 横河電機株式会社 filed Critical 横河電機株式会社
Priority to JP8263784U priority Critical patent/JPS61601U/en
Publication of JPS61601U publication Critical patent/JPS61601U/en
Application granted granted Critical
Publication of JPH0418003Y2 publication Critical patent/JPH0418003Y2/ja
Granted legal-status Critical Current

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  • Safety Devices In Control Systems (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案第一実施例装置の構成を示すブロック構
成図。 第2図は本考案第二実施例装置の構成を示すブロック構
成図。 第3図は本考案第三実施例装置の構成を示すブロック構
成図。 1・・・演算手段、2・・・異常検出手段、3・・・切
換手段ミ10・・・平均値演算回路、11・・・最大値
演算回路、12・・・最小値演算回路、31〜35・・
・切換器、36・・・切換器操作回路、41〜44・・
・アナ口グ信号入力端子、45・・・アナログ信号出力
端子、51〜54・・・検出端、151〜154・・・
入力変換器リ
FIG. 1 is a block diagram showing the configuration of a device according to a first embodiment of the present invention. FIG. 2 is a block configuration diagram showing the configuration of an apparatus according to a second embodiment of the present invention. FIG. 3 is a block configuration diagram showing the configuration of an apparatus according to a third embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Calculating means, 2... Abnormality detection means, 3... Switching means Mi10... Average value computing circuit, 11... Maximum value computing circuit, 12... Minimum value computing circuit, 31 ~35...
・Switcher, 36...Switcher operation circuit, 41-44...
- Analog signal input terminal, 45...Analog signal output terminal, 51-54...Detection end, 151-154...
Input converter

Claims (1)

【実用新案登録請求の範囲】 (1)多数のアナログ信号入力端子と、 そのアナログ信号の統計値を表すアナログ信号を送出す
る演算手段と を備えたアナログ手段の演算回路において、上記多数の
アナログ信号の各々についてその異常を検出する手段と
、 上記多数のアナログ信号の各々について設けられ、上記
検出する手段の対応する検出出力により制御され、上記
演算手段の入力を上記入力端子のアナログ信号から上記
演算手段の出力のアナPグ信号に切換える切換回路と を備えたことを特徴とするアナログ信号の演算回路。 (2)統計値が平均値である実用新案登録請求の範囲第
(1)項に記載のアナログ信号の演算回路。 {3}統計値が最大値である実用新案登録請求の範囲第
(1)項に記載のアナログ信号の演算回路。 (4)統計値が最小値である実用新案登録請求の範囲第
(1)項に記載のアナログ信号の演算回路。
[Claims for Utility Model Registration] (1) In an arithmetic circuit of analog means comprising a large number of analog signal input terminals and an arithmetic means for sending out analog signals representing statistical values of the analog signals, means for detecting an abnormality for each of the plurality of analog signals, and controlled by the corresponding detection output of the detecting means, the input of the arithmetic means is controlled from the analog signal of the input terminal to perform the arithmetic operation. An analog signal arithmetic circuit comprising: a switching circuit for switching the output of the means to an analog Pg signal. (2) The analog signal arithmetic circuit according to claim (1), wherein the statistical value is an average value. {3} The analog signal calculation circuit according to claim (1) of the utility model registration, wherein the statistical value is the maximum value. (4) The analog signal arithmetic circuit according to claim (1), wherein the statistical value is the minimum value.
JP8263784U 1984-06-04 1984-06-04 Analog signal calculation circuit Granted JPS61601U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8263784U JPS61601U (en) 1984-06-04 1984-06-04 Analog signal calculation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8263784U JPS61601U (en) 1984-06-04 1984-06-04 Analog signal calculation circuit

Publications (2)

Publication Number Publication Date
JPS61601U true JPS61601U (en) 1986-01-06
JPH0418003Y2 JPH0418003Y2 (en) 1992-04-22

Family

ID=30630531

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8263784U Granted JPS61601U (en) 1984-06-04 1984-06-04 Analog signal calculation circuit

Country Status (1)

Country Link
JP (1) JPS61601U (en)

Also Published As

Publication number Publication date
JPH0418003Y2 (en) 1992-04-22

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