JPH0418003Y2 - - Google Patents
Info
- Publication number
- JPH0418003Y2 JPH0418003Y2 JP8263784U JP8263784U JPH0418003Y2 JP H0418003 Y2 JPH0418003 Y2 JP H0418003Y2 JP 8263784 U JP8263784 U JP 8263784U JP 8263784 U JP8263784 U JP 8263784U JP H0418003 Y2 JPH0418003 Y2 JP H0418003Y2
- Authority
- JP
- Japan
- Prior art keywords
- output
- analog signal
- minimum value
- terminal
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 35
- 230000005856 abnormality Effects 0.000 claims description 22
- 230000002159 abnormal effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000004886 process control Methods 0.000 description 2
- 238000012369 In process control Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010965 in-process control Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
Landscapes
- Feedback Control In General (AREA)
- Safety Devices In Control Systems (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案はプロセス制御の分野に利用される。特
に、複数個のアナログプロセス量の最大値および
最小値を演算する回路に関する分野に利用され
る。[Detailed description of the invention] [Industrial application field] The invention is used in the field of process control. In particular, it is used in the field of circuits that calculate the maximum and minimum values of a plurality of analog process quantities.
加熱装置などの熱源のように同種の制御対象が
分布する装置には、複数個のセンサが設置され、
このセンサの測定値の最大値および最小値に基づ
いてこの装置の管理が行われることが多い。とこ
ろで、故障したセンサに接続される入力変換器か
らは、変換器の有するバーンアウト機能により統
一電気信号の最大値または最小値が出力されるの
で、演算された最大値および最小値が実際のそれ
ぞれの値と異なる値になる現象が起きる。
Multiple sensors are installed in devices where the same type of control targets are distributed, such as heat sources such as heating devices.
This device is often managed based on the maximum and minimum values of the measured values of this sensor. By the way, since the input converter connected to the failed sensor outputs the maximum or minimum value of the unified electrical signal due to the converter's burnout function, the calculated maximum and minimum values may not be the actual values. A phenomenon occurs where the value differs from the value of .
従来例演算回路では、この現象を回避するため
に、故障センサに接続される入力変換器がこの演
算回路から切離され、またこの切離しに伴う演算
回路の再構築が行われるので、回路が複雑になる
欠点があつた。 In conventional arithmetic circuits, in order to avoid this phenomenon, the input converter connected to the faulty sensor is disconnected from the arithmetic circuit, and the arithmetic circuit is reconfigured as a result of this disconnection, making the circuit complicated. It had some drawbacks.
本考案は、前述の欠点を除去するもので、複数
個のセンサによるアナログ測定が行われるプロセ
スでセンサ故障があつた場合に、アナログ測定量
の最大値および最小値の演算が、演算回路に簡単
な手段を付加することによりそのプロセスの制御
に支障を与えない精度で実行される回路を提供す
ることを目的とする。
The present invention eliminates the above-mentioned drawbacks, and in the event of a sensor failure in the process of analog measurement using multiple sensors, calculation of the maximum and minimum values of the analog measured quantity can be easily performed using the calculation circuit. The purpose of the present invention is to provide a circuit that can be executed with precision that does not interfere with the control of the process by adding such means.
本考案は、多数のアナログ信号入力端子と、そ
のアナログ信号の最大値または最小値を求めて出
力する演算手段と、上記多数のアナログ信号の
各々についてその異常を検出する手段と、この検
出する手段の異常検出出力により上記アナログ信
号入力端子の上記演算手段への入力を切り換える
切換手段とを備え、上記演算手段は、最大値およ
び最小値をそれぞれ演算する手段を含み、上記切
換手段は、上記検出する手段の異常検出出力によ
り、上記演算手段の出力が最大値である場合には
上記演算手段が演算した最小値出力を、上記演算
手段の出力が最小値である場合には上記演算手段
が演算した最大値出力を異常が検出された上記入
力端子のアナログ信号に代えて上記演算手段の入
力にそれぞれ与える切換回路を含むことを特徴と
する。
The present invention includes a large number of analog signal input terminals, a calculation means for determining and outputting the maximum or minimum value of the analog signals, a means for detecting an abnormality in each of the large number of analog signals, and a means for detecting the abnormality. switching means for switching the input of the analog signal input terminal to the calculation means based on the abnormality detection output of Based on the abnormality detection output of the means for calculating, if the output of the calculation means is the maximum value, the calculation means calculates the minimum value output, and if the output of the calculation means is the minimum value, the calculation means calculates the minimum value output. The present invention is characterized in that it includes a switching circuit that supplies the maximum value output to the inputs of the calculation means in place of the analog signal of the input terminal in which the abnormality has been detected.
異常検出手段で検知された異常アナログ信号の
代りに、演算手段の出力が演算手段に入力され
る。
Instead of the abnormal analog signal detected by the abnormality detection means, the output of the calculation means is input to the calculation means.
演算手段の出力が最大値であるときは、この演
算手段が有する最小値演算回路の出力が異常アナ
ログ手段に代りこの演算手段が有する最大値演算
回路に入力され、演算手段からは正常アナログ信
号の最大値が出力される。 When the output of the calculation means is the maximum value, the output of the minimum value calculation circuit of this calculation means is input to the maximum value calculation circuit of this calculation means instead of the abnormal analog means, and the output of the normal analog signal is input from the calculation means to the maximum value calculation circuit of this calculation means. The maximum value is output.
また、演算手段の出力が最小値であるときは、
この演算手段が有する最大値演算回路の出力が異
常アナログ手段に代りこの演算手段が有する最小
値演算回路に入力され、演算手段からは正常アナ
ログ信号の最小値が出力される。 Also, when the output of the calculation means is the minimum value,
The output of the maximum value calculation circuit of this calculation means is input to the minimum value calculation circuit of this calculation means instead of the abnormal analog means, and the minimum value of the normal analog signal is output from the calculation means.
以下、本考案実施例装置を図面に基づいて説明
する。第１図は、本考案第一実施例装置の構成を
示すブロツク構成図であり、第２図は、本考案第
二実施例装置の構成を示すブロツク構成図であ
る。
Hereinafter, an embodiment of the present invention will be explained based on the drawings. FIG. 1 is a block diagram showing the configuration of the apparatus according to the first embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of the apparatus according to the second embodiment of the present invention.
この第一実施例装置は多数のアナログ入力の最
大値を、第二実施例装置はその最小値を演算して
出力する装置である。 The device of the first embodiment calculates and outputs the maximum value of a large number of analog inputs, and the device of the second embodiment calculates and outputs the minimum value thereof.
まず、この第一実施例装置の構成を第１図に基
づき説明する。 First, the configuration of the apparatus of the first embodiment will be explained based on FIG.
演算手段１は最大値演算回路１１と、最小値演
算回路１２を備える。そして、実施例装置１０２
は、演算手段１と、異常検出手段２と、切換手段
３と、第一ないし第四のアナログ信号入力端子４
１〜４４と、アナログ信号出力端子４５とを備え
る。ここで、切換手段３は第一ないし第五の切換
器３４〜３５と切換器操作回路３６とを備える。
検出端５１の出力は入力変換器１５１を経由し第
一アナログ信号入力端子４１に接続され、第一の
アナログ信号入力端子４１は第一の切換器３１の
第一の被切換端子に接続される。第一の切換器３
１の共通端子は最大値演算回路１１および最小値
演算回路１２の第一の入力に接続される。検出端
５２の出力は入力変換器１５２を経由し第二アナ
ログ信号入力端子４２に接続される。第二のアナ
ログ信号入力端子４２は第二の切換器３２の第一
の被切換端子に接続され、第二の切換器３２の共
通端子は最大値演算回路１１および最小値演算回
路１２の第二の入力に接続される。検出端５３の
出力は入力変換器１５３を経由し第三のアナログ
信号入力端子４３に接続される。第三のアナログ
信号入力端子４３は第三の切換器３３の第一の被
切換端子に接続される。第三の切換器３３の共通
端子は最大値演算回路１１および最小値演算回路
１２の第三の入力に接続される。検出端５４の出
力は入力変換器１５４を経由して第四アナログ信
号入力端子５４に接続される。第四のアナログ信
号入力端子５４は第四の切換器３４の第一の被切
換端子に接続される。第四の切換器３４の共通端
子は最大値演算回路１１および最小値演算回路１
２の第四の入力に接続される。 The calculation means 1 includes a maximum value calculation circuit 11 and a minimum value calculation circuit 12. And, the embodiment device 102
is a calculation means 1, an abnormality detection means 2, a switching means 3, and first to fourth analog signal input terminals 4.
1 to 44 and an analog signal output terminal 45. Here, the switching means 3 includes first to fifth switches 34 to 35 and a switching device operating circuit 36.
The output of the detection end 51 is connected to the first analog signal input terminal 41 via the input converter 151, and the first analog signal input terminal 41 is connected to the first switched terminal of the first switch 31. . First switching device 3
1 common terminal is connected to the first input of the maximum value calculation circuit 11 and the minimum value calculation circuit 12. The output of the detection end 52 is connected to the second analog signal input terminal 42 via an input converter 152. The second analog signal input terminal 42 is connected to the first switched terminal of the second switch 32, and the common terminal of the second switch 32 is connected to the second terminal of the maximum value calculation circuit 11 and the minimum value calculation circuit 12. connected to the input of The output of the detection end 53 is connected to the third analog signal input terminal 43 via the input converter 153. The third analog signal input terminal 43 is connected to the first switched terminal of the third switch 33. A common terminal of the third switch 33 is connected to the third input of the maximum value calculation circuit 11 and the minimum value calculation circuit 12. The output of the detection end 54 is connected to the fourth analog signal input terminal 54 via an input converter 154. The fourth analog signal input terminal 54 is connected to the first switched terminal of the fourth switch 34. The common terminal of the fourth switch 34 is connected to the maximum value calculation circuit 11 and the minimum value calculation circuit 1.
connected to the fourth input of 2.
最大値演算回路１１の出力はアナログ信号出力
端子４５に接続される。また最小値演算回路１２
の出力は第五の切換器３５の共通端子に接続され
る。第五の切換器３５の第一の被切換端子は第一
の切換器３１の第二の被切換端子に接続される。
第五の切換器３５の第二の被切換端子は第二の切
換器３２の第二の被切換端子に接続される。第五
の切換器３５の第三の被切換端子は第三の切換器
３３の第二の被切換端子に接続される。第五の切
換器３５の第四の被切換端子は第四の切換器３４
の第二の被切換端子に接続される。また、第一の
切換器３１の共通端子は異常検出手段２の第一の
入力に接続され、第二の切換器３２の共通端子は
異常検出手段２の第二の入力に接続され、第三の
切換器３３の共通端子は異常検出手段２の第三の
入力に接続され、第四の切換器３４の共通端子は
異常検出手段２の第四の入力に接続される。異常
検出手段２の出力は切換操作回路３６の入力に接
続される。 The output of the maximum value calculation circuit 11 is connected to an analog signal output terminal 45. Also, the minimum value calculation circuit 12
The output of is connected to the common terminal of the fifth switch 35. The first switched terminal of the fifth switch 35 is connected to the second switched terminal of the first switch 31.
The second switched terminal of the fifth switch 35 is connected to the second switched terminal of the second switch 32. The third switched terminal of the fifth switch 35 is connected to the second switched terminal of the third switch 33. The fourth switched terminal of the fifth switch 35 is connected to the fourth switch 34.
is connected to the second switched terminal of. Further, the common terminal of the first switch 31 is connected to the first input of the abnormality detection means 2, the common terminal of the second switch 32 is connected to the second input of the abnormality detection means 2, and the common terminal of the second switch 32 is connected to the second input of the abnormality detection means 2. The common terminal of the switch 33 is connected to the third input of the abnormality detection means 2, and the common terminal of the fourth switch 34 is connected to the fourth input of the abnormality detection means 2. The output of the abnormality detection means 2 is connected to the input of the switching operation circuit 36.
次に、この第一実施例装置の動作を第１図に基
づいて説明する。検出端５１〜５４の正常および
異常は異常検出手段２で識別される。第１図は、
第四の検出端５４に異常があり、第一ないし第三
の検出端５１〜５３が正常の場合が例示されてい
る。この場合に、第一ないし第三の切換器３１〜
３３では、共通端子と第一の被切換端子とが、ま
た、第四の切換器３４では、共通端子と第二の被
切換端子とが、異常検出手段２により駆動させる
切換操作回路３６の作動により閉路する。したが
つて、第四の切換器３４を経由して最大値演算回
路１１に導かれる入力は、正常な検出端である第
一ないし第三の検出端５１〜５３からの入力の最
小値であり、最大値演算回路１１の出力は正常な
検出端から導かれる入力のうちの最大値入力にな
る。 Next, the operation of the apparatus of the first embodiment will be explained based on FIG. The abnormality detection means 2 identifies whether the detection ends 51 to 54 are normal or abnormal. Figure 1 shows
A case is illustrated in which there is an abnormality in the fourth detection end 54 and the first to third detection ends 51 to 53 are normal. In this case, the first to third switching devices 31 to
33, the common terminal and the first switched terminal, and in the fourth switch 34, the common terminal and the second switched terminal are activated by the switching operation circuit 36 driven by the abnormality detection means 2. The circuit is closed by Therefore, the input led to the maximum value calculation circuit 11 via the fourth switch 34 is the minimum value of the inputs from the first to third detection terminals 51 to 53, which are normal detection terminals. , the output of the maximum value calculation circuit 11 becomes the maximum value input among the inputs derived from the normal detection terminal.
次に第二実施例装置を第２図に基づいて説明す
る。 Next, a second embodiment of the apparatus will be explained based on FIG. 2.
第一実施例装置１０２では、最大値演算回路１
１がアナログ信号出力端子４５に接続され、ま
た、最小値演算回路１２が第五の切換器３５の共
通端子に接続されるのに対し、第二実施例装置１
０３では、最大値演算回路１１は第五の切換器３
５の共通端子に接続され、また、最小値演算回路
１２はアナログ信号出力端子に接続される。 In the first embodiment device 102, the maximum value calculation circuit 1
1 is connected to the analog signal output terminal 45, and the minimum value calculation circuit 12 is connected to the common terminal of the fifth switching device 35, whereas the second embodiment device 1
In 03, the maximum value calculation circuit 11 is connected to the fifth switch 3.
In addition, the minimum value calculation circuit 12 is connected to the analog signal output terminal.
第２図に示す装置は、第２図に示す装置と同様
に、第４図の検出端５４に異常があり、第一ない
し第三の検出端５１〜５３が正常の場合が例示さ
れている。この場合の演算回路１０３の動作を説
明すると、第四の切換器３４を経由して最小値演
算回路１２に導かれる入力は、正常な検出端であ
る第一ないし第三の検出端５１〜５３からの入力
の最小値であり、最小値演算回路１２の出力は正
常な検出端から導かれる入力のうちの最小値にな
る。 Similar to the device shown in FIG. 2, the device shown in FIG. 2 is exemplified in the case where the detection end 54 in FIG. 4 has an abnormality and the first to third detection ends 51 to 53 are normal. . To explain the operation of the arithmetic circuit 103 in this case, the input led to the minimum value arithmetic circuit 12 via the fourth switch 34 is from the first to third detection terminals 51 to 53 which are normal detection terminals. The output of the minimum value calculation circuit 12 is the minimum value of the inputs derived from the normal detection terminal.
この実施例装置では、検出端の個数は四である
が、任意の複数個であつても本考案を実施するこ
とができる。 In this example device, the number of detection ends is four, but the present invention can be practiced with any number of detection ends.
本考案は、以上説明したように、プロセス制御
に用いられる測定量の最大値、最小値の演算に要
する複数個の検出単に単発故障が発生した場合
に、プロセス制御に支障を与えない精度の演算値
を簡単な回路の付加により実現する効果がある。
またアナログ入力変換器の切離しによる演算回路
の再構築を必要としない。
As explained above, the present invention is based on multiple detections required to calculate the maximum and minimum values of measured quantities used in process control, and calculations with precision that do not interfere with process control even in the event of a single failure. This has the effect of realizing the value by adding a simple circuit.
Furthermore, there is no need to reconstruct the arithmetic circuit by disconnecting the analog input converter.
第１図は本考案第一実施例装置の構成を示すブ
ロツク構成図。第２図は本考案第二実施例装置の
構成を示すブロツク構成図。
１……演算手段、２……異常検出手段、３……
切換手段、１１……最大値演算回路、１２……最
小値演算回路、３１〜３５……切換器、３６……
切換操作回路、４１〜４４……アナログ信号入力
端子、４５……アナログ信号出力端子、５１〜５
４……検出端、１５１〜１５４……入力変換器。
FIG. 1 is a block configuration diagram showing the configuration of an apparatus according to a first embodiment of the present invention. FIG. 2 is a block configuration diagram showing the configuration of an apparatus according to a second embodiment of the present invention. 1... Calculating means, 2... Abnormality detection means, 3...
Switching means, 11... Maximum value calculation circuit, 12... Minimum value calculation circuit, 31 to 35... Switch, 36...
Switching operation circuit, 41-44...Analog signal input terminal, 45...Analog signal output terminal, 51-5
4...Detection end, 151-154...Input converter.
Claims (1)
て出力する演算手段と、 上記多数のアナログ信号の各々についてその異
常を検出する手段と、 この検出する手段の異常検出出力により上記ア
ナログ信号入力端子の上記演算手段への入力を切
り換える切換手段と を備え、 上記演算手段は、最大値および最小値をそれぞ
れ演算する手段を含み、 上記切換手段は、 上記検出する手段の異常検出出力により、上記
演算手段の出力が最大値である場合には上記演算
手段が演算した最小値出力を、上記演算手段の出
力が最小値である場合には上記演算手段が演算し
た最大値出力を異常が検出された上記入力端子の
アナログ信号に代えて上記演算手段の入力にそれ
ぞれ与える手段を含む アナログ信号の演算回路。[Claims for Utility Model Registration] A large number of analog signal input terminals, arithmetic means for determining and outputting the maximum or minimum value of the analog signals, and means for detecting an abnormality in each of the large number of analog signals; switching means for switching the input of the analog signal input terminal to the calculation means based on the abnormality detection output of the detection means; the calculation means includes means for calculating a maximum value and a minimum value, respectively; and the switching means Based on the abnormality detection output of the above detecting means, when the output of the above calculating means is the maximum value, the minimum value output calculated by the above calculating means is calculated, and when the output of the above calculating means is the minimum value, the above An analog signal arithmetic circuit comprising means for respectively applying a maximum value output calculated by the arithmetic means to the inputs of the arithmetic means in place of the analog signal of the input terminal in which an abnormality has been detected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8263784U JPS61601U (en) | 1984-06-04 | 1984-06-04 | Analog signal calculation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8263784U JPS61601U (en) | 1984-06-04 | 1984-06-04 | Analog signal calculation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61601U JPS61601U (en) | 1986-01-06 |
| JPH0418003Y2 true JPH0418003Y2 (en) | 1992-04-22 |
Family
ID=30630531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8263784U Granted JPS61601U (en) | 1984-06-04 | 1984-06-04 | Analog signal calculation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61601U (en) |
-
1984
- 1984-06-04 JP JP8263784U patent/JPS61601U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61601U (en) | 1986-01-06 |
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