JPS6356430U

JPS6356430U -

Info

Publication number: JPS6356430U
Application number: JP14940186U
Authority: JP
Priority date: 1986-09-29
Filing date: 1986-09-29
Publication date: 1988-04-15

Description

[Brief explanation of drawings]

第１図は本考案に係る三角関数発生回路の構成
例を示す図、第２図は第１図回路の各部の信号の
タイムチヤート、第３図は従来の三角関数発生回
路の構成例を示す図、第４図は第３図回路の各部
の信号のタイムチヤートである。２１，２４……バツフア、２２，２３，２５，
２７……ラツチ、２６……加減算器、２８……乗
算器。 Figure 1 is a diagram showing a configuration example of a trigonometric function generation circuit according to the present invention, Figure 2 is a time chart of signals in each part of the circuit in Figure 1, and Figure 3 is a configuration example of a conventional trigonometric function generation circuit. FIG. 4 is a time chart of signals at various parts of the circuit shown in FIG. 21, 24...Batsuhua, 22, 23, 25,
27...latch, 26...adder/subtractor, 28...multiplier.

Claims

[Claims for Utility Model Registration] A first latch in which cos nT or sin nT is held, a second latch in which a constant 2cos T is held, and cos {(n-1)T} or sin {(n -1
)T} is held, and a signal is introduced from the first and second latches;
2cos T・cos nT or 2cos T・
A multiplication means for calculating sin nT, a signal is introduced from this multiplication means and a third latch, and 2 cos T cos nT-cos {(n-
1) T} or 2cos T・sin nT−si
A trigonometric function generation circuit comprising: an adder/subtracter that performs an operation of n{(n-1)T};