JPS62138253U

JPS62138253U -

Info

Publication number: JPS62138253U
Application number: JP2214986U
Authority: JP
Priority date: 1986-02-20
Filing date: 1986-02-20
Publication date: 1987-08-31

Description

[Brief explanation of the drawing]

第１図は本考案に係わるデータ転送クロツクレ
ート変換回路の一実施例を示すブロツク系統図、
第２図はその動作を説明するためのタイムチヤー
ト、第３図は従来のデータ転送クロツクレート変
換回路を示すブロツク系統図、第４図はその動作
を説明するためのタイムチヤートである。１……ｋビツト直列入力並列出力シフトレジス
タ、２……ｋビツト並列入力直列出力シフトレジ
スタ、３……クロツク発生・タイミング作成回路
、４……ｋビツトラツチ。 FIG. 1 is a block system diagram showing an embodiment of a data transfer clock rate conversion circuit according to the present invention.
FIG. 2 is a time chart for explaining its operation, FIG. 3 is a block system diagram showing a conventional data transfer clock rate conversion circuit, and FIG. 4 is a time chart for explaining its operation. 1... k-bit serial input parallel output shift register, 2... k-bit parallel input serial output shift register, 3... clock generation/timing generation circuit, 4... k-bit latch.

Claims

[Scope of utility model registration request]

a k-bit serial input parallel output shift register;
A k-bit latch connected in parallel with this k-bit serial-input parallel-output shift register, a k-bit parallel-input serial-output shift register connected in parallel with this k-bit latch, and an operating clock and timing for these shift registers and latches. What is claimed is: 1. A data transfer clock rate conversion circuit comprising a clock generation/timing generation circuit that supplies a clock.