JPH0349698U

JPH0349698U -

Info

Publication number: JPH0349698U
Application number: JP10883889U
Authority: JP
Priority date: 1989-09-18
Filing date: 1989-09-18
Publication date: 1991-05-15

Description

[Brief explanation of drawings]

第１図は本考案のシフトレジスタの駆動回路を
示す回路図、第２図は従来回路を示す回路図、第
３図は、第２図のシフトレジスタ内部における遅
延型フリツプフロツプの構成を示す回路図、第４
図は、第１図及び第２図のクロツク発生回路にお
けるクロツクの発生タイミングを示すタイミング
チヤートである。１……クロツク発生回路、５……シフトレジス
タ、６，７，９，１０……クロツクライン、１２
……第１の転送回路、１７……第２の転送回路、
３４，３６……Ｎ−ＭＯＳ、３５，３７……Ｐ−
ＭＯＳ。 Fig. 1 is a circuit diagram showing a drive circuit for the shift register of the present invention, Fig. 2 is a circuit diagram showing a conventional circuit, and Fig. 3 is a circuit diagram showing the configuration of a delay type flip-flop inside the shift register of Fig. 2. , 4th
This figure is a timing chart showing the timing of clock generation in the clock generation circuits of FIGS. 1 and 2. 1... Clock generation circuit, 5... Shift register, 6, 7, 9, 10... Clock line, 12
...first transfer circuit, 17...second transfer circuit,
34, 36...N-MOS, 35, 37...P-
M.O.S.

Claims

[Claims for Utility Model Registration] (1) A first transfer circuit that inputs/outputs or holds data based on a first clock, and inputs data from the first transfer circuit based on a second clock. a shift register comprising a plurality of stages of delay flip-flops including a second transfer circuit for outputting or holding; a clock generation circuit for generating the first clock and the second clock; a first clock line for applying a clock based on the first transfer circuit to the first transfer circuit of the plurality of stages of the delay type flip-flop; and a first clock line for applying a clock based on the second clock to the second transfer circuit of the plurality of stages of the delay type flip-flop. a second clock line for applying voltage to a transfer circuit; and a shift register driving circuit, wherein the first clock line and the second clock line are connected from the output of the clock generation circuit to the output of the shift register. As the clock moves towards the clock, a prohibition circuit is provided in the first transfer circuit that prohibits the first transfer circuit and the second transfer circuit from entering the input/output state simultaneously by the first clock and the second clock, respectively. 1. A shift register drive circuit, characterized in that the shift register drive circuit is connected to a clock line and the second clock line. (2) In the delay type flip-flop, the first transfer circuit has a first transmission gate for inputting and outputting data;
The shift register according to claim 1, wherein the second transfer circuit has a second transmission gate for inputting/outputting data from the first transfer circuit. drive circuit. (3) The inhibition circuit includes a first transistor for turning off the second transmission gate when the first transmission gate is turned on, and a first transistor for turning off the second transmission gate when the second transmission gate is turned on. 3. The shift register drive circuit according to claim 2, further comprising a second transistor for turning off the first transmission gate.