JPH02198215A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To save number of components and to reduce the chip area by inputting a reset signal to a clocked inverter(CI) of a master side and a slave side respectively via a MOS transistor(TR) so as to reset a CI output properly. CONSTITUTION:When reset is applied with a clock signal T at an L level, an N-channel MOS TR 12 is turned on, a P-channel MOS TR 6 and an N- channel MOS TR 7 are turned off and an output Q of an FF circuit goes to an L level. On the other hand, when the signal T is at an H level, the TR 12 is turned on and the N-channel MOS TR 9 is turned on, then the P-channel MOS TR 5 is turned off and the output Q goes to an L level, Thus, the TR 9 is connected to an output M of the master side CIA to input a reset signal inverse of R, the TR 12 is connected to the output Q of the CIB at the slave side to input the reset signal R and the CIB output is brought properly to the reset state by the TRs 9, 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a flip-flop circuit with reset.

[Prior Art] Conventionally, this type of flip-flop circuit with reset includes a clocked inverter A on the master side formed using IMOS transistors 1 to 4, and a MOS transistor 5, as shown in FIG. By providing MOS) transistors 9 and 10 on the master side, the input circuit for the reset signal R is configured with a NAND circuit, and the slave By providing MOS transistors 11 and 12 on the side, the input circuit for the reset signal R was constructed from a NOR circuit.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional example, since the reset circuit is configured using a NAND circuit and a NOR circuit, the number of elements increases and the configuration becomes complicated. When constructing a large-scale circuit such as a multi-stage shift register using a large number of flip-flop circuits, there is a problem in that the chip area becomes large.

The present invention has been made in view of the above points, and its purpose is to provide a flip-flop that can reduce the number of elements and reduce the chip area when configuring a large-scale circuit. The purpose is to provide circuits.

[Means for Solving the Problems] The 7-rip Flora 1 circuit of the present invention is a flip-flop circuit using a pair of clocked inverters, in which a reset signal is sent to the clocked inverter on the master side via the first MOS transistor. At the same time, a reset signal is input to the clocked inverter on the slave side via the second MOS transistor, and both MOS transistors appropriately reset the output of the clocked inverter.

[Function] The present invention is configured as described above, and a reset signal is input to the clocked inverter on the master side via the first MOS transistor, and the second MOS transistor is input to the clocked inverter on the slave side. A reset signal is input through the MOS transistor, and the clocked inverter output is set to the reset state as appropriate by both MOS transistors. In comparison, the number of elements can be reduced, and the chip area can be reduced when configuring a large-scale circuit.

[Embodiment] FIG. 1 shows an embodiment of the present invention. In a flip-flop circuit similar to the conventional example using a pair of clocked inverters A and B, a first clocked inverter A on the master side is used. A reset signal R is inputted through the MOS) transistor 9, and a reset signal R is inputted to the clocked inverter B on the slave side via the second MOS) transistor 12, and both MO3t-transistors 9 and 1 are inputted.
2, the outputs of the tallocked inverters A and B are set to a reset state as appropriate. In the embodiment, a P-channel MOS transistor 9 is used as the first MOS transistor 9 connected to the output of the clocked inverter B on the master side, and a second MOS transistor 9 connected to the output of the clocked inverter B on the slave side is used. As the transistor 12 (MOS) transistor 12, an N-channel type transistor is used.

The operation of the embodiment will be described below. 2 and 3 are operation explanatory diagrams, showing the signal waveforms of the input data signal D, clock signals T, T'', reset signal R1, and output signals M and Q. clock signal T
This figure shows the operation when a reset is applied when R is "L" (reset signal R → "H", reset signal → "L"). Since the transistor (channel type MOS)-transistor and the N-channel type MOS transistor 7 are turned off, the flip-flop circuit output Q is forcibly turned "off".

On the other hand, FIG. 3 shows the operation when a reset is applied when the clock signal T is °'H', and the N-channel type MOS transistor 12 is turned on and the N-channel type MoS transistor 9 is turned on. Therefore, the P-channel type MOS transistor 5 is turned off, and the flip-flop circuit output Q is forcibly set to 'L''.

As described above, in this embodiment, the output M to the clocked inverter on the master side is a P-channel type MOS.
) - transistor 9 is connected to input the reset signal R, and an N-channel MOS transistor 12 is connected to the output Q of the clocked inverter B on the slave side and the reset signal R is input, and both MO3) transistor 9 are connected. ，
12, the clocked inverter B output is appropriately reset, and unlike the conventional example, the NA
Compared to configuring a reset circuit using an ND circuit and a NOR circuit, the number of elements can be reduced by two, making it possible to reduce the chip area when configuring a large-scale circuit. .

FIG. 4 does not show another embodiment, in which a clocked inverter A on the master side is composed of a transmission gate made of MoS transistors 21 and 22 and an inverter made of MOS transistors 23 and 24, and a Mo5t-transistor 25
, 26 and a MOS transistor 27
．． In the flip-flop circuit which constitutes the clocked inverter B on the slave side with an inverter consisting of 28, a reset signal R is inputted through an N-channel type MOS transistor 29, and a reset signal is inputted through a P-channel type MOS transistor 30. When the reset signals R and R are input, the flip-flop circuit output Q is forcibly set to "L".

[Effects of the Invention] The present invention is configured as described above, and a reset signal is input to the clocked inverter on the master side via the first MOS transistor, and a second MOS transistor is input to the clocked inverter on the slave side. A reset signal is input through a transistor, and both MOS transistors reset the output of the clocked inverter as appropriate. When a reset circuit is configured using a NAND circuit and a NOR circuit as in the conventional example, This has the effect that the number of elements can be reduced compared to the previous one, and the chip area can be reduced when configuring a large-scale circuit.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of one embodiment of the present invention, Figs. 2 and 3 are explanatory diagrams of the same operation as above, Fig. 4 is a circuit diagram of another embodiment, and Fig. 5 is a circuit diagram of a conventional example. . 1 to 12. 21 to 30 are MOS) - transistors, A, B
is a clocked inverter. Agent Patent Attorney Ishi 1) Chief 7Figure 1Figure 2Figure 3Figure 4Figure 5

Claims (1)

[Claims] (1) In a flip-flop circuit using a pair of clocked inverters, a reset signal is input to the clocked inverter on the master side through the first MOS transistor, and a second MOS transistor is input to the clocked inverter on the slave side. 1. A flip-flop circuit characterized in that a reset signal is inputted through the MOS transistors, and the output of a clocked inverter is appropriately set to a reset state by both MOS transistors.