JPS59100614A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To reduce the pattern occupying area against high speed by inputting directly a control signal of set/reset to a gate of a feedback circuit so as to eliminate the effect on the circuit operation when set/reset is not in operation. CONSTITUTION:A transistor (TR) 27 is turned on when a set terminal is at ''1'', an output Q' is goes forcibly to ''0'' and an output Q goes forcibly to ''1''. On the other hand, a TR22 is turned on and the TR27 is turned off when the set terminal is at ''0''. As a load to the output Q' line, a gate capacitance of an inverter 21 is small. The junction capacitance of a feedback loop of a block 28 can be small, because the junction capacitance of the TR27 only is large. Thus, the load capacitance of the Q' line is small, the clock inverter 2 is speeded up. Since only the dimension of a few TRs has only to be increased against the high speed of the circuit operation, an FF circuit having a small pattern occupying area is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a flip-flop circuit having set, reset functions, etc.

[Technical background of the invention and its problems]

The master-slave type frizzo-frozzo shown in FIGS. 1 and 2 is a circuit that controls set (preset) and reset (clear) signals via NAND and NORff-). In the figure, 1 and 2 are clocked inverters provided on the data line, 3.4 is a NAND ff-to,
5 and 6 are clocked inverters, 7 and 8 are N0Rff-
), 9-12 are NAND gate 314, NOR dart 2
, 8 are clocked inverters for static operation, and 13 is an inverter. Figure 3 is the symbol of a clocked inverter and its detailed circuit, Figure 4 is a timing chart showing the operation of the flip-flop circuit in Figure 2, Figure 5 (,) is an inverter, and Figure 5 (b) is powered by two people. NAN
Df), FIG. 5(C) is a detailed circuit diagram of a two-man powered NOR r-to. Table 1 below is a truth table showing the operation of FIG. 1, and Table 2 is a truth table showing the operation of FIG. 2.

Table 1 Table 2 However, in Tables 1 and 2, H is high (1#) level, L
is a low (0'') level, and the asterisk (*) means that it is not related to ``H1'' and ``L''.

In a flip-flop having a set or reset function as described above, if high speed is required, the delay time of each dart must be shortened. At this time, in the circuits shown in FIGS. 1 and 2, in the NANII"-) or NOR dart inputting the set or reset signal, the P or N channel type MO8) transistor is shown in FIGS. 5(b) and 5(e). As shown in Figure 5, two transistors are inserted in series between the source and drain, so compared to an inverter (one transistor between the source and drain as shown in Figure 5 (!L)) that requires the same delay time, the transistor The channel width of J NAND ?-) or f-) in the front stage of the NOR gate must be increased. In order to eliminate the delay due to the increase, the channel width of the dart must be increased, which also affects the front stage of the r-). However, the size of each transistor is large, which poses a problem in terms of speeding up.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and is intended to improve the speed of the flip F70 knob having set and reset functions. The present invention aims to provide a 7-Rig flop circuit in which the area occupied by the turns can be reduced, in other words, the channel width of each MO8 transistor can be made as small as possible.

[Summary of the invention]

The present invention eliminates the influence on the circuit operation when the set or reset is not working by directly inputting the control signal such as set or reset to the dart of the holding (feedback) circuit. .

[Embodiments of the invention]

The present invention will be described in detail below with reference to the drawings. FIG. 6 shows the same embodiment, but since this is an example that corresponds to the one in FIG. 1, corresponding parts are given the same reference numerals and explanations are omitted, and the characteristic points will be explained. Do the following. In the figure, reference numeral 21 denotes an inverter inserted into the various output data lines of the clock 5-domain inverter 2. P-channel MOS transistors 22 to 24 are connected in series between the power supply VDD and the output terminal 01, and N-channel MOS transistors 25 and 26 are connected in series between the output terminal 01 and the power supply VIIg. An N-channel transistor 27 is provided between the output terminal 01 and the power supply Vllll. Transistor 22.27 r-
The gates of transistors 24 and 25 are connected to the data Q2 input, and the gates of transistors 23 and 25 are connected to the data Q2 input.
Clock signals φ and 7 are supplied to the 26 darts, respectively.

The circuit in Figure 6 shows that when the set terminal is 1#, the transistor 2
7 is on, the output page is forced to 10'', and the output Q is forced to 1#, which is the same operation as in Fig. 1.On the other hand, when the set terminal is 'O', the transistor 22 is on, When transistor 27 is off, block 28 is equivalent to clocked inverter 10 of FIG. 1 and operates in the same way as in FIG.

6- In the circuit of FIG. 6, considering the load on the output i-line, the dart capacitance of the inverter 21 is small, as in the case of FIG. 5 (,). Further, the junction capacitance of the feedback loop of the block 28 can be small because only the transistor 27 needs to be large. Therefore, the load capacitance of the mutual lines becomes small, so that the clocked inverter 2 can operate at high speed.

FIG. 7 shows another embodiment of the present invention, but since this is an example in which it corresponds to that in FIG. I will explain the points. The clock signals φ and ¥ are input to a NOR gate 31. which receives the original clock and the reset signal. Inverter 32,
3 J' is formed. 34 is clocked inverter 5
This is an inverter inserted into the output data line of the P-channel transistors 35 and 36 are connected in series between the power supply vDD and the output terminal 0, and the output terminal 02 and the power supply V81 are connected in series.
N-channel transistors 37 to 39 are connected in series between them. Further, a P-channel type transistor 40 is provided between the output terminal 02 and the power supply vDD. transistor 39
The darts of transistors 36 and 37 are connected to the output data line of the inverter 34, and the darts of transistors 35 and 38 are each supplied with a clock signal 7. Supply φ. An inverter 42 is inserted into the output data line of the clocked inverter 6.

The circuit in Fig. 7 shows that when the reset terminal is ``1#'', the clocked-in pin is set as φ = 61'' and 7 = ``0''.
On evening 6, the power is turned on. Meanwhile, the transistor 40 is turned on, and the output terminal 0. becomes '1' and point a becomes @'O', the truth table in Table 2 is reset, and the operation is the same as in the case of FIG. Also, the reset terminal is 0
”, the NOR dart 31 is influenced only by the clock signal, and the clock φ, i is determined. Then, the transistor 40
is turned off and transistor 39 is turned on.

Therefore! The lock 43 is the clocked inverter 1 in FIG.
1, the operation is the same as in the case of FIG.

In the circuit of FIG. 7, considering the output line of the clocked inverter 5, the ff-) capacitance of the inverter 34 is small as in the previous case. Further, the junction capacitance of the output line of the clocked inverter 5 can be kept small because only the transistor 4o needs to be made large. Therefore, the load capacitance of the clocked inverter 5 is small, so that the inverter 5 can operate at high speed.

FIG. 8 is a modification of FIG. 6, in which a P-channel transistor 271 is provided between the power supply VDD and the output terminal 01, and an N-channel transistor 221 is inserted between the transistor 26 and the power supply v■. This is an example in which the transistor f-) is connected to the control signal input terminal to provide a reset signal, and the transistors 27 and 22 in FIG. 6 are omitted. In this case, the portion corresponding to the NAND gate 3 in FIG. 6 is a NOR gate 3', and becomes an inversion reset type 7-lip flop.

9- Figure 9 is a modification of Figure 7, with power supply V88 and output terminal 0! An N-channel type transistor 401 is provided between the transistor 35 and the power supply VDD, a P-channel type transistor 391 is inserted between the transistor 35 and the power supply VDD, and the gates of these transistors are connected to the control signal input terminal. This is an example where 39 is omitted. In this case, it is a set type flip-flop type.

〔Effect of the invention〕

As described above, according to the present invention, since it is sufficient to increase the dimensions of a small number of transistors in order to increase the speed of circuit operation, it is possible to provide a flip-flop circuit that occupies a small four-turn area.

[Brief explanation of drawings]

Figures 1 and 2 are conventional flip-flop circuit diagrams, and Figure 3 is a conventional flip-flop circuit diagram.
The figure shows the symbol and circuit diagram of a clocked inverter, Figure 4 is a timing chart showing the operation of a conventional circuit, Figure 5 is a detailed diagram of a dart circuit, Figure 6 is a circuit diagram of an embodiment of the present invention, and Figure 7 Figures 10-9 are circuit diagrams of other embodiments of the present invention. 1.2, 5, 6, 9.12...Clocked inverter, J.=NANIl"-), J3, 21, 34.
. 42... Inverter, 22-24. -35.36°4
0...P chaol type MO8) transistor, 25-27
．． 37-39...N-channel type MO8) transistor,
01, 0... Output end. Applicant's agent Patent attorney Takehiko Suzue 11- 0 1C) To - 00 83-

Claims (1)

[Claims] It comprises a circuit main body in which clocked inverters and inverters f-) are alternately arranged and connected in cascade, and a holding loop for statically operating the inverter f-), the holding loop being connected to a first potential supply end and A series circuit of first to third MOS transistors of the first channel type is provided between the output end, and a series circuit of fourth and fifth MOS transistors of the second channel type is provided between the second potential supply end and the output end. A series circuit of transistors is provided, a second channel type sixth MO8 transistor is provided between the second potential supply end and the output end, and a series circuit of the third and fourth MOS transistors is provided. - gate is connected to the data line, clock signals having a mutually inverted relationship are supplied to r-1 of the second and fifth MOS transistors, and the dart of the first and sixth MOS transistors A flip-flop circuit, wherein a control signal for setting an output level of the circuit body is applied.