JPS6240816A - Latching circuit, and flip-flop circuit using this latching circuit - Google Patents

Abstract

PURPOSE:To execute a high speed operation by connecting each input terminal and output terminal of two clock gates, respectively, and providing a data transfer gate on each connecting point of the input terminal and the output terminal, respectively. CONSTITUTION:When a clock signal phi becomes '1', a data DI and an opposite phase DI are supplied to nodes N3, N4 through clocked inverters 171, 172 (data transfer gates), respectively. When a clock signal of an opposite phase becomes '1', the potential of the nodes N3, N4 are amplified and latched by clocked inverters 181, 182 (clocked gates). In this case, even if a circuit threshold value of the inverters 171, 172 is varied, these nodes N3, N4 are corrected to a correct potential immediately by the inverters 181, 182, if a magnitude relation of the potential of the nodes N3, N4 is correct. In this way, a high speed operation can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to logic circuits, and particularly to a latch circuit and a flip-flop circuit using this latch circuit.

[Technical background of the invention and its problems]

Conventionally, latch circuits (Transp@rent Latch
h) is configured as shown in FIG. 21 (,), for example.

That is, the input data DI is supplied to the input end of the clocked inverter 11 controlled by the clock signal φ. The output end of this clocked inverter 11 is connected to the input end of an inverter 120, and also connected to the output end of a clocked inverter 13 controlled by a clock signal i. The output end of the inverter 12 and the input end of the clocked inverter 13 are connected, so that a latch output DO is obtained from the output end Q of the inverter 12. FIG. 21(b) shows the above-mentioned FIG. 21(b).
) shows a block diagram of the circuit.

FIG. 22 shows a master-slave type D flip-flop circuit constructed by cascading two stages of latch circuits 1 to 1 shown in FIG. 21 (,) above. FIG. 23 shows clocked inverters 14 and 814° controlled by clock signals φ and φ, respectively, and an inverter '5j p I
This figure shows a D-type flip-flop circuit configured by cascade-connecting clocked inverters 13, . 13. is removed. 22nd above
The flip-flop circuit shown in the figure and FIG. 23 is represented by a block diagram as shown in FIG. A shift register can be constructed by cascading a plurality of stages of Fritsuno flop circuits as shown in FIG. In FIG. 25, each type of Fritznoflow, f 1 el
1 i 6. +...16IIIVi, data is sequentially shifted to the next stage at the falling edge of the clock signal φ.

As described in 1 to 1 above, the latch circuit is the basic circuit of the FritsunoFlo 27 circuit and the Shift Renostatahiro.

Incidentally, the above-mentioned D-type flip-flop circuit is widely used in computer registers, etc., but as the operating speed of computers increases, it is desired that the above-mentioned D-type flip-flop circuit also be faster. Particularly, such requirements are strong for registers forming the stage of a sous-game computer that operates on 9-line processing.

However, the above configuration has the disadvantage that it cannot sufficiently meet the above-mentioned high speed requirements. This is a problem with the clocked inverters that constitute the latch circuits and flip-flop circuits.

This will be explained in detail below. The clocked inverter is connected to power supplies vDD and vg as shown in FIG.

P-channel type MO8) transistor Q connected in series between
, , Q, and N-channel type MO8) Lannostar Q1.
It consists of Q4. The above MO8 transistor Q,
, Q, f・−) has a clock signal φ, ? are respectively supplied, and input data DI is supplied to the gates of the MO8) transistors Q*-Qs. And the above MO8
Output data DO from the connection point between transistors Q and Q.
get.

When the clocked inverter with the above configuration is used to construct a loop-type flip-flop as shown in FIGS. 22 and 23, the clock signal φ must be at the 6r level ( output node N1. of clocked inverter 111 or 141 during the period when N1. N is the inverter 12. Or 15
Each of the 10 circuits must reach a threshold vM. Therefore, there is a limit to increasing the frequency of the clock signal φ, 70. Moreover, even if the potential of the nodes N,,N, reaches the circuit threshold value vM, each node N,,N,
If the black signal φ reaches the @'0# level before the dart is sufficiently precharged or discharged, it takes time to drive the dart at the next stage, which causes a reduction in operating speed. Furthermore, if the threshold voltage of the P-channel MOS transistors Q, , Q, which constitute the clocked inverter becomes lower than the set value due to manufacturing process reasons or during use (for example - (down to about -1.5v with respect to the SV setting value), P-channel type MO
8) The drive ability of the transistors Qt and Qs is significantly reduced, and the output node cannot be brought to the "1#1#" level in a short time, resulting in a decrease in operating speed and reliability.

[Purpose of the invention]

This invention was made in view of the circumstances mentioned above.
The purpose is to provide a latch circuit that is capable of high-speed operation, has a wide operating margin, and has high reliability, and a Fritsuno-Fronno circuit using this latch circuit.

[Summary of the invention]

That is, in this invention, in order to achieve the above object, the input terminals and output terminals of two clocked inverters are connected to each other, and data is transmitted to each connection point between the input terminal and output terminal of these clocked inverters. Transfer darts are respectively provided, and input signals of opposite phases are supplied to the clocked inverter via these data transfer darts and latched.

Further, two stages of the latch circuits are connected in cascade to form a Fritsuno-Fronno circuit.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1(m) shows a configuration example of a latch circuit, and FIG. 1(b) shows its block diagram. Clocked inverter (data transfer dart) controlled by clock signal φ17. .

The input terminals of 173 have opposite phase data DI and D, respectively.
I is supplied. The above clocked inverter J71+”
The output terminals of a clocked inverter (clocked gate) 18m controlled by a relay signal φ are connected between the output terminals of the clock l and the output terminals of a clocked inverter (clocked gate) 18m controlled by a relay signal φ are connected, respectively. gate) 1
8. Output and input ends are connected respectively. Latch output signals Do and Do are obtained from the connection point N1 between the input end and the output end of the clocked inverters 18mm and 18m, and the connection point N4 between the output end and the input end, respectively.

In the above configuration, the clocked inverter 1B
, , 1B constitute a sense amplifier circuit and amplify data DI, DI input via a clocked inverter 111.1F. Now, assuming that the clock signal φ is at the ″′1# level, the data D
I and DI are supplied to nodes N, , N4 via clocked inverters 171.1'l, respectively. Then, when the clock signal φ reaches the @i# level, the node N,
.

The potential of N4 is amplified and latched by clocked inverter 181+Jgm. At this time, due to some reason, the clocked inverter 17m.

Even if there is a fluctuation in the circuit threshold value vM of 17, if the magnitude relationship of the potentials of nodes Ns and N4 is correct, these nodes N, , N4 will be connected to the black inverter 1B1 .
III, the potential is immediately corrected to the correct potential. For example, each clocked inverter 171 * 11B + 1
131 + 18* circuit threshold value vM is 2.5v, input cuff "-IDI="o" (Ov), DI="l"
(5v), and clock signal φ changes from 11” level to “
When the voltage changes to 0 level, the potentials of nodes Nl and N4 become 1.5v and 1.5v, respectively. Even if it becomes OV, this potential is immediately changed to sv by the clocked inverter 181*1'*.
, ov, and can provide data to the nodes connected to these nodes N,,N,. Note that the clock signal φ is 1
0” level, clocked inverter lJ+18M
The data of nodes N, . . . N4 is statically held.

Therefore, according to such a configuration, clocked inputs 17□, 17. If at least one of them takes in enough data DI or DI, the other will not operate normally and the potential of its output node will reach the circuit threshold value vM of the gate connected to the next stage (but even if it does not, it will function normally). The operation can be performed with high reliability.Furthermore, even if the output of the clocked inverter 171r1'* is not completely determined, it is only necessary to determine the magnitude relationship, so that the operation speed can be increased.

FIGS. 2 through 7 each show the results of a simulation using the circuit simulation 5PICE of the sense amplifier circuit consisting of the clocked innocent 18I+181 shown in FIG. 1 (凰). In this simulation, the circuit is configured as shown in FIG. Converting such a circuit to 0MO8, N-channel type M
O8) The ratio of the channel width Wn and channel length Ln of the transistor is Wn/Ln=15/1.2, P channel type MO8
) The ratio of the channel width Wp and the channel length LP of Lanzostar is set to Wp/L p =22/1.5. Figure 2 shows A (corresponding to node N in Figure 1)
5V, B (corresponding to node N4 in Figure 1) is OV
The simulation results are shown when a clock signal is applied after the initial settings are made.

Similarly, Fig. 3 shows 1A=4V, B=lV, and Fig. 4 shows A=3.
V, B = 2V, Figure 5 shows A = 2.6 V,, B
= 2.4V.

Figure 6 shows A=2V, B=lV, and Figure 7 shows A=1.
After initial setting v and B=OV, a clock signal φ is applied. As shown in the figure, even if the levels of the input signals A and H are applied to the inverter 19, 19. Even if it is lower than the circuit threshold voltage vM, due to the amplification operation of the clocked inverters 1B, , 1B, eventually A'=O
V, B'=5V is set. In this way, it is possible to operate satisfactorily even if one of the supplied data has an incomplete value.

Next, as shown in FIG. 9, an inverter 20 was provided in place of the clocked inverter 18□ in FIG. 8, and a similar circuit simulation was performed. This result is the 10th
and FIG. 11. In Figure 10, A=2
．． 5V, and in FIG. 11, after initial setting to A-2V, a black signal l is supplied. As shown in the figure, in the circuit configuration shown in FIG. 9, if the input signal A is 2.5V, this potential is crossed.

Kudo Impata 18. 5v by and inverter 20
However, if the input signal A is 2V, it becomes Ov, and the correction is impossible. On the other hand, in the circuit shown in FIG. 8, as shown in FIGS. 6 and 7, even when the input signal A is 2v and 1v, it can be corrected to 5v and latched.

FIG. 12 (6) shows another embodiment of the invention.

In the figure, the same components as those in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted. That is, by providing a clock donand dart 21 in place of the clocked inverter 188 in FIG.
It is possible to set. FIG. 12(b) shows a block diagram of FIG. 12(a).

Even in such a configuration, basically the same as shown in FIG.
The circuit operates in the same way as the circuit above, and the same effect can be obtained.

In each of the above embodiments, the clocked inverter 111rl'm was used as the data transfer gate, but as shown in FIG.
and nodes N,,N.

Inverter 23. ．． 23. are provided, and latch outputs Do, DO are provided from the output terminals of these inverters 231*23m.
You can also try to get .

FIG. 14 shows another embodiment of the present invention, in which two stages of the latch circuits shown in FIG. Clocked inverters 17, 417 . controlled by a clock signal (first control signal). Data DI and DI of opposite phase are supplied to the input terminals of , respectively. Between the output terminals of each of the clocked inverters 171rl1M, the input terminal and output terminal of a clocked inverter 18□ controlled by the clock signal 1 are connected, and the clocked inverter 188 controlled by the clock signal f is connected. The output end and input end of are connected to each other. A clock signal (
second control signal) positive controlled clocked inverter 17. The input end of is connected. In addition, the above-mentioned clocked in-no-event 18. Input end and black, Kudo impata 18
．． The connection point (node N4) with the output end of the ? A clocked inverter 1740 input terminal controlled by a clocked inverter 1740 is connected thereto. Each of the above clocked inverters 11B+
A clocked inverter 18 . The input terminal and output terminal of clocked inverter 184 controlled by clock signal φ are connected to each other. The clocked inverter 18.
The output signal Do is obtained from the connection point (node Ns) between the 0 input terminal and the output terminal of the clocked inverter 18°, and the connection point between the input terminal of the clocked inverter 184 and the output terminal of the clocked inverter 18m. (Node N,) output signal ``0'' is obtained.

In the above configuration, the clocked inverter 17
□, 17. and 18□, 18. a latch circuit consisting of a clocked inverter If/, , 114 and 1B=
18. Each of the latch circuits shown in FIG.
) performs exactly the same operation as the circuit. Therefore, each latch circuit is capable of high-speed operation and has high reliability.
A flip-flop circuit constructed by cascading child circuits as described above can also operate at high speed, and has a wide operating margin and high reliability.

FIG. 15 shows the above-mentioned circuit simulation 5PICE for the flip-flop circuit shown in FIG. 14.
This figure shows the results of a motion simulation using . Here, the circuit shown in FIG. 14 is converted into a CMOB, and the ratio of the channel width Wn and the channel length Ln of the N-channel MOB transistor is set to Wn/Ln=15/1.2, P
Channel type MO8) The ratio of the channel width Wp and the channel lengths t and p of the runnostar is set to Wp/Lp=15/1.2, and the clock signal φ is 333.33MH.
z (period: 3 ns@o). As shown in the figure, it can be seen that sufficient operation is possible even when the clock signal φ has a high frequency.

FIG. 16 shows a block diagram of the flip-flop circuit shown in FIG. 14. In this case, the f flow rough circuit 24 is cascaded in multiple stages (n stages) by connecting the input terminal D and the output terminal Q and i, respectively, as shown in Figure @17, and the same clock is applied to each clock input terminal CK. When the signal φ is supplied,
Shift registers can be configured.

Note that, as shown in FIG. 18, the nodes N, , N in the flip-flop circuit shown in FIG. 14 and the clocked inverters 17, 117! , and nodes N, ,N, respectively. 254 are provided, and an inverter 25. .

Even if the output signals DO and DO are obtained from 254, the same operation as the circuit shown in FIG. 14 can be performed and the same effect can be obtained.

FIG. 19 shows another embodiment of the present invention, in which transfer gates 261 to 264 are provided in place of clocked inverters 17□ to 174 as data transfer gates in FIG. 18, respectively. . This circuit is constructed by cascading two stages of the latch circuits shown in FIG. 13 above.

FIG. 20 shows yet another configuration example of the flip-flop circuit. That is, in each of the embodiments described above, clock signals φ, i were used, but in the circuit shown in FIG. 20, clock signals φ1+L and φ8 . How to use each φ8,
The circuit configuration is the same as the previous distribution figure 14.

Even with the configuration shown in FIGS. 19 and 20,
It goes without saying that basically the circuit operates in the same way as the circuits shown in FIGS. 14 and 18, and the same effects can be obtained.

[The germ of invention]

As described above, according to the present invention, it is possible to obtain a latch circuit that is capable of high-speed operation, has a wide operating margin, and has high reliability, and a flip-flop circuit using this latch circuit.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a latch circuit according to an embodiment of the present invention, and FIGS. 2 to 7 are diagrams showing the results of seamirelation conducted to explain the operation of the circuit shown in FIG. 1, respectively. Figure 8 is a diagram showing the circuit used for the sea mileage in Figures 2 to 7 above, Figure 9 is a diagram showing the circuit used for another sea mileage, and Figures 10 and 11 are respectively 12 and 13 are diagrams showing a latch circuit according to another embodiment of the present invention, respectively.
The figure shows a flip-flop circuit constructed using the launch circuit shown in Fig. 1 above, Fig. 15 shows the results of a simulator of the 7 flip-flop circuit shown in Fig. 14 above, and the f circuit. 14 is a block diagram of the flip-flop circuit, FIG. 17 is a diagram showing a shift register constructed using the flip-flop circuit of FIG. 16, and FIGS. 18 to 20 are the flip-flop circuits of FIG. 14, respectively. FIG. 21 is a diagram showing a conventional latch circuit; FIG. 22 is a diagram showing a conventional flip-flop circuit constructed using the latch circuit shown in FIG. 21;
FIG. 23 is a diagram showing another configuration example of a conventional flip-flop circuit, FIG. 24 is a block diagram of the flip-flop circuit shown in FIGS. 22 and 23, and FIG. 25 is a block diagram of the flip-flop circuit shown in FIGS.
Shift 1/ constructed using the flip-flop circuit shown in the figure.
FIG. 26 is a circuit diagram showing an example of the configuration of a clocked input/output register. 1B, , IFI, . . . clocked inverter (first degree second clocked data 1-), J . . . clock signal,
17. 17. ...clocked inverter (first and second data transfer 'l'-to), φ...clock signal (
control signal), DI, DI...input data, Do. 6-0...Output signal. Patent attorney Suzue Takehiko-Kazuaki and OtQ Hitoichi 80=. 15 H - Figure 26

Claims (6)

[Claims] (1) A first clocked gate, an output terminal is connected to the input terminal of the first clocked gate, and an input terminal is connected to the output terminal, and is controlled by the same clock signal as the first clocked gate. a second clocked gate, and first and second data transfer gates that are controlled by a control signal and supply opposite phase data to input terminals of the first and second clocked gates, respectively; Second above,
A latch circuit characterized in that a latch output is obtained from an output terminal of a first clocked gate. (2) The first and second clocked gates each have
2. The latch circuit according to claim 1, comprising a clocked inverter. (3) The first and second data transfer gates each have a
2. The latch circuit according to claim 1, comprising a clocked inverter. (4) a first clocked gate controlled by a first clock signal, an output end connected to the input end of the first clocked gate, and an input end connected to the output end; a second clocked gate controlled by a clock signal; and first and second clocked gates controlled by the first control signal and supplying opposite phase data to the input terminals of the first and second clocked gates, respectively. a data transfer gate, a third clocked gate controlled by the second clock signal, an output end connected to the input end of the third clocked gate, and an input end connected to the output end; a fourth clocked gate controlled by the second clock signal; and a latch signal controlled by the second control signal and outputted from the output ends of the second and first clocked gates. and third and fourth data transfer gates that respectively supply input terminals of the four clocked gates,
A flip-flop circuit characterized in that an output is obtained from the output terminals of the fourth and third clocked gates. (5) The flip-flop circuit according to claim 4, wherein each of the first to fourth clocked gates comprises a clocked inverter. (6) The flip-flop circuit according to claim 4, wherein each of the first to fourth data transfer gates comprises a clocked inverter.