JPH0212055B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a master-slave type latch circuit formed by cascading two unit latch circuits each having a complementary MOS structure (CMOS).

Two CMOS inverters are connected in series, a transmission gate is connected between the input side and the input signal source, and the output of the second inverter and the input of the first inverter are connected to another transmission. A device in which two stages of unit latch circuits are connected in cascade using unit latch circuits connected by gates is often used as a master-slave type latch circuit in semiconductor integrated circuits.

This type of latch circuit is used as a counter when multiple stages are connected in series to repeatedly input and hold data using two-phase clocks having opposite phases.

Figure 1 is a circuit diagram showing a unit latch circuit composed of CMOS, where 1 and 2 are CMOS inverters, and 3 is a p-channel MOS transistor (hereinafter referred to as p-channel MOS transistor).
-MOST) Q _p1 and an n-channel MOS transistor (hereinafter referred to as n-MOST) Q _o1 , and 4 is a feedback side transmission gate consisting of p-MOSTQ _p2 and n-MOSTQ _o2 . It is a transmission gate. FIG. 2 is a waveform diagram of clocks V ₁ and V ₂ , where clock V ₂ is the inverted output of clock V ₁ .

Figure 3 is a circuit diagram showing a master-slave type latch circuit in which two stages of such unit latch circuits are connected in cascade.The first stage unit latch circuit _L1 has inverters 11 and 12, p-MOSTQ _p11 and n
- input side transmission gate 13 consisting of MOSTQ _o11 , and p-MOSTQ _p12 and n
- It is composed of a feedback transmission gate 14 consisting of MOSTQ _o12 . The second stage unit latch circuit _L2 has inverters 21 and 22, p-
Input side transmission gate 23 consisting of MOSTQ _p21 and n-MOSTQ _o21 and p-
It consists of a feedback transmission gate 24 consisting of MOSTQ _p22 and n-MOSTQ _o22 , and n-MOSTQ p22 and n-MOSTQ o22.
Clock v ₁ is supplied to the gates of MOSTQ _o11 , Q _o22 and p-MOSTQ _p12 , Q _p21 , and n-
A clock _v2 is supplied to the gates of MOSTQ _o12 , Q _o21 and p-MOSTQ _p11 , Q _p22 . The input voltage of the first stage unit latch circuit _L1 is V _A , and the inverter 1 is
The input voltage of the inverter 11 is _VB , the output voltage of the inverter 11 _{is VC} , and the output voltage of the unit latch circuit _{L1 is VD} .
A voltage V _C is supplied to the input of the second stage unit latch circuit _L2 . The input voltage of the inverter 21 is V _E ,
Let the output voltage of unit latch circuit _L2 be _VF .

In the above configuration, if the two-phase clocks V ₁ and V ₂ that control data input and data retention are in a completely opposite phase relationship, the input transmission gate 13 of the first stage unit latch circuit L ₁ is When turned ON, the input side transmission gate 23 of the second stage unit latch circuit _L2 is completely OFF, and the data input to the first stage unit latch circuit _L1 is directly transmitted to the second stage unit latch circuit L2. The so-called lacing of leakage to the unit latch circuit _L2 does not occur. However, if one of the two-phase clocks has a time delay due to the influence of capacitance, racing occurs and causes malfunction.

This invention has been made in view of the above points, and aims to realize a master-slave type latch circuit that always operates normally by analyzing the mechanism in which racing occurs and finding conditions under which racing does not occur. The purpose is to

Regarding Figure 4 a and b below, clock V ₂
Let us consider the conditions under which racing occurs when V operates with a delay of time T _D from the change in V ₁ . timing
At _T1 , V _A is taken into the unit latch circuit _L1 . It is held at timing _T2 and transferred to unit latch circuit _L2 . At timing _T3 , the unit latch circuit _L1 is at _{the A} (“0” level in Fig. 4a,
In FIG. 4b, the transmission gate 13 is turned ON to input the "1" level), and the transmission gate 23 is turned OFF so that the unit latch circuit _L2 retains the previous value.

At the first half T ₃₁ , T ₃₂ , T ₃₃ of timing T ₃ , V ₁ ,
Since V ₂ > 0, the n-MOST of the transmission gates of unit latch circuits L ₁ and L ₂ is turned OFF.
is in a transition state from to ON or is in a complete ON state. Therefore, the timings T ₃₁ , T ₃₂ , T ₃₃
Before the transmission gate 23 of the unit latch circuit L ₂ is completely turned OFF, the transmission gate 13 of the unit latch circuit L ₁ is turned off completely.
By starting the ON state, _A is input and the output _VF of the unit latch circuit _L2 is inverted, causing racing. Here, the timing at which racing occurs is determined to be T ₃₁ , T ₃₂ , or T ₃₃ . For simplification, in FIG. 4a, at timing T ₃₂ when input V _A is changed from potential V _DD to GND,
As shown in Figure 5, the gate input signals of all transmission gates are V _DD and are at a high level, so all p-MOSTs are in the OFF state n-
All MOSTs are turned ON. Each node potential is
V _DD (high level) is shown as “1” and GND (low level) is shown as “0”. The equivalent circuit of unit latch circuit L ₁ is as follows before unit latch circuit L ₁ changes:
If we remove the two inverters, we get Figure 6, and when we solve for Q _o12 in the saturated region and Q _o11 in the non-saturated region, V _B is expressed by the following equation.

Here, V _DD ; power supply voltage V _TN ; n-MOST threshold voltage β _N2 ; n-MOST Q _o12 at feedback transmission gate 14;
Conductance (hereinafter conductance is referred to as β) β _N1 ; n-MOSTQ _o11 at input side transmission gate 13
β β _N1 = β _N2 , V _DD = 5V, V _TN = 0.6V, then V _B
=1.29V, and V _D =5V held by the unit latch circuit _L1 is inverted to 0V. At this time, if V _F = 0V is held in the unit latch circuit L ₂ , from equation [1], even if V _C = 5V, V _E = 1.29V, and V _F =
Racing will not occur if 0V is maintained.

However, at timing _T31 , the input transmission gate 13 of the unit latch circuit _L1
When V _C = 0V to 5V in the ON state, if the input transmission gate 23 of the unit latch circuit L ₂ is also ON, racing occurs when V _E reaches the voltage that inverts the unit latch circuit L ₂ . occurs.

Next, in Figure 4b, V _A is changed from GND to V _DD
At timing T ₃₂ when changed to [1]
From the formula, V _B = 1.29V, and the unit latch circuit _L1 maintains V _D = 0V even when the input transmission gate 13 is in the ON state, so the timing is
Racing doesn't happen on the T ₃₁ . However, at timing _T33 , the transmission gate 13 of the unit latch circuit _L1 is in the ON state, and V _C =
When changing from 5V to 0V, if the transmission gate 23 of the unit latch circuit _L2 is also ON, racing will occur when V _E reaches a voltage that inverts the unit latch circuit _L2 . From the above, V _A
Racing is slow due to data differences
Occurs at the rising edge of V ₁ or the falling edge of clock V ₂ . The condition for racing to occur in the future is when the input V _A changes from V _DD to GND.
Consider the rise of V ₁ .

In FIG. 4a, the gate input voltage V ₁ of the transmission gate at which racing occurs at timing T ₃₁ is determined. FIG. 7 shows the state of the transmission gate at timing _T31 from FIGS. 3 and 4a. Here, each node potential is V _DD
(high level) is “1”, GND (low level) is “0”
shall be. The input voltage at which the inverter inverts is V _B =
Assuming that V _DD /2 and V _C =V _DD , the equivalent circuit of the transmission gates of unit latch circuit L ₁ and unit latch circuit L ₂ is as shown in FIG. The conditions for racing to occur are V _B = V _E = V _DD /
2 and assuming that all transistors in Fig. 8 operate in the saturation region, the unit latch circuit
The transmission gate gate input voltages V ₁₁ and V ₁₂ at L ₁ and L ₂ are given by the following equations, respectively. Unit latch circuit L ₁ (input side transmission gate OFF → ON) Unit latch circuit L ₂ (input side transmission gate ON → OFF) Here; x= _VDD - _{VTN - VTPy1} = _VDD - _VTN - _VBY2 = _VDD - _{VTN -VE .}

Let β _p1 = β _p2 = β _N1 = β _N2 , V _DD = 5V, |V _TP |=
If V _TN = 0.6V, V _B = V _E = V _DD /2, [2],
From formula [3], V ₁₁ =V ₁₂ =2.98V. this is,
This is the boundary between whether racing occurs or not.

If β _p2 > β _p1 , β _N2 > β _N1 , β _p1 = β _N1 , β _p2 = β _N2 , then V ₁₁ > V ₁₂ and before the input transmission gate 13 of the unit latch circuit L ₁ is turned on. Since the transmission gate 23 on the input side of the unit latch circuit _L2 is turned OFF, no racing occurs. For example, when β _p2 = β _N2 = 1.1β _p1 = 1.1β _N1 ,
V ₁₁ = 3.00V, V ₁₂ = 2.90V, and racing can be suppressed. That is, by making β of the feedback transmission gate larger than β of the input transmission gate, racing can be prevented even if there is some time delay in the clock waveform.

As detailed above, the master
In slave type latch circuits, the transmission gate on the feedback side of each unit latch circuit is configured.
Since the conductance β of the MOST is made larger than the conductance β of the MOST constituting the input transmission gate, stable operation is possible without causing racing even if there is a slight time delay in the inverted output of the gate clock.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a unit latch circuit constructed of CMOS, Figure 2 is a waveform diagram of a two-phase clock, Figure 3 is a circuit diagram of a master-slave type latch circuit to which the present invention is applied, and Figure 4a. , b are waveform diagrams of various parts to explain the racing generation mechanism, FIG. 5 is a circuit diagram showing the state of the master-slave type latch circuit at timing T ₃₂ of FIG. 4 a, and FIG. FIG. ₇ is a circuit diagram showing the state of the master-slave type latch circuit at timing T ₃₁ of FIG. 4 a, and FIGS. 8 a and b are 8 is an equivalent circuit diagram of the transmission gates of unit latch circuits _L1 and _L2 in the situation of FIG. 7, respectively; FIG. In the figure, L ₁ and L ₂ are unit latch circuits, 11,
12, 21, 22 are inverter circuits, 13, 23
is the input side transmission gate, 14, 24
is the return side transmission gate. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1 first-stage and second-stage inverter circuits connected in cascade, an input-side transmission gate consisting of a complementary MOS transistor inserted in the input path of the first-stage inverter circuit, and the first-stage inverter circuit;
The complementary type
In a structure in which a plurality of unit latch circuits each having a feedback transmission gate made of a MOS transistor are connected in cascade, the conductance of the MOS transistor constituting the feedback transmission gate of each unit latch circuit is expressed as above. A master device characterized in that the conductance is larger than the conductance of the above-mentioned MOS transistor constituting the input side transmission gate.
Slave type latch circuit.