JPH04172809A - Flip flop circuit - Google Patents

Abstract

PURPOSE:To reduce the layout size of a flip flop circuit by providing a transfer gate as an input-side latch and a dynamic latch having an amplifying and inverting functions as an output-side latch. CONSTITUTION:An input latch is composed of a transfer gate which is constituted by connecting a P- and N-channel MOS transistors M5 and M6 in parallel and clock inputs CK and the inverse of CK are complementarily inputted to each gate. The output of the transfer gate is connected to an internal node N1. An output-side latch is composed of a tri-state inverter which is constituted by connecting P-channel transistors M1 and M2 and N-channel transistors M3 and M4 in series. The internal node N1 is connected to the gates of the transistors M1 and M4 and clocks CK and the inverse of CK are connected to the gates of the transistors M2 and M3. The output of the output-side latch is fetched from the drains of the transistors M2 and M3.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to flip-flop circuits, particularly MOS).
Dynamic flip circuit composed of transistors
Regarding flop circuits.

[Conventional technology]

Conventionally, there is a dynamic flip-flop of this type as shown in FIG.

As a latch on the input side, a transistor M5. M6 and N-channel MOS) transistor M7. M8
Using a tri-state inverter consisting of M6.
M7 has clock input CK.

By inputting σX in a complementary manner, when σY=high level and CK=low level, the potential of the input terminal VrN is stored in an inverted state at the internal node N1.

When the clocks GK and -σX are inverted, the latch on the input side is turned off, and the charge at the node N1 is stored in the gate electrode of the latch at the subsequent stage.

The latch on the output side is the same as the input side, between the P-channel transistors Ml and M2 and the N-channel MOS transistor M.
3. M4, however, clock inputs CK, -
σX is M3. M2 is controlled, and when the clock OK is high level and σ is low level, the potential of node N1 is set to the pressure terminal V. Invert and output to TJT.

FIG. 2 shows a time chart of the above operation. This flip-flop operates on the rising edge of the clock CK, and is called "dynamic" because its internal state is maintained simply by being stored in the gate electrodes of the MOS transistors M1 and M4. It is.

Also, the output V. UT's! The position is also V when OK = low level and CK = high level. It will be maintained by the capacitive load added to the LIT.

[Problem to be solved by the invention]

In the conventional flip-flop described above, the role of the input side latch by MOS transistors M5 to M8 is only to store the potential of the input terminal VrN in the internal node N1. Since no input load or wiring load is added to the output side latch, the drive ability is not a problem, unlike the output side latch.

Therefore, transistors M5-M8 are transistors M1-M
Although it is possible to use transistors smaller in size than transistors M5. M6
or transistor M7. Since this is carried out using a bus in which two stages of M8 are connected in series, there is a drawback that the charging and discharging time becomes longer if a too small one is used. In other words, L
There is a limit to how compact the layout can be when converted to SI.

[Means to solve the problem]

The flip-flop circuit of the present invention has a transfer gate as an input latch and an amplification/amplification circuit as an output latch.
It has a dynamic latch with inversion function.

Therefore, the layout size can be reduced by using the input side latch as a mere transfer gate.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention. The input latch is composed of a transfer gate in which a P-channel MOS transistor M5 and an N-channel MOS transistor M6 are connected in parallel, and clock inputs CK and CK are input complementary to each gate 1. The output of the transfer gate is connected to internal node NU. The output side latch is composed of P-channel transistors M1, M2 and N-channel trough 915M3. It consists of a tri-state inverter in which M1 and M4 are connected in series, and the internal node N1 is connected to the gates of M1 and M4, and the internal node N1 is connected to the gates of M2 and M4. The gate of M3 has a clock “σ”, C
K is connected, and the output is taken out from the drains of M2 and M3.

The difference in operation from the conventional example shown in FIG. 4 is the transfer gate of the input latch. The potential of the input terminal VfN is transmitted to the internal node N1 without being inverted when CK=high level and CK=low level. At this time, the transfer gate has no amplification effect and there is a concern that the speed will decrease, but in the conventional example, the load connected to the input terminal VIN, that is, M5. In the present invention, the charging and discharging of the gate electrode of M8 is performed through the transfer gate of M5. This corresponds to the charging and discharging of the M6 gate electrode, so when viewed from the perspective of the change in the internal node Nl from the input,
It is not inferior to the conventional example.

The minimum time required for charging and discharging internal nodes is expressed by set-up time and hold time, and the W/L# of each transistor channel is 26 μm/1.0 μm.
The sum of set-up time and hold time is 0.5n.
The result is sa:.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

The difference from the circuit in Figure 1 is that the input side latch is a P-channel MO.
This is where the S transistor M5 is removed. Therefore,
Internal node Nl is at high level and VDD VT (
VT swings only up to the threshold voltage of transistor M6), and a through current flows when the output side latch is turned on, but the operation as a flip-flop is exactly the same as in the first embodiment.

According to this configuration, a flip-flop can be configured with five MOS transistors.

〔Effect of the invention〕

As explained above, the present invention is a dynamic flip
By using the latch on the input side of the flop as a transfer gate, there is an effect that the flip-flop can be constructed with 5 to 6 M○S transistors.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the flip-flop of the present invention, FIG. 2 is an operation time chart of the flip-flop of the present invention and the conventional flip-flop, and FIG. 3 is a circuit diagram of a second embodiment of the flip-flop of the present invention. FIG. 4 is a circuit diagram of a conventional flip-flop. M1 to M8...MOS) transistor, vrN・
...Input terminal, VOUT...Output terminal,
CK, GK...Clock input terminal, vDD...
...Positive power supply, VSS...Negative power supply. Agent Patent Attorney Susumu UchiharaMrNHb: 5os) Lasishinuk SS 1st Ward Klong Kuenshi 0
5 2 countries

Claims (1)

[Claims] In a dynamic flip-flop circuit that consists of two latches that operate complementary to the input clock and are connected in a vertical line, the latch on the input side consists of a transfer gate that does not have an amplification or inversion function. A flip-flop circuit characterized in that the latch on the output side is composed of a dynamic latch with amplification and inversion functions.