JP2022534821A - Low power flip-flop circuit - Google Patents

Abstract

Aspects of flip-flop circuits are described herein. By way of example, these aspects may include pass gates, pass gate inverters, leakage compensation units, and inverters. A pass gate may be coupled between the flip-flop data input terminal and the first node. A pass gate inverter and an inverter may be sequentially connected between the first node and the flip-flop data output terminal. The leakage compensation unit may be connected in parallel with the pass gate inverter and the inverter between the first node and the flip-flop data output terminal. [Selection drawing] Fig. 1

Description

A flip-flop is a sequential circuit ( sequence circuit). A flip-flop can store a next value that depends on the value of one or more input signals. Conventionally, flip-flops include data, clock, set and/or reset input signals.

A data (usually denoted D) input signal is typically clocked into a flip-flop upon receiving a predetermined clock edge. Set (usually denoted as S) and reset (usually denoted as R) input signals are not normally clocked, which means that when a set or reset signal becomes active (eg, goes high). , meaning that the stored value changes immediately without waiting for the arrival of the clock edge. A flip-flop is typically a master-slave latch structure. Each latch becomes active (transparent) either at a logic high or at a logic low (not an edge). On the rising (trigger) edge, the master latch latches the input and stores the data value, and the slave latch becomes active (transparent) and passes the value to the output. Assuming the active phase of the master latch is 0, on the falling edge the master latch becomes active (transparent) to accept the next value, the slave latch latches what was latched by the master latch, and the master Continue to output the value stored in the latch. Therefore, the output changes only at each trigger edge. An active set signal forces the stored value (usually denoted as Q) high regardless of the previously stored value. An active reset signal forces the stored value Q low regardless of the previously stored value. Set/reset flip-flops (i.e. flip-flops with both set and reset input signals) typically have limited set and reset signals so that at most one is active at any given time. It is possible. Since flip-flops are a fundamental building block of modem digital design, power consumption and area must be minimized. New flip-flops have been proposed that reduce power consumption and area compared to traditional flip-flop designs.

SUMMARY The following presents a simplified summary of one or more aspects to provide a basic understanding of these aspects. This summary is not a comprehensive overview of all possible conceptual aspects, nor is it intended to point out key or critical elements of all aspects, nor is it intended to identify any of them. nor is it intended to delineate the scope of all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form that lead to the more detailed description that is presented below.

This specification shows an example of a flip-flop circuit. An exemplary flip-flop circuit may include a flip-flop data input terminal and a flip-flop data output terminal. The exemplary flip-flop circuit may further include a clock terminal for providing a first clock signal and a second clock signal that is an inversion signal of the first clock signal. Additionally, the exemplary flip-flop circuit may include a pass gate coupled between the flip-flop data input terminal and the first node. The pass gate may include a first P-channel gate terminal and a first N-channel gate terminal. The first P-channel gate terminal and the first N-channel gate terminal may be connected to the first clock signal and the second clock signal, respectively.

The exemplary flip-flop circuit may further include a passgate inverter coupled between the first node and the second node. The passgate inverter may include a first P-channel transistor, a second P-channel transistor, a first N-channel transistor, and a second N-channel transistor. The first P-channel transistor and the second N-channel transistor may be connected to the first node. The second P-channel transistor may be connected to the second clock signal and the first N-channel transistor may be connected to the first clock signal.

The exemplary flip-flop circuit may further include an inverter connected between the second node and the flip-flop data output terminal.

Furthermore, the exemplary flip-flop circuit may include one or more leakage compensation units coupled between the first node and the flip-flop data output terminal. Each of the leakage compensation units may include a third P-channel transistor and a third N-channel transistor.

To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed and this specification is intended to include all such aspects and their equivalents. intended.

The disclosed aspects will now be described in conjunction with the accompanying drawings, which are provided by way of illustration of the disclosed aspects, and are not limiting, and in which like numerals indicate like elements.
1 is a block diagram showing a conventional flip-flop circuit; FIG. FIG. 4 is a block diagram showing another conventional flip-flop circuit; FIG. 4 is a block diagram showing another conventional flip-flop circuit; It is a block diagram which shows the flip-flop circuit in one Example of this invention. 5 is a timing diagram showing signals of the flip-flop circuit of FIG. 4; FIG. 1 is a block diagram illustrating a flip-flop circuit in one or more embodiments of the invention; FIG.

Various aspects are now described with reference to the drawings. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects. It may be evident, however, that these aspects may be practiced without these specific details.

A flip-flop circuit may be designed to include two latches separated by a pass gate. For example, FIG. 1 shows a conventional flip-flop circuit 100 including passgate 102, latch 120, passgate 106, and latch 122 coupled in series. Passgates are sometimes called pass gates or transmission gates. Depending on the signal coupled to the N-channel terminal of the passgate and the P-channel, the passgate may be in a closed state (also called a "connected state") or an open state. For example, pass gate 102 of flip-flop circuit 100 is coupled between a data input terminal (shown as “D” in FIG. 1) and latch 120 . Another pass gate 106 is coupled between latch 120 and latch 122 . Latch 120 includes a pair of cross-coupled inverters 110 and 112 and pass gate 104 coupled to inverter 112 in feedback. Similar to latch 120 , latch 122 includes another pair of cross-coupled inverters 114 and 116 and pass gate 108 coupled to inverter 116 . As shown in FIG. 1, clock signal CK is inverted to produce inverted clock signal CPB which is provided to the N-channel terminals of pass gates 102, 104, 106 and 108, respectively. The inverted clock signal CPB may be further inverted to generate the clock pulse CP. A clock pulse CP may be provided to the P-channel terminal of each of pass gates 102, 104, 106 and 108. FIG.

In some examples, the conventional flip-flop circuit of FIG. 1 can function adequately to generate the correct signals. However, pass gates 104, 108 and inverters 112, 116 can cause high power consumption. The extra power consumption comes from the additional load on the clock distribution network due to the logic operations of the passgates and inverters. Therefore, another conventional flip-flop circuit without feedback structure has been proposed.

FIG. 2 is a block diagram showing another conventional flip-flop circuit 200. As shown in FIG. Flip-flop circuit 200 may include pass gate 202 , inverter 204 , pass gate 206 , and inverter 208 . Pass gate 202, inverter 204, pass gate 206, and inverter 208 may be connected in series. As shown, flip-flop 200 does not include a feedback circuit between nodes B1 and B2. As a result, the voltage at node B1 becomes unstable due to leakage from or into pass gate 202, causing an erroneous data value at the data output terminals of flip-flop circuit 200 (shown as "A2", "Q"). may occur.

FIG. 3 is a block diagram showing another conventional flip-flop circuit 300. As shown in FIG. As shown, flip-flop circuit 300 may include pass gate 302 , pass gate inverter 303 , and inverter 312 . In some examples, pass gate 302, pass gate inverter 303, and inverter 312 may be connected sequentially. Pass gate inverter 303 may be connected between pass gate 302 and inverter 312 . In some examples, the pass gate inverter 303 may include two P-channel transistors 304,306 and two N-channel transistors 308,310. A gate terminal of P-channel transistor 304 and a gate terminal of N-channel transistor 310 may be connected to node B1. The gate terminal of P-channel transistor 306 may be connected to inverted clock signal CPB, and the gate terminal of N-channel transistor 308 may be connected to clock signal CK or clock pulse CP.

Also, the source terminal or drain terminal of the P-channel transistor 304 may be connected to the power supply terminal VDD. The source or drain terminal of N-channel transistor 310 may be connected to the ground terminal. P-channel transistor 306 and N-channel transistor 308 are connected through their source or drain terminals and may be further connected to node B2.

Flip-flop circuit 300 may provide lower power consumption compared to flip-flop circuit 200 . In addition, leakage current from P-channel transistors 304 and 306 during the time interval when clock pulse CP or clock signal CK is low (value "0") and inverted clock signal CPB is high (value "1"). may increase the voltage at node B2, while leakage current from N-channel transistors 308 and 310 may decrease the voltage at node B2. Thus, the voltage at node B2 may be stabilized for a period of time. The period may be extended by additional capacitance. However, the voltage at node B1 can be relatively unstable because there is no feedback structure to stabilize the voltage at node B1.

FIG. 4 is a block diagram illustrating a flip-flop circuit 400 according to one embodiment of the invention. As shown, flip-flop circuit 400 may include pass gate 402 , leakage compensation unit 404 , pass gate inverter 406 , and inverter 408 . Passgate 402, passgate inverter 406, and inverter 408 may be connected in series. That is, the pass gate 402 may be connected between the flip-flop data input terminal and the first node B1. A pass gate inverter 406 may be connected between the first node B1 and the second node B2. An inverter 408 may be connected between the second node B2 and the flip-flop data output terminals A2/Q. Leakage compensation unit 404 may be connected in parallel with pass gate inverter 406 and inverter 408 between flip-flop data output terminal A2/Q and first node B1.

In some examples, the P-channel terminal of pass gate 402 may be coupled to clock pulse CP signal and the N-channel terminal of pass gate 402 may be coupled to inverted clock signal CPB.

Similar to passgate inverter 306 , passgate inverter 406 may further include P-channel transistor 410 , P-channel transistor 412 , N-channel transistor 414 , and N-channel transistor 416 . In some examples, P-channel transistor 410, P-channel transistor 412, N-channel transistor 414, and N-channel transistor 416 may be connected sequentially. A gate terminal of P-channel transistor 410 and a gate terminal of N-channel transistor 416 may be connected to a first node B1. The source or drain terminal of P-channel transistor 410 may be connected to power supply terminal VDD, and the source or drain terminal of N-channel transistor 416 may be connected to ground.

In a further example, the gate terminal of P-channel transistor 412 may be connected to inverted clock signal CPB and the gate terminal of N-channel transistor 414 may be connected to clock pulse CP. P-channel transistor 412 and N-channel transistor 414 may be connected to a second node B2 through source or drain terminals.

Unlike the flip-flop circuit 300, the flip-flop circuit 400 may include at least one leakage compensation unit 404 connected between the first node B1 and the flip-flop data output terminals A2/Q. In at least one example, leakage compensation unit 404 may include P-channel transistor 418 and N-channel transistor 420, which may be connected in series. The gate terminals of P-channel transistor 418 and N-channel transistor 420 may be connected to flip-flop data output terminals A2/Q. A source or drain terminal of P-channel transistor 418 may be connected to the first node B1.

During the time interval when clock pulse CP is high (value '1') and inverted clock signal CPB is low (value '0'), leakage current from pass gate 402 flows to the first node. It is possible to increase the voltage on B1. Therefore, the voltages at the first node B 1 and the flip-flop data output terminal A 2 /Q may no longer be equal, which may further cause leakage in the leakage compensation unit 404 . Leakage in the leakage compensation unit 404 can then cause the voltage at the first node B1 to drop. This allows the voltage at the first node B1 to be regulated to the correct value.

Similarly, if leakage current from pass gate 402 causes the voltage at first node B1 to drop, the voltages at first node B1 and flip-flop data output terminal A2/Q may no longer be equal. Leakage in the leakage compensation unit 404 can cause the voltage at the first node B1 to increase. The voltage at the first node B1 can then be adjusted to the correct value as well.

FIG. 5 is a timing diagram showing the signals of the flip-flop circuit of FIG.

As shown, at time points earlier than time point T1, leakage current from pass gate inverter 406 may cause the voltage at node B2 to gradually drop until time point T1. At time point T2, because clock signal CK and clock pulse CP are high and inverted clock signal CPB is low, leakage current in pass gate 402 can cause the voltage at first node B1 to drop.
However, the voltage difference between the first node B1 and the flip-flop data output terminal A2/Q may prevent leakage in the leakage compensation unit 404 and further decrease the voltage at the first node B1. Yes (indicated by the dashed line between T2 and T3). Thus, as shown, the voltage at the first node B1 can be maintained as high as possible from time point T2 to time point T3.

Similarly, between time points T3 and T4, leakage current from pass gate inverter 406 may cause the voltage at node B2 to gradually rise until time point T4.

Further, between time points T5 and T6, when clock signal CK and clock pulse CP are high and inverted clock signal CPB is low, leakage current in pass gate 402 causes Voltage may rise. In addition, the voltage difference between the first node B1 and the flip-flop data output terminal A2/Q can prevent the leakage in the leakage compensation unit 404 and further increase the voltage at the first node B1. Yes (indicated by the dashed line between T5 and T6).

FIG. 6 is a block diagram illustrating a flip-flop circuit 600 according to one or more embodiments of the invention.

As shown, flip-flop circuit 600 may include components similar to flip-flop circuit 400 shown in FIG. Flip-flop circuit 600 may include one or more leakage compensation units 604 . For example, the leakage compensation units may be connected in series, in parallel, or in any arrangement. Each of the leakage compensation units 604 may include a P-channel transistor and an N-channel transistor. The gate terminals of the P-channel and N-channel transistors may be connected to a first node B1, flip-flop data output terminals A2/Q or other leakage compensation units.

The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may also be applied to other aspects. Accordingly, the claims are not intended to be limited to the embodiments shown herein, but are to be accorded full scope consistent with the language of the claims, wherein: References to elements in the singular are not intended to mean "one and only", but rather "one or more," unless specified otherwise. Unless otherwise specified, the term "some" means one or more. All structural and functional equivalents known or later to become known to those skilled in the art to the elements of the various aspects described herein are expressly incorporated herein by reference. is intended to be covered by the claims. Moreover, nothing disclosed herein is intended to be made available to the public, whether or not such disclosure is explicitly recited in the claims. No claim element should be construed as "means plus function" unless that element is explicitly recited using the phrase "means for".

Moreover, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless stated otherwise, or clear from context, the phrase "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, the statement "X uses A or B" is satisfied if "X uses A", "X uses B", or "X uses both A and B". It will be. Further, as used in this application and the appended claims, the articles "a" and "an" generally refer to " should be construed to mean "one or more".

Claims (11)

A flip-flop circuit,
a flip-flop data input terminal and a flip-flop data output terminal;
a clock terminal for providing a first clock signal and a second clock signal that is an inverse of said first clock signal;
A pass gate coupled between said flip-flop data input terminal and a first node, said first P-channel gate terminal coupled to said first clock signal and said second clock signal, respectively. the pass gate comprising one N-channel gate terminal;
A pass gate inverter coupled between the first node and the second node, comprising a first P-channel transistor, a second P-channel transistor, a first N-channel transistor, and a second N-channel transistor. channel transistors, wherein the first P-channel transistor and the second N-channel transistor are connected to the first node, and the second P-channel transistor is connected to the second clock signal. the pass gate inverter, wherein the first N-channel transistor is connected to the first clock signal;
an inverter connected between the second node and the flip-flop data output terminal;
one or more leakage compensation units coupled between the first node and the flip-flop data output terminal, each of the one or more leakage compensation units comprising a third P-channel transistor and a third the one or more leakage compensation units comprising three N-channel transistors;
The flip-flop circuit, comprising: 2. The flip-flop circuit of claim 1, wherein the drain terminal of said first P-channel transistor is connected to said first node. 2. The flip-flop circuit of claim 1, wherein the drain terminal of said second N-channel transistor is connected to said first node. 2. The flip-flop circuit of claim 1, wherein the drain terminal of said second P-channel transistor is connected to said second clock signal. 2. The flip-flop circuit of claim 1, wherein the drain terminal of said first N-channel transistor is connected to said first clock signal. drain terminals of the third P-channel transistor and the third N-channel transistor are connected to the flip-flop data output terminal;
2. The circuit of claim 1, wherein said third P-channel transistor is connected to said first node and said third N-channel transistor is connected to said flip-flop data output terminal. flip-flop circuit. drain terminals of the third P-channel transistor and the third N-channel transistor are connected to the flip-flop data output terminal;
2. The circuit of claim 1, wherein said third N-channel transistor is connected to said first node and said third P-channel transistor is connected to said flip-flop data output terminal. flip-flop circuit. drain terminals of the third P-channel transistor and the third N-channel transistor are connected to the first node;
2. The circuit of claim 1, wherein said third N-channel transistor is connected to said first node and said third P-channel transistor is connected to said flip-flop data output terminal. flip-flop circuit. drain terminals of the third P-channel transistor and the third N-channel transistor are connected to the first node;
2. The circuit of claim 1, wherein said third P-channel transistor is connected to said first node and said third N-channel transistor is connected to said flip-flop data output terminal. flip-flop circuit. 2. The flip-flop circuit of claim 1, wherein said one or more leakage compensation units are connected sequentially. 2. The flip-flop circuit of claim 1, wherein said one or more leakage compensation units are connected in parallel.

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