CN112385145A

CN112385145A - Low power flip-flop circuit

Info

Publication number: CN112385145A
Application number: CN201980044915.3A
Authority: CN
Inventors: M·毛
Original assignee: Xiaolong Intellectual Property Holding Co ltd
Current assignee: Xiaolong Intellectual Property Holding Co ltd
Priority date: 2019-06-04
Filing date: 2019-08-31
Publication date: 2021-02-19
Also published as: KR102478168B1; CA3103827C; KR20210035098A; WO2020247005A1; EP3981073A1; JP2022534821A; CA3103827A1

Abstract

Aspects for a flip-flop circuit are described herein. As an example, these aspects may include a transmission gate, a transmission gate inverter, a leakage compensation unit, and an inverter. The transmission gate may be coupled between the flip-flop data input terminal and the first node. The transmission gate inverter and the inverter may be sequentially connected between the first node and the flip-flop data output terminal. The leakage compensation unit may be connected between the first node and the flip-flop data output terminal in parallel with the transmission gate inverter and the inverter.

Description

Low power flip-flop circuit

Background

Flip-flops may refer to sequential circuits that store a "high" value (voltage high or logic 1) or a "low" value (voltage low or logic 0). The flip-flop may store the next value depending on the value of one or more input signals. In general, a flip-flop may include data, clock, set and/or reset input signals.

A data (generally indicated by "D") input signal is typically clocked into a flip-flop upon receipt of a given clock edge. The set (generally denoted by "S") and reset (generally denoted by "R") input signals are generally not clocked, which means that when the set and reset signals become active (e.g., go high), the stored value changes immediately without waiting for the arrival of a clock edge. Flip-flops are typically master-slave latch structures. Each latch is active (transparent) during a logic high or logic low phase (non-edge). On a rising (triggering) edge, the master latch will latch in and store the data value, and the slave latch will become active (transparent) and pass the value to the output. Assuming the active phase for the master latch is 0, on the falling edge the master latch will become active (transparent) to receive the next value and the slave latch will latch the contents latched by the master latch to continue outputting the value stored in the master latch. The output will only change on each triggering edge. The active set signal forces the stored value (generally denoted by "Q") to be set high regardless of the previously stored value. The active reset signal forces the stored value to be set low regardless of the previously stored value. In a set/reset flip-flop (i.e., a flip-flop having both set and reset input signals), the set and reset signals are typically limited so that at most one of them may be active at any given time. Since flip-flops are an essential part of modern digital designs, there is always a need to minimize their power consumption and area. A flip-flop design is presented that will reduce its power consumption and area compared to conventional designs.

Disclosure of Invention

The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

This disclosure presents examples of flip-flop circuits. An example flip-flop circuit may include a flip-flop data input terminal and a flip-flop data output terminal. The example flip-flop circuit may further include a clock terminal that provides a first clock signal and a second clock signal, wherein the second clock signal is an inverse of the first clock signal. Further, the example flip-flop circuit may include a transmission gate coupled between the flip-flop data input terminal and the first node. The transfer gate may include a first P-channel gate terminal and a first N-channel gate terminal. The first P-channel gate terminal and the first N-channel gate terminal may be connected to a first clock signal and a second clock signal, respectively.

The example flip-flop circuit may further include a transmission gate inverter coupled between the first node and the second node. The transmission gate inverter may include a first P-channel transistor, a second P-channel transistor, a first N-channel transistor, and a second N-channel transistor. The first P-channel transistor and the second N-channel transistor may be connected to the first node. The second P-channel transistor may be connected to the second clock signal, and the first N-channel transistor may be connected to the first clock signal.

The example flip-flop circuit may further include an inverter connected between the second node and the flip-flop data output terminal.

Still further, an example flip-flop circuit may include one or more leakage compensation cells coupled between the first node and the flip-flop data output terminal. Each of the leakage compensation units may include a third P-channel transistor and a third N-channel transistor.

To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed and the description is intended to include all such aspects and their equivalents.

Drawings

The disclosed aspects will hereinafter be described in conjunction with the appended drawings, provided to illustrate and not to limit the disclosed aspects, wherein like designations denote like elements, and:

FIG. 1 is a block diagram illustrating a conventional flip-flop circuit;

fig. 2 is a block diagram showing another conventional flip-flop circuit;

FIG. 3 is a block diagram illustrating another conventional flip-flop circuit;

FIG. 4 is a block diagram illustrating a flip-flop circuit according to one embodiment of the present invention;

FIG. 5 is a timing diagram showing signals of the flip-flop circuit of FIG. 4; and

FIG. 6 is a block diagram illustrating a flip-flop circuit in accordance with one or more embodiments of the present invention.

Detailed Description

Various aspects are now described with reference to the drawings. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects. It may be evident, however, that such aspect(s) may be practiced without these specific details.

The flip-flop circuit may be designed to include two latches separated by a transmission gate. For example, fig. 1 illustrates a conventional flip-flop circuit 100 that includes a transmission gate 102, a latch 120, a transmission gate 106, and a latch 122 coupled together in sequence (sequentially). The transmission gate may also be referred to as a pass gate or a transfer gate. The transmission gate may be in a closed state (may also be referred to as a "connected state") or an open state according to signals coupled to the N-channel terminal and the P-channel of the transmission gate. For example, transmission gate 102 of flip-flop circuit 100 is coupled between a data input terminal (shown as "D" in fig. 1) and latch 120. Another transmission gate 106 is coupled between latch 120 and latch 122. Latch 120 includes a pair of cross-coupled inverters 110 and 112 and transmission gate 104 coupled in feedback to inverter 112. Similar to latch 120, latch 122 includes another pair of cross-coupled inverters 114 and 116 and transmission gate 108 coupled to inverter 116. As shown in fig. 1, the clock signal CK is inverted to generate an inverted clock signal CPB, which is provided to respective N-channel terminals of the transfer gates 102, 104, 106, and 108. The inverted clock signal CPB may be further inverted to generate the clock pulse CP. Clock pulses CP may be provided to respective P-channel terminals of transmission gates 102, 104, 106, and 108.

In some examples, the conventional flip-flop of fig. 1 may function properly to generate the correct signal. However, the transmission gates 104 and 108 and the inverters 112 and 116 may cause high power consumption. The additional power consumption comes from the additional loading of the transmission gates on the clock distribution network and the logic operation of the inverters. Therefore, another conventional flip-flop circuit having no feedback structure is proposed.

Fig. 2 is a block diagram illustrating another conventional flip-flop circuit 200. The flip-flop circuit 200 may include a transmission gate 202, an inverter 204, a transmission gate 206, and an inverter 208. The transmission gate 202, the inverter 204, the transmission gate 206, and the inverter 208 may be connected in sequence. As shown, the flip-flop 200 does not include a feedback loop between the node B1 and the node B2. Thus, the voltage at node B1 is unstable due to leakage from or to transmission gate 202 and causes erroneous data values at the data output terminals (shown as "A2" and "Q") of flip-flop circuit 200.

Fig. 3 is a block diagram illustrating another conventional flip-flop circuit 300. As depicted, flip-flop circuit 300 may include a transmission gate 302, a transmission gate inverter 303, and an inverter 312. In some examples, transmission gate 302, transmission gate inverter 303, and inverter 312 may be connected in sequence. Transmission gate inverter 303 may be connected between transmission gate 302 and inverter 312. In some examples, the pass-gate inverter 303 may include two P-

channel transistors

304 and 306, and two N-

channel transistors

308 and 310. The gate terminal of P-channel transistor 304 and the gate terminal of N-channel transistor 310 may be connected to node B1. The gate terminal of P-channel transistor 306 may be connected to inverted clock signal CPB and the gate terminal of N-channel transistor 308 may be connected to clock signal CK or clock pulse CP.

Further, a source terminal or a drain terminal of the P-channel transistor 304 may be connected to the power supply terminal VDD. A source terminal or a drain terminal of the N-channel transistor 310 may be connected to a ground terminal. P-channel transistor 306 and N-channel transistor 308 may be connected by their source or drain terminals, and may be further connected to node B2.

Flip-flop circuit 300 may result in lower power consumption compared to flip-flop circuit 200. Furthermore, in time intervals in which clock pulse CP or clock signal CK is low ("0") and inverted clock signal CPB is high ("1"), leakage current from P-

channel transistors

304 and 306 may cause the voltage at node B2 to increase; however, leakage current from N-

channel transistors

308 and 310 may cause the voltage at node B2 to decrease. As such, the voltage at node B2 may stabilize for a period of time. This time can be extended by an extra capacitor. However, because there is no feedback structure to stabilize the voltage at node B1, the voltage at node B1 may be relatively unstable.

Fig. 4 is a block diagram illustrating a flip-flop circuit 400 according to one embodiment of the present invention. As depicted, the flip-flop circuit 400 may include a transmission gate 402, a leakage compensation unit 404, a transmission gate inverter 406, and an inverter 408. The transmission gate 402, the transmission gate inverter 406, and the inverter 408 may be connected in sequence. In other words, the transmission gate 402 may be connected between the flip-flop data input terminal and the first node B1. The transmission gate inverter 406 may be connected between the first node B1 and the second node B2. The inverter 408 may be connected between the second node B2 and the flip-flop data output terminal a 2/Q. The leakage compensation unit 404 may be connected between the flip-flop data output terminal a2/Q and the first node B1 in parallel with the transmission gate inverter 406 and the inverter 408.

In some examples, a P-channel terminal of transfer gate 402 may be coupled to clock pulse CP signal and an N-channel terminal of transfer gate 402 may be coupled to inverted clock signal CPB.

Similar to the transmission gate inverter 306, the transmission gate inverter 406 may also include a P-channel transistor 410, a P-channel transistor 412, an N-channel transistor 414, and an N-channel transistor 416. In some examples, P-channel transistor 410, P-channel transistor 412, N-channel transistor 414, and N-channel transistor 416 may be connected in sequence. The gate terminal of P-channel transistor 410 and the gate terminal of N-channel transistor 416 may be connected to a first node B1. The source or drain terminal of the P-channel transistor 410 may be connected to the power supply terminal VDD; a source or drain terminal of the N-channel transistor 416 may be connected to a ground terminal.

In a further example, the gate terminal of P-channel transistor 412 may be connected to inverted clock signal CPB and the gate terminal of N-channel transistor 414 may be connected to clock pulse CP. The P-channel transistor 412 and the N-channel transistor 414 may be connected to the second node B2 through source or drain terminals.

Unlike the flip-flop circuit 300, the flip-flop circuit 400 may include at least one leakage compensation unit 404 connected between the first node B1 and the flip-flop data output terminal a 2/Q. In at least one example, leakage compensation unit 404 may include a P-channel transistor 418 and an N-channel transistor 420, which may be connected in sequence. The gate terminals of P-channel transistor 418 and N-channel transistor 420 may be connected to flip-flop data output terminal a 2/Q. A source or drain terminal of the P-channel transistor 418 may be connected to the first node B1.

In the time interval when clock pulse CP is high ("1") and inverted clock signal CPB is low ("0"), leakage current from transmission gate 402 may cause the voltage at first node B1 to increase. Therefore, the voltage at the first node B1 and the voltage at the flip-flop data output terminal A2/Q may no longer be equal, which may further cause leakage at the leakage compensation unit 404. The leakage at the leakage compensation unit 404 may then cause the voltage at the first node B1 to decrease. Therefore, the voltage at the first node B1 may be adjusted to the correct value.

Similarly, when the leakage current from the transmission gate 402 causes the voltage at the first node B1 to decrease, the voltage at the first node B1 and the voltage at the flip-flop data output terminal a2/Q may no longer be equal. The leakage at the leakage compensation unit 404 may increase the voltage at the first node B1. The voltage at the first node B1 may then similarly be adjusted to the correct value.

Fig. 5 is a timing diagram showing signals of the flip-flop circuit of fig. 4.

As depicted, before time point T1, the voltage at node B2 gradually drops due to leakage current from the transmission gate inverter 406 until time point T1. At a time point T2, the clock signal CK and the clock pulse CP are high, and the inverted clock signal CPB is low, the leakage current at the transmission gate 402 may cause the voltage at the first node B1 to decrease. However, the difference in the voltages at the first node B1 and the flip-flop data output terminal a2/Q may cause leakage at the leakage compensation unit 404 and further prevent the voltage at the first node B1 from dropping (as shown in the dashed line between T2 and T3). Therefore, the voltage at the first node B1 may be maintained high from time point T2 to time point T3 as shown.

Similarly, between the time point T3 and the time point T4, the voltage at the node B2 may gradually rise due to the leakage current from the transmission gate inverter 406 until the time point T4.

Further, between the time point T5 and the time point T6, the clock signal CK and the clock pulse CP are high, and the inverted clock signal CPB is low, the leakage current at the transmission gate 402 may cause the voltage at the first node B1 to increase. The difference in the voltages at the first node B1 and the flip-flop data output terminal a2/Q may cause leakage at the leakage compensation unit 404 and further prevent the voltage at the first node B1 from increasing (as shown in the dashed line between T5 and T6).

Fig. 6 is a block diagram illustrating a flip-flop circuit 600 in accordance with one or more embodiments of the present invention.

As depicted, the flip-flop circuit 600 may include similar components as the flip-flop circuit 400 according to fig. 4. The flip-flop circuit 600 may include one or more leakage compensation units 604. For example, the leakage compensation units may be connected in sequence, in parallel, or in any connection. Each of the leakage compensation units 604 may include a P-channel transistor and an N-channel transistor. The gate terminals of the P-channel transistor and the N-channel transistor may be connected to the first node B1, the flip-flop data output terminal a2/Q, or other leakage compensation unit.

The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean "one and only one" unless specifically so stated, but rather "one or more. The term "some" means one or more unless specifically stated otherwise. All structural and functional equivalents to the elements of the various aspects described herein that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. Unless a claim element is explicitly recited using the phrase "as a means of … …," the element should not be construed as a means plus function.

Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, the phrase "X employs A or B" is intended to mean any of the naturally included permutations, unless specifically stated otherwise or clear from the context. That is, the phrase "X employs A or B" is satisfied in either case: x is A; b is used as X; or X employs both A and B. In addition, the articles "a" and "an" as used in this application or the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form.

Claims

1. A flip-flop circuit comprising

A flip-flop data input terminal and a flip-flop data output terminal;

a clock terminal providing a first clock signal and a second clock signal, wherein the second clock signal is an inverse of the first clock signal;

a transmission gate coupled between the flip-flop data input terminal and a first node, wherein

The transfer gate includes a first P-channel gate terminal and a first N-channel gate terminal, and

said first P-channel gate terminal and said first N-channel gate terminal are connected to said first clock signal and said second clock signal, respectively;

a transmission gate inverter coupled between the first node and a second node,

wherein the transmission gate inverter includes a first P-channel transistor, a second P-channel transistor, a first N-channel transistor, and a second N-channel transistor,

wherein the first P-channel transistor and the second N-channel transistor are connected to the first node,

wherein the second P-channel transistor is connected to the second clock signal, an

Wherein the first N-channel transistor is connected to the first clock signal;

an inverter coupled between the second node and the flip-flop data output terminal; and

one or more leakage compensation cells coupled between the first node and the flip-flop data output terminal, wherein each of the one or more leakage compensation cells includes a third P-channel transistor and a third N-channel transistor.

2. The flip-flop circuit of claim 1, wherein a drain terminal of the first P-channel transistor is connected to the first node.

3. The flip-flop circuit of claim 1, wherein a drain terminal of the second N-channel transistor is connected to the first node.

4. The flip-flop circuit of claim 1, wherein a drain terminal of the second P-channel transistor is connected to the second clock signal.

5. The flip-flop circuit of claim 1, wherein a drain terminal of the first N-channel transistor is connected to the first clock signal.

6. The flip-flop circuit of claim 1,

wherein drain terminals of the third P-channel transistor and the third N-channel transistor are connected to the flip-flop data output terminal,

wherein the third P-channel transistor is connected to the first node, an

Wherein the third N-channel transistor is connected to the flip-flop data output terminal.

7. The flip-flop circuit of claim 1,

wherein the third N-channel transistor is connected to the first node, an

Wherein the third P-channel transistor is connected to the flip-flop data output terminal.

8. The flip-flop circuit of claim 1,

wherein drain terminals of the third P-channel transistor and the third N-channel transistor are connected to the first node,

wherein the third N-channel transistor is connected to the first node, an

9. The flip-flop circuit of claim 1,

wherein the third P-channel transistor is connected to the first node, an

10. The flip-flop circuit of claim 1, wherein the one or more leakage compensation cells are connected in sequence.

11. The flip-flop circuit of claim 1, wherein the one or more leakage compensation cells are connected in parallel.