JP3381875B2 - Sequential circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequential circuit, and in particular, during a power down period, it keeps the immediately preceding operating state to stop the normal operation, and at the same time, provides a low threshold voltage for high speed operation. The present invention relates to a sequential circuit that shifts to a low power consumption state by cutting off power supply to a predetermined internal circuit composed of a MOSFET included therein.

[0002]

2. Description of the Related Art A conventional sequential circuit of this type has a characteristic that a MOSFET having a low threshold voltage has a relatively large leak current flowing between a drain and a source when it is non-conductive. During the down period,
The power supply voltage side and the ground potential side of a circuit composed of a low threshold voltage MOSFET are cut off by MOSFETs each having a high threshold voltage with a small leak current.

FIG. 12 is a block diagram showing an outline of a D flip-flop as a conventional sequential circuit. In FIG. 12, 10 is an internal signal CK and its inversion based on a clock signal CLK input from the outside during normal operation. A clock holding circuit that generates a signal CKN and holds the internal signals CK and CKN immediately before the start in response to the start of power down, and 20 latches an external data signal D based on the internal signals CK and CKN during normal operation. It is an output latch circuit, and both are composed of low threshold voltage MOSFETs.

PD and PDN are external power-down control signals for instructing the power-down period of the circuit and its inverted signals. Q10A and Q10B are predetermined parts of the clock holding circuit 10 according to the power-down control signals PD and PDN. High threshold MOSFETs Q20A, Q20 for cutting off the supply of power supply voltage VDD and ground potential GND to
B is a high threshold MOSFET that cuts off the supply of the power supply voltage VDD and the ground potential GND to a predetermined portion of the latch circuit 20 according to the power-down control signals PD and PDN. MOS
The FETs Q10A, Q10B, Q20A, Q20B are turned off, and the clock holding circuit 1
0 and a predetermined portion of the latch circuit 20 are shut off, and the low threshold voltage MOSF in each circuit is shut off.
The leakage current due to ET is suppressed.

FIG. 13 is an explanatory diagram (truth table) showing the operation of a general D flip-flop, in which the data signal D is latched in synchronization with the rising edge of the clock signal CLK. Output as output signal Q and its inverted signal QN, and also clock signal CLK
At the falling edge of, the output signals Q and QN do not change and the previous state is maintained. Note that FIG.
, "0" and "1" indicate the low level and high level of the input signal, respectively, and "X" indicates that the input signal is independent of the output signals Q and QN (Irreleva
nt).

FIG. 14 is a circuit diagram of a conventional clock holding circuit. In FIG. 14, INV11 is a clock signal CL.
An inverter that inverts and outputs K, SW11 is a switch that shuts off the output of the inverter INV11 during power down,
INV12 is an inverter that inverts the output of the switch SW11 and outputs an internal signal CK, INV13, INV14.
Is an inverter that inverts the outputs of the switch SW11 and the inverter INV12, and SW12 is in a conductive state “ON” at the time of power down, and the inverters INV13 and INV1
4 is a switch that forms a flip-flop that holds the internal signals CKN and CK by the inverter INV1.
1, INV12 and switches SW11 and SW12 are each composed of a low threshold voltage MOSFET, and inverters INV13 and INV14 are respectively composed of a high threshold voltage MOSFET.

During normal D flip-flop operation, the switch SW11 is controlled to be "ON" and the switch SW12 is controlled to be "OFF".
The LK is inverted and output by the inverter INV11 and output as the internal signal CKN, and further inverted by the inverter INV12 and output as the internal signal CK. High threshold voltage MOSFETs Q11A and Q12A (Q1 in FIG. 12) are provided on the power supply voltage VDD side and the ground potential GND side of the inverters INV11 and INV12, respectively.
10A), Q11B, Q12B (Q10 in FIG. 12)
(Corresponding to B) is provided, these MOSFETs are controlled to be “OFF” at the time of power down, and the leak current consumed by the inverters INV11 and INV12 is suppressed.

As a result, during power down, the MOS is
Since the FETs Q11A and Q11B are each controlled to be "OFF", the power supply to the inverter INV11 is cut off, and the switch SW11 is controlled to be "OFF" so that the clock signal CLK is cut off. Also MO
Since the SFETs Q12A and Q12B are controlled to be "OFF", respectively, the power supply to the inverter INV12 is cut off, and the switch SW12 is controlled to "ON" so that the inverters INV13 and I12 are constantly supplied with power.
A flip-flop is formed by the NV 14, and the states of the internal signals CK and CKN immediately before power down are held and output to the latch circuit 20, and the latch circuit 2 at the end of power down, that is, when normal operation is restored.
A malfunction due to a mismatch with the state of 0 is avoided.

FIG. 15 is a circuit diagram of a conventional latch circuit. In FIG. 15, 20A is a master latch circuit which is provided in the preceding stage and latches a data signal D based on internal signals CK and CKN from a clock holding circuit 10. Reference numeral 20B is a slave latch circuit which is provided in the subsequent stage and which latches the output of the master latch circuit 20A based on the internal signals CK and CKN and outputs the output signals Q and QN. In the master latch circuit 20A, INV21 is an inverter that inverts and outputs the data signal D, and SW21 is a switch that shuts off the output of the inverter INV21 when the internal signal CK is at high level "1" (internal signal CKN is at low level "0"). , INV2
Reference numeral 2 is an inverter that inverts the output of SW21 and outputs it as a master latch signal.

INV25 and INV26 are switches SW2
1 and an inverter that inverts the output of the inverter INV22, SW22 is "ON" when the internal signal CK is "1".
The inverters INV25 and INV26 are switches that form a flip-flop that holds the master latch signal. The inverters INV21 and INV22 and the switches SW21 and SW22 are MOSFETs of low threshold voltage, and the inverter INV2.
5, INV26 is high threshold voltage MOSFE
It is composed of T. In the slave latch circuit 20B, INV23 is an inverter that inverts and outputs the master latch signal, SW23 is a switch that shuts off the output of the inverter INV23 when the internal signal CK is "0", IN
V24 is an inverter that inverts the output of SW23 and outputs it as a slave latch signal.

INV27 and INV28 are switches SW2
3 and an inverter that inverts the output of the inverter INV24, SW24 is "ON" when the internal signal CK is "0".
The inverters INV27, INV28 are switches forming a flip-flop for holding the slave latch signal, and the inverters INV23, INV24,
The switches SW23 and SW24 are each composed of a low threshold voltage MOSFET, and the inverter INV2
7 and INV28 are high threshold voltage MOSFE, respectively.
It is composed of T. Furthermore, INV29, INV3
Reference numeral 0 denotes an inverter that outputs output signals Q and QN by inverting the input and output (slave latch signal) of the inverter INV24, both of which are composed of low threshold voltage MOSFETs.

In the normal D flip-flop operation, in the master latch circuit 20A, the switch SW21 is controlled to "ON" and the switch SW22 is controlled to "OFF" when the internal signal CK is "0".
The data signal D is inverted and output by the inverter INV21 and then inverted and output by the inverter INV22 as a master latch signal, and when the internal signal CK becomes “1”, that is, at the rising edge of the internal signal CK, the switch SW21 is turned on. The switch SW22 is controlled to be "OFF" and the switch SW22 is controlled to be "ON", and the data signal D immediately before the internal signal CK becomes "1" is held by the flip-flop composed of the inverters INV22 and INV26, and the master latch signal. Is output as.

In the slave latch circuit 20B, when the internal signal CK is "1" (when the switch SW21 is "OFF"), the switch SW23 is controlled to "ON" and the switch SW24 is controlled to "OFF". Therefore, when the master latch signal is inverted and output by the inverter INV23 and is further inverted and output as the slave latch signal by the inverter INV24, and then the internal signal CK becomes “0” (the switch SW21 is “ON”). In the case of), that is, at the falling edge of the internal signal CK, the switch SW23 is “OFF”.
And the switch SW24 is controlled to be “ON” and the flip-flop composed of the inverters INV24 and INV28 holds the master latch signal immediately before the internal signal CK becomes “0”, and the inverter INV
It is output as output signals Q and QN via 29 and INV30.

Therefore, at the rising edge of the internal signal CK, the data signal D is latched by the master latch circuit 20A and output as a master latch signal, and at the subsequent falling edge of the internal signal CK, the master latch signal becomes the slave latch signal. The data signal D is latched by the circuit 20B and output as the output signals Q and QN, a new data signal D is read by the master latch circuit 20A, and thereafter, the data signal D is sequentially synchronized with the rising and falling of the internal clock CK. It will be latched.

Further, the inverters INV21 to INV24
Of the high threshold voltage MOSFETs Q21A and Q22A, respectively on the power supply voltage VDD side and the ground potential GND side of
Q23A, Q24A (corresponding to Q10A in FIG. 12), Q2
1B, Q22B, Q23B, Q24B (Q10 of FIG. 12
(Corresponding to B) is provided, and the inverter INV2
9, power supply voltage VDD side of INV30 and ground potential GND
On the side, high threshold voltage MOSFET Q29
A, Q29B, Q30A, Q30B are provided,
At the time of power down, these MOSFETs are simultaneously controlled to be “OFF” by the power down signals PD and PDN, and the inverters INV21 to INV24 and INV2.
9. The leak current consumed by INV30 is suppressed.

As a result, at the time of power down, the inverters INV21 to INV24 and INV29, INV
The power supply to 30 is cut off to enter the low power consumption state, and the clock holding circuit 10 causes the internal signals CK and C
Since KN is held, the internal state of the latch circuit 20 does not change, and even if the master latch circuit 20A or the slave latch circuit 20B is in the latch state in which the input side is cut off, the inverter is always supplied with power. INV2
5, INV26 or inverters INV27, INV2
The master latch signal or the slave latch signal is held by the flip-flop circuit formed by 8, and the state in the D flip-flop circuit at the start of power down, that is, at the time of stopping normal operation and at the end of power down, that is, at the time of restoring normal operation The malfunction due to the mismatch between the output signals Q and QN can be avoided.

[0017]

Therefore, in such a conventional sequential circuit, when the power down control signal PD input from the outside is controlled to "0" (power down control signal PDN is "1"). The clock holding circuit 10
In addition, since the power supply to the inverters formed by the low threshold voltage MOSFETs in the slave latch circuit 20 is cut off all at once, the clock is held at the end of power down, that is, when the normal operation is restored. Due to the difference in the number of elements between the circuit 10 and the latch circuit 20 and the difference in the capacitance component between the power supply voltage VDD and the ground potential GND, the power supply voltage of the clock holding circuit 10 is changed to the latch circuit 20.
If there is a tendency to recover faster, the latch circuit 20
There is a problem that an internal signal different from the internal state immediately before the start of the power down held in is supplied, resulting in a malfunction at the end of the power down. The present invention is intended to solve such a problem, and provides a sequential circuit that can operate at a high speed with a low power supply voltage and can perform a reliable and stable power-down operation to reduce power consumption. Is intended.

[0018]

In order to achieve such an object, the sequential circuit according to the present invention has a clock circuit during normal operation.
Generate a predetermined internal signal based on the lock signal, and
First power down indicated by the wardown control signal
Holds the immediately preceding internal signal in response to the start of the period, and
Retains the internal signal at the end of the wardown period
Clock holding circuit and internal signal during normal operation
Latched by the second power-down control signal.
Immediately before the start of the second power down period
To keep the parts operating and to shut off the power supply
Latch operation is stopped by the
Resume the power supply and restart the latch operation according to the end
A sequential circuit having a latch circuit and a first power
The down control signal indicates the first power down period as the first
Second power indicated by the second power-down control signal
Power-down period that ends after the end of the down period
Is used. Also, the first power
The down control signal indicates the first power down period as the first
Second power indicated by the second power-down control signal
Starts before the start of the down period and
Power down that ends after the end of the wardown period
It uses a signal having a period. Further, the latch circuit has output setting means for forcibly outputting a predetermined output signal in accordance with the output setting signal during normal operation, and power is supplied to the output setting means at the start of the first power down period. The operation of the output setting means is stopped by cutting off, and the operation stop of the output setting means is released by restoring the power supply to the output setting means at the end of the first power down period. is there. Also the first
Set the first power-down period to the power-down control signal.
The second power down control signal
First power delayed by a predetermined time from the power down period
A signal having a down period is used. Also,
The first power-down control signal is the first power-down period.
As indicated by the second power down control signal
Power starting before the start of the second power down period
It uses a signal having a down period.

[0019]

Therefore, at the end of the power down period, after the power supply to the latch circuit is restored, the holding of the internal signal by the clock holding circuit is released. At the start of the power down period, the latch operation is stopped after the clock holding circuit holds the internal signal. Further, at the start of the power down period, the operation of the output setting means is stopped before the stop of the latch operation, and at the end of the power down period, the stop of the operation of the output setting means is released before the restart of the latch operation.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block configuration diagram showing an outline of a D flip-flop as a sequential circuit which is an embodiment of the present invention, and the same or equivalent portions as those in the above description (FIG. 12) are denoted by the same reference numerals. In the figure, the clock hold circuit 10, 20 is a latch circuit, PD1, PD1N the power-down control signal Contact <br/> and its inverted signal from the outside which instructs power-down circuit, PD2, PD2N is PD1, PD1
A predetermined time ta from the end timing of the N power down period
Delayed power-down control signal indicating the end power down period, Q 10C, Q10D the power-down control signal P
It is a high threshold MOSFET that cuts off the supply of the power supply voltage VDD and the ground potential GND to a predetermined portion of the clock holding circuit 10 according to D2 and PD2N.

FIG. 2 is a circuit diagram showing the clock holding circuit 10. The circuit configuration itself is the same as the circuit diagram of the clock holding circuit shown in FIG. 14, but is composed of MOSFETs of low threshold voltage. Inverter INV11,
The INV12 and the switches SW11 and SW12 are controlled by the power down control signals PD2 and PD2N. In addition, the inverters INV11, INV12
Of the high-threshold voltage MOSFETs Q11C and Q12C on the power supply voltage VDD side and the ground potential GND side, respectively.
(Corresponding to Q10C in Fig. 1), Q11D, Q12D (Fig. 1
(Corresponding to Q10D) is provided, these MOSFETs are controlled to be “OFF” at the time of power down, and the leak current consumed by the inverters INV11 and INV12 is suppressed.

FIG. 3 shows the power down control signals PD1 and P.
Is a timing chart showing a relationship between D2, T1 is between the power-down period indicated by the power-down control signal PD1 is input from the outside, T 2 is between the power-down period of the power-down control signal PD2, a power-down period T2 The power down period is ended with a delay of time ta from the end timing of the power down period T1.

Further, FIG. 4 shows a power down control signal PD2.
And a power down control signal PD1 is inverted by an inverter INV41 to become a power down control signal PD2N delayed from the power down control signal PD1 by an operation delay of the inverter INV41, and an inverter INV42. And is output as a power down control signal PD2 delayed by the operation delay of the inverter INV42 from the power down control signal PD2N. Therefore, the time ta is defined by the sum of the operation delay times in the inverters INV41 and INV42, and particularly the inverter INV41
Is composed of a plurality of inverters, the power-down control signals PD2 and PD2N having a desired delay time are provided.
Can be generated.

Now, the latch circuit 20 is composed of a circuit similar to that of FIG. 15 described above, and in particular, the power down control signals PD1 and PDN are used instead of the power down control signals PD and PDN.
When PD1N is supplied, the power-down control signal PD1 becomes “0” first at the end of power-down, and the power supply voltage VDD is supplied to the inverter composed of the MOSFET of the low threshold voltage in the latch circuit 20 to restore the normal operation. It At this time, the power down control signals PD2, PD2N supplied to the clock holding circuit 10 indicate that the power down period is still in progress, and the internal signals CK, CK are shown.
N is held in the state immediately before the start of power down.

As a result, the latch circuit 20 to which the power supply voltage has been re-supplied is supplied to the internal signal C immediately before the start of power down.
Since K and CKN are supplied stably, the latch circuit 20 recovers to the state immediately before the start of power down without malfunctioning, and after a lapse of time ta, the power down control signals PD2 and PD2N indicate the end of power down. As shown, MOSFETs Q11C, Q11D, Q12C,
Each Q12D is controlled to be "ON" and the inverter I
The power supply voltage VDD is supplied to NV11 and INV12, and the switch SW11 is turned "ON".
12 are controlled to be “OFF” respectively, and internal signals CK,
The holding of CKN is released, the internal signals CK and CKN are newly generated based on the clock signal CLK input from the outside, and are supplied to the latch circuit 20, and the D flip-flop operation for the data signal D is restarted. It will be one.

Therefore, when the power supply to the latch circuit 20 is restored, the clock holding circuit 10 shifts to the latch circuit 20.
Internal signals CK and CKN immediately before the start of power down
Is stably supplied, the latch circuit 20 is restored to the state immediately before the start of power down without malfunctioning, and then the clock holding circuit 10 is supplied with power to generate a new clock signal CLK from the outside. Internal signal C
The K and CKN are supplied to the latch circuit 20, and the latch circuit 20 is supplied at the end of the power down period.
Internal operation state and clock holding circuit 1
It is possible to completely prevent a malfunction due to a mismatch with the internal signals CK and CKN from 0, and it is possible to realize an accurate and stable power down operation.

Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a circuit diagram of the clock holding circuit, which has a circuit configuration similar to that of the clock holding circuit 10 of FIG. 2. In particular, the inverter INV11, the switches SW11 and SW12 are connected to the power down control signal PD.
3, PD3N (third power down control signal) controls the internal signal C before the latch circuit 20 enters the power down state at the start of power down.
It holds K and CKN.

Compared with the power down control signal PD1 for controlling the latch circuit 20, the PD3 has a power down period prior to the start of power down and a power down control indicating the end of the power down period after the end of power down. Signal (third power down control signal), and switches SW11, SW12 and MOS
It is supplied to the FETs Q11C and Q11D. A high threshold voltage MOSF is provided on each of the power supply voltage VDD side and the ground potential GND side of the inverters INV11 and INV12.
ETQ11C, Q11D, Q12A, Q12B are provided, and power down control signal P is provided at power down.
These MOSFETs are controlled to "OFF" by D3 (PD3N) and PD1 (PD1N), and the inverter IN
The leak current consumed by V11 and INV12 is suppressed.

FIG. 6 shows power-down control signals PD1 and P.
3 is a timing chart showing the relationship of D3, T3 is a power down period of the power down control signal PD3 (third power down period), and the power down period T3 is a time tb before the start timing of the power down period T1. The down period is started, and the power down period is ended after a delay of time ta from the end timing of the power down period T1.

At the start of power down, the latch circuit 20
Of the power-down control signal PD3 is "1" (PD3N) before the time tb before the power-down control is performed.
Is controlled to "0"), and the switch SW11 is "OFF".
And the output of the inverter INV11 is cut off, and the switch SW12 is turned "ON".
A flip-flop is formed by NV13 and INV14, internal signals CK and CKN are held in a state immediately before the start of power down, and further MOSFETs Q11C and Q11 are provided.
Each D is controlled to "OFF" and the inverter INV1
The power supply to 1 is cut off.

Then, after a lapse of time tb from this, the power-down control signal PD1 is controlled to "1" (PD1N is "0") to bring the latch circuit 20 into the power-down state and the MOSFET Q12A of the clock holding circuit 10. ，
Q12B becomes "OFF", the power supply to the inverter INV12 is cut off, and the D flip-flop circuit is completely powered down.

Further, after the power-down period T1 has elapsed, the power-down control signal PD1 is controlled to "0" to recover the latch circuit 20 from the power-down state, and the MOSFETs Q12A and Q12B of the clock holding circuit 10 are recovered.
Becomes "ON", the power supply to the inverter INV12 is restarted, and after a lapse of time ta, the power down control signal PD3 is controlled to "0", and the MOSFET Q11
C and Q11D are turned "ON" to restart the power supply to the inverter INV11, the switch SW11 is turned "ON" and the switch SW12 is turned "OFF", the holding of the internal signals CK and CKN is released, and the clock signal is released. New internal signals CK and CKN are generated based on CLK, and the latch operation by the latch circuit 20 is restarted.

Therefore, the clock holding circuit 10 is controlled to the power down state and the internal signals CK and CKN are held before the latch circuit 20 is controlled to the power down state. Internal signal C when circuit 20 transitions to the power down state
This will completely prevent malfunctions due to changes in K and CKN. The power down control signals PD1 and PD3 are
Each may be supplied from the outside, or may be generated by a logic circuit in the D flip-flop circuit based on a predetermined signal from the outside.

Next, a third embodiment of the present invention will be described with reference to FIGS. FIG. 7 is a block diagram showing the outline of a D flip-flop as a sequential circuit according to another embodiment of the present invention. The same or equivalent parts as those in the above description (FIGS. 1 and 12) are designated by the same reference numerals. is there. In the figure, 10 is a clock holding circuit based on the circuit shown in FIG. 5, and 60 is a latch circuit that latches and outputs a data signal D from the outside based on internal signals CK and CKN during normal operation.

Further, Q10A, Q10B and Q10
C and Q10D are power down control signals PD1 (PD1
N) and PD3 (PD3N), the power supply voltage VDD and the ground potential GND to a predetermined portion of the clock holding circuit 10
Threshold MOSFET, Q60, for shutting off supply of
A, Q60B and Q60C, Q60D are power down control signals PD1 (PD1N) and PD3 (PD3N)
A high-threshold MOS circuit that cuts off the supply of the power supply voltage VDD and the ground potential GND to a predetermined portion of the latch circuit 60 in accordance with
It is a FET.

FIG. 8 is an explanatory diagram (truth table) showing the operation of a general D flip-flop having a function of clearing the output signals Q and QN during the normal operation. In the normal D flip-flop operation, The clear signal CLN (output setting signal) input from the outside is controlled to "1"("1"), and this clear signal CLN is "0"("0").
When controlled to, the output signal Q is cleared to "0" (the output signal QN is "1") regardless of the level states of the data signal D and the clock signal CLK input from the outside.

FIG. 9 shows a latch circuit 60 shown in FIG.
FIG. 16 is a circuit diagram showing that the same or equivalent portions as those in the above description (FIG. 15) are denoted by the same reference numerals. In the figure,
Reference numeral 60A is a master latch circuit which is provided in the preceding stage and latches the data signal D based on the internal signals CK and CKN from the clock holding circuit 10; Is a slave latch circuit that outputs the output signals Q and QN.

In the master latch circuit 60A, NO
R61 is a NOR gate which inverts the output of SW21 and outputs it as a master latch signal. When the internal signal CK becomes "1" and SW22 becomes "ON", the inverter INV26 holds the master latch signal. Make up a flip-flop. SW61 is a switch that is turned “ON” when the power down control signal PD3 is “1”, and the internal signal CK becomes “1” and SW22.
Is ON, INV25 and INV2
6 constitutes a flip-flop for holding the master latch signal. The NOR gate NOR61 is composed of a low threshold voltage MOSFET, and the switch S
W61 is composed of a high threshold voltage MOSFET.

In the slave latch circuit 60B, N
The OR 62 is a NOR gate that inverts the output of the SW 23 and outputs it as a slave latch signal. When the internal signal CK becomes "0" and SW 24 becomes "ON", the OR 62 holds the slave latch signal with the inverter INV28. Make up a flip-flop. SW62 is a switch that is turned “ON” when the power down control signal PD3 is “1”, and the internal signal CK is “0” and SW2.
INV27 and INV when 4 is "ON"
28 forms a flip-flop for holding the slave latch signal. The NOR gate NOR62 is composed of a low threshold voltage MOSFET, and the switch SW62 is composed of a high threshold voltage MOSFET.

The INV 63 is an inverter that inverts the clear signal CLN and outputs it to the NOR gates NOR 61 and NOR 62, and is composed of a low threshold voltage MOSFET. NOR gates NOR61, NOR62,
A high threshold voltage MOSFET is provided on each of the power supply voltage VDD and the ground potential GND of the inverter INV63.
Q61C, Q62C, Q63C (corresponding to Q10C in FIG. 7), Q61D, Q62D, Q63D (Q10D in FIG. 7)
Corresponding to the power down control signal PD.
3, PD3N causes "O" during power down period T3.
FF ”, NOR gates NOR61 and NOR6
2. The leak current consumed by the inverter INV63 is suppressed.

In the normal D flip-flop operation, the switch SW is switched by the power-down control signals PD3 and PD3N.
61 and SW62 are each controlled to be “OFF”, and the clear signal CLN becomes “1”, and the inverter INV63
Since the output of is controlled to "0", the NOR gate NOR
92 and NOR 96 operate similarly to the inverter, and perform the same latching operation as in FIG. When the clear signal CLN is controlled to "0", the inverter I
The output of NV63 becomes "1", and NOR gate NOR6
1, the outputs of the NOR 62 are fixed to "0", respectively, and the output signal Q is cleared to "0" (the output signal QN is "1").

Next, the power down operation will be described. At the start of power-down, the power-down control signal PD3 is controlled to "1" (PD3N is "0") prior to the power-down control signal PD1.
MOSFET Q61C, Q61D, Q62C, Q62
D, Q63C, Q63D are each "OFF",
The power supply to the NOR gates NOR61 and NOR62 and the inverter INV63 is cut off, and the switches SW61 and SW62 are turned "ON", so that the internal signal CK
Is "1", the inverters INV25, INV26
The flip-flop is configured to hold the master latch signal, and when the internal signal CK is “0”, the inverters INV27 and INV28 are configured to hold the slave latch signal.

Subsequently, the power-down control signal PD1 is controlled to "1" (PD1N is "0"), and the inverters INV21, INV23, INV29 to INV21-INV23 are similarly operated as described above.
The power supply to the INV 31 is cut off, and the power is switched to a complete power down state, resulting in a state of low power consumption such as a leak current in a high threshold voltage MOSFET. At the end of power down, the power down control signal PD1 becomes “0” before the power down control signal PD3,
Contrary to the start of power down described above, the inverter INV
The power supply to 21, 21, INV23, INV29 to INV31 is restored, and the master latch signal held by the flip-flop composed of the inverters INV25, INV26 based on the internal signals CK, CKN, or the inverters INV27, INV28. Output signals Q and QN are output according to the slave latch signal held by the constructed flip-flop.

After that, the power down control signal PD
3 becomes “0”, and the switches SW61 and SW62 become “O”.
FF ”, and a flip-flop composed of inverters INV25 and INV26, or inverter INV2
7, the flip-flop composed of INV28 is released, and NOR gates NOR61, NOR62,
The power supply to the inverter INV63 is restored, and the D flip-flop operation is restored.

Therefore, at the start of power-down, the NOR gate N is turned off before the power supply to the circuit composed of the low threshold voltage MOSFET for performing the latch operation is cut off.
The power supply to the OR 61, NOR 62, and the inverter INV 63 is cut off to stop the clear operation based on the clear signal CLN, and at the end of the power down, the power supply to the circuit configured by the low threshold voltage MOSFET for performing the latch operation. After the supply is restored, NOR gate NOR61,
Since the power supply to the NOR 62 and the inverter INV63 is restored to cancel the stop of the clear operation based on the clear signal CLN, the malfunction caused by the clear signal CLN during the power down period is completely suppressed, and the reliable power is ensured. The down operation is performed.

Next, a fourth embodiment of the present invention will be described with reference to FIGS. FIG. 10 is an explanatory diagram (truth table) showing an operation of a general D flip-flop having a function of presetting an output signal during a normal operation. In the normal D flip-flop operation, a preset input from the outside is performed. Signal PRN is “1” (“1”)
The preset signal PRN is set to "0".
When controlled to (“0”), the output signal Q is preset to “1” (output signal QN is “0”) regardless of the level states of the data signal D and the clock signal CLK input from the outside. To be done. Further, in the case of having a function of clearing the held data, the clear signal is “0”, the preset signal is “1”, the output signals Q and QN are cleared, the clear signal is “1”, and the preset signal is “0”. Preset in.

FIG. 11 is a circuit diagram showing a latch circuit having a clear function and a preset function, and the same or equivalent parts as those in the above description (FIG. 9) are designated by the same reference numerals. In the figure, 70A is a master latch circuit, and the NAND 71 inverts the output of SW21 and
NAND gate, NAND7, which outputs as a latch signal
Reference numeral 2 is a NAND gate which inverts and outputs the master latch signal, and both constitute a flip-flop which holds the master latch signal when the internal signal CK becomes "1" and the SW22 becomes "ON". SW71 is a switch that is turned “ON” when the power down control signal PD3 is “1”, the internal signal CK is “1”, and SW22 is “O”.
In the case of "N", INV25 and INV26 form a flip-flop that holds the slave latch signal. The NAND gates NAND71, NAN
D72 is composed of a low threshold voltage MOSFET, and SW71 is composed of a high threshold voltage MOSFET.

70B is a slave latch circuit,
The AND 75 is a NAND gate which inverts the output of the SW 23 and outputs it as a slave latch signal, and the NAND 76 is an NAND gate which inverts and outputs the slave latch signal, and both the internal signal CK becomes “0” and SW 24 becomes “O”.
When it becomes "N", a flip-flop for holding the slave latch signal is formed. SW72 is a switch that is turned “ON” when the power down control signal PD3 is “1”, the internal signal CK is “0”, and SW24 is “O”.
In the case of "N", INV27 and INV28 form a flip-flop for holding the slave latch signal. The NAND gates NAND75, NAN
D76 is composed of a low threshold voltage MOSFET, and SW72 is composed of a high threshold voltage MOSFET.

Further, INV73 and INV74 are master
Inverter for buffer output of latch signal, INV77
INV79 is an inverter that outputs the output signals Q and QN by inverting the slave latch signal, and each is composed of a low threshold voltage MOSFET. NAND gates NAND71, NAND72, NA
Power supply voltage VDD and ground potential GND side of ND75 and NAND76 are respectively high threshold voltage MOSFE.
TQ71C, Q72C, Q75C, Q76C (Q in FIG. 7
10C), Q71D, Q72D, Q75D, Q7
6D (corresponding to Q10D in FIG. 7) is provided, which is controlled to “OFF” in the power down period T3 by the power down control signals PD3 and PD3N to suppress the leak current consumed in each NAND gate. ing.

In the normal D flip-flop operation, the switch SW is switched by the power-down control signals PD3 and PD3N.
61, SW62, SW71, and SW72 are respectively "OF
If the clear signal CLN and the preset signal PRN are both controlled to "1",
AND gate NAND71, NAND72, NAND7
5, the NAND 76 operates in the same manner as the inverter, and performs the same latch operation as in FIG. If the preset signal PRN is controlled to “0”, the NAND
The outputs of the gates NAND71 and NAND76 are fixed at "1", and the output signal Q is "1" (output signal QN
Is preset to "0").

Next, the power down operation will be described. At the start of power-down, the power-down control signal PD3 is controlled to "1" (PD3N is "0") prior to the power-down control signal PD1.
MOSFET Q71C, Q71D, Q72C, Q72
D, Q75C, Q75D, Q76C, Q76D are turned off, and the NAND gates NAND71, N
The power supply to the AND72, NAND75 and NAND76 is cut off, and the switches SW61 and SW6
2, SW71, SW72 are turned on, and internal signal C
When K is “1”, the inverters INV25, INV2
A flip-flop is constituted by 6 to hold the master latch signal, and when the internal signal CK is "0", a flip-flop is constituted by the inverters INV27 and INV28 to hold the slave latch signal.

Then, the power-down control signal PD1 is controlled to "1" (PD1N is "0"), the power supply to the inverter INV21 is cut off as described above, and the MOSFETs Q73A, Q73B, Q77A, Q7.
7B, Q78A, Q78B are turned "OFF", and inverters INV73, INV74, INV77 to INV79
The power supply to the device is cut off and the power is completely shifted to the low power consumption state of about the leakage current in the high threshold voltage MOSFET. Further, at the end of power down, the power down control signal PD1 becomes “0” prior to the power down control signal PD3, and contrary to the above-described power down start, inverters INV21, IN
The power supply to V73, INV74, and INV77 to INV79 is restored, and the output signals Q and QN are output in accordance with the master latch signal held by each flip-flop based on the internal signal CK or the slave latch signal. Is output.

Further, the power-down control signal PD3 becomes "0", and the switches SW61, SW62, SW7.
1, SW72 becomes "OFF", each flip-flop is released, and the NAND gate NAN
The power supply to the D71, NAND72, NAND75, and NAND76 is restored, and the D flip-flop operation is restored.

Therefore, at the start of power down, before shutting off the power supply to the circuit composed of the low threshold voltage MOSFET for performing the latch operation, the NAND gates NAND71, NAND72, NAND75, NAND are provided.
A circuit composed of a low threshold voltage MOSFET that cuts off the power supply to 76 to stop the clear operation based on the clear signal CLN and the preset operation based on the preset signal PRN, and performs the latch operation at the end of the power down. After restoration of power supply to the NAND gate NA
ND71, NAND72, NAND75, NAND76
Since the clear operation and the preset operation stop are released by restoring the power supply to the power supply, the malfunction caused by the clear signal CLN or the preset signal PRN during the power down period is completely suppressed, and the reliable power down operation is performed. Is carried out.

[0055]

As described above, the present invention provides the first
Set the first power-down period to the power-down control signal.
The second power down control signal
Power Dow ends later than the end of the Power Down period
When the power down period ends, the power supply to the latch circuit is restored after the power-down period ends, and then the internal signal held by the clock holding circuit is released. At this time, the clock holding circuit stably supplies the internal signal immediately before the start of power down to the latch circuit, and the latch circuit recovers to the state immediately before the start of power down without malfunctioning. Power is supplied to the clock holding circuit, and a new internal signal is supplied to the latch circuit based on the clock signal from the outside, and the internal operating state held in the latch circuit at the end of the power down period Accurate and stable, because it can completely prevent malfunction due to mismatch with the internal signal from the clock holding circuit. It is possible to realize a powered down operation.

In addition, the first power-down control signal
The second power-down control as the power-down period of 1
From the start of the second power-down period indicated by the signal
Use a signal that has a power-down period that starts first.
Thus, at the start of the power down period, the latch operation is stopped after the internal signal is held by the clock holding circuit, so the internal signal is held by the clock holding circuit before the latch operation is stopped. At the start of the power down period, it is possible to completely prevent a malfunction caused by a change in the internal signal when the operation of the latch circuit is stopped, and it is possible to realize an accurate and stable power down operation. Further, at the start of the power down period, the operation of the output setting means is stopped before the stop of the latch operation, and at the end of the power down period, the operation stop of the output setting means is released before the restart of the latch operation. At the start of the power-down period, the operation of the output setting means in the latch circuit is stopped before stopping the latch operation, and at the end of the power-down period, the operation of the output setting means is released before the operation stop of the output setting means is released. The suspension is released, and malfunctions due to the output setting signal at the start and end of the power down period can be completely suppressed, and a reliable and stable power down operation can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a D flip-flop according to an exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram showing a clock holding circuit of FIG.

FIG. 3 is a timing chart of a power down control signal.

FIG. 4 is a circuit diagram showing a circuit for generating a power down control signal.

FIG. 5 is a circuit diagram of a clock holding circuit according to a second embodiment of the present invention.

FIG. 6 is a timing chart of a power down control signal.

FIG. 7 is a block diagram of a D flip-flop according to a third exemplary embodiment of the present invention.

FIG. 8 is an explanatory diagram showing an operation of a D flip-flop having a clear function.

9 is a circuit diagram showing the latch circuit of FIG. 7. FIG.

FIG. 10 is an explanatory diagram showing an operation of a D flip-flop having a preset function.

FIG. 11 is a circuit diagram of a latch circuit according to a fourth embodiment of the present invention.

FIG. 12 is a block diagram of a conventional D flip-flop.

FIG. 13 is an explanatory diagram showing the operation of a general D flip-flop.

FIG. 14 is a circuit diagram showing the clock holding circuit of FIG.

FIG. 15 is a circuit diagram showing the latch circuit of FIG.

[Explanation of symbols]

10 ... Clock holding circuit, 20 ... Latch circuit, PD1,
PD1N ... power-down control signal, PD2, PD2N ...
Power-down control signal, PD3, PD3N ... power-down control signal, Q10C, Q10D, Q20A, Q20B
... MOSFET, CLK ... Clock signal, CK, CKN
... internal signal, D ... data signal, Q, QN ... output signal.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Junzo Yamada 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Inside Nippon Telegraph and Telephone Corporation (56) Reference JP-A-5-210976 (JP, A) (58) ) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 1/26-1/32 H03K 19/00

Claims (5)

(57) [Claims] 1. In a normal operation, a predetermined internal signal is generated based on a clock signal, and the immediately preceding internal signal is held in response to the start of a first power-down period indicated by a first power-down control signal. A clock holding circuit that releases holding of an internal signal in response to the end of the first power-down period, and a second power indicated by a second power-down control signal that latches in response to the internal signal during normal operation. In response to the start of the down period, the immediately preceding internal operation state is held and the power supply is cut off to stop the latch operation. At the end of the second power down period, the power supply is restored to perform the latch operation. And a latch circuit for restarting, wherein the first power-down control signal is the first power-down control signal.
As the down period, the second power down control signal
Later than the end of the second power down period
A sequential circuit having a power-down period that ends . 2. In normal operation, the location is based on a clock signal.
Constant internal signal to generate the first power-down control signal
Directly in response to the start of the first power-down period indicated by
The previous internal signal is held and the first power-down period
A clock hold cycle that releases the hold of the internal signal upon completion.
And latch operation according to the internal signal during normal operation
The second power-down control signal indicates the second
Depending on the start of the power-down period,
Latch by holding and shutting off the power supply
Stop operation and respond to the end of the second power down period.
Latch operation to restore power supply and restart latch operation
And a first power-down control signal, wherein the first power-down control signal is the first power-down control signal.
As the down period, the second power down control signal
Prior to the start of the second power down period indicated by
At the end of the second power-down period.
A sequential circuit characterized by having a power-down period that ends after a delay . 3. The sequential circuit according to claim 2, wherein the latch circuit has output setting means for forcibly outputting a predetermined output signal according to the output setting signal during normal operation, and the first power down period. The power supply to the output setting means is stopped by stopping the power supply to the output setting means, and the power supply to the output setting means is stopped in response to the end of the first power down period. A sequential circuit characterized in that the operation stop of the output setting means is released by restoration. 4. In normal operation, the location is based on a clock signal.
Constant internal signal to generate the first power-down control signal
Directly in response to the start of the first power-down period indicated by
The previous internal signal is held and the first power-down period
A clock hold cycle that releases the hold of the internal signal upon completion.
And latch operation according to the internal signal during normal operation
The second power-down control signal indicates the second
Depending on the start of the power-down period,
Latch by holding and shutting off the power supply
Stop operation and respond to the end of the second power down period.
Latch operation to restore power supply and restart latch operation
And a first power-down control signal, wherein the first power-down control signal is the first power-down control signal.
As the down period, the second power down control signal
A predetermined time from the second power down period indicated by
Characterized by having a delayed first power down period
Sequential circuit to do. 5. The normal operation is based on a clock signal.
Constant internal signal to generate the first power-down control signal
Directly in response to the start of the first power-down period indicated by
The previous internal signal is held and the first power-down period
A clock hold cycle that releases the hold of the internal signal upon completion.
And latch operation according to the internal signal during normal operation
The second power-down control signal indicates the second
Depending on the start of the power-down period,
Latch by holding and shutting off the power supply
Stop operation and respond to the end of the second power down period.
Latch operation to restore power supply and restart latch operation
And a first power-down control signal, wherein the first power-down control signal is the first power-down control signal.
As the down period, the second power down control signal
Prior to the start of the second power down period indicated by
Characterized by having a power-down period starting at
Sequential circuit.