CN112821882B - High-performance Schmitt trigger capable of switching working points and working point switching method - Google Patents

High-performance Schmitt trigger capable of switching working points and working point switching method Download PDF

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Publication number
CN112821882B
CN112821882B CN202011614038.XA CN202011614038A CN112821882B CN 112821882 B CN112821882 B CN 112821882B CN 202011614038 A CN202011614038 A CN 202011614038A CN 112821882 B CN112821882 B CN 112821882B
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nmos
pmos
electrode
drain electrode
source electrode
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CN112821882A (en
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刘天奇
蔡小五
杨广文
甘霖
李博
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National Supercomputing Center In Wuxi
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National Supercomputing Center In Wuxi
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger

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Abstract

The application provides a high-performance Schmitt trigger capable of switching working points, which relates to the field of semiconductor integrated circuit design and comprises a positive threshold adjustment module, a negative threshold adjustment module and a gating information number module.

Description

High-performance Schmitt trigger capable of switching working points and working point switching method
Technical Field
The present application relates to the field of semiconductor integrated circuit design, and more particularly to a high performance schmitt trigger with switchable operating points.
Background
The schmitt trigger has bidirectional hysteresis characteristics for an input signal, and corresponds to a positive threshold voltage and a negative threshold voltage respectively, and the output result is the inversion of the input signal. When the input signal rises from low level to high level, the output is inverted from high level to low level only if the voltage value is larger than the forward threshold voltage; when the input signal falls from high to low, the output will be inverted from low to high only if the voltage value is less than the negative threshold voltage. Because of the existence of positive and negative threshold voltages, the schmitt trigger has excellent noise interference resistance, and is widely applied to various interface circuits.
As shown in FIG. 1, the Schmitt trigger in the prior art is generally formed by connecting three PMOS transistors and three NMOS transistors, the value of the positive threshold voltage can be adjusted by simply adjusting the width-to-length ratio of the MN-2 transistor to the MN-3 transistor, and the value of the negative threshold voltage can be adjusted by adjusting MP-1, MP-3, MN-2 transistor and MN-3 transistor. With the above method, an ideal high-low level noise interference immunity can be generally obtained for a specific level of input signal.
However, in some application scenarios, the integrated circuit product is often required to be compatible with multiple levels of input signals of one chip, for example, the input signals of the high-voltage power driving circuit are required to be compatible with 3.3V/5.0V, so that the product can be more widely applied. With the schmitt trigger circuit structure shown in fig. 1, a developer can adjust the positive and negative threshold voltages to be within the working range of the low-voltage signal, so that the schmitt trigger circuit can work for the high-voltage signal, and the compatibility of multiple signals is obtained. However, this compatibility comes at the expense of the ability to resist noise interference at high voltage signals. The schmitt trigger operates at a high voltage signal and its negative threshold voltage can be well above the value of the low voltage signal in order to obtain a good noise immunity. For the schmitt circuit structure in the prior art, if the anti-interference capability under the high-voltage signal working condition is required to be properly increased, the positive threshold voltage and the negative threshold voltage of the schmitt circuit structure are generally properly increased, however, the anti-interference capability under the low-voltage signal working condition is greatly reduced due to the excessive positive threshold voltage. This results in the prior art schmitt trigger having, when its transistor parameters are determined, generally only one operating point for the circuit, even if it is compatible with both operating points, obtained at the expense of the noise immunity of part of the operating points.
Disclosure of Invention
The high-performance Schmitt trigger with switchable working points solves the problem that a Schmitt circuit in the prior art is difficult to perfectly compatible with two working points, so that the circuit can be compatible with the two working points, and excellent noise interference resistance can be obtained at both working points.
In order to solve the technical problems, the technical scheme provided by the application is as follows:
the application provides a high-performance Schmitt trigger capable of switching working points, which comprises a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, a third NMOS, an input end, an output end and a power supply, wherein the first PMOS is connected with the second PMOS; the source electrode of the first PMOS is connected with a power supply; the source electrode of the second PMOS is respectively connected with the drain electrode of the first PMOS and the source electrode of the third PMOS; the drain electrode of the second PMOS is connected with the drain electrode of the first NMOS; the source electrode of the first NMOS is respectively connected with the drain electrode of the second NMOS and the source electrode of the third NMOS; the source electrode of the second NMOS is grounded; the input end is connected with the grid electrode of the first PMOS, the grid electrode of the second PMOS, the grid electrode of the first NMOS and the grid electrode of the second NMOS; the output end is connected with the drain electrode of the second PMOS, the drain electrode of the second NMOS, the grid electrode of the third PMOS and the grid electrode of the third NMOS; the system comprises a positive threshold adjustment module, a negative threshold adjustment module and a gating information number module; the forward threshold adjustment module comprises a fourth NMOS and a fifth NMOS; the drain end of the third NMOS is connected with the source electrode of the fourth NMOS and the source electrode of the fifth NMOS; the drain electrode of the fourth NMOS and the drain electrode of the fifth NMOS are respectively connected with the power supply; the grid electrode of the fourth NMOS is connected with the output end; the negative threshold adjustment module comprises a fourth PMOS and a sixth NMOS; the drain electrode of the third PMOS is connected with the source electrode of the fourth PMOS and the source electrode of the sixth NMOS; the drain electrode of the fourth PMOS and the drain electrode of the sixth NMOS are respectively grounded; the grid electrode of the fourth PMOS is connected with the output end; the grid electrode of the fifth NMOS and the grid electrode of the sixth NMOS are respectively connected with the gating signal module; the gating signal module can switch the conduction of a fifth NMOS and the sixth NMOS, and only one of the fifth NMOS and the sixth NMOS is conducted at the same time.
The high-performance schmitt trigger capable of switching the working point provided by the application preferably comprises an auxiliary adjusting module; the auxiliary regulating module comprises a seventh NMOS; the drain electrode of the seventh NMOS is connected with the drain electrode of the second NMOS; the source electrode of the seventh NMOS is connected with the source electrode of the second NMOS; the grid electrode of the seventh NMOS is connected with the gating signal module; the gating signal module can enable a seventh NMOS to be conducted, and the sixth NMOS and the seventh NMOS are conducted simultaneously.
The high-performance schmitt trigger capable of switching the working point provided by the application preferably further comprises a zeroth NMOS; the source electrode of the first NMOS is connected with the drain electrode of the second NMOS through the zeroth NMOS; the drain electrode of the second NMOS is connected with the source electrode of the zeroth NMOS; and the source electrode of the first NMOS is connected with the drain electrode of the zeroth NMOS.
The high-performance schmitt trigger capable of switching the working point provided by the application preferably further comprises a zeroth PMOS; the source electrode of the second PMOS is connected with the drain electrode of the first PMOS through the zeroth PMOS; the source electrode of the zeroth PMOS is connected with the drain electrode of the first PMOS; and the drain electrode of the zeroth PMOS is connected with the source electrode of the second PMOS.
The high-performance schmitt trigger capable of switching the working point is preferably characterized in that the gating signal module comprises a gating signal end, a fifth PMOS and an eighth NMOS; the grid electrode of the sixth NMOS and the grid electrode of the seventh NMOS are respectively connected with the gating signal end; the source end of the fifth PMOS is connected with the power supply; the drain terminal of the fifth PMOS is respectively connected with the grid electrode of the fifth NMOS and the drain electrode of the eighth NMOS; the source electrode of the eighth NMOS is grounded; and the grid electrode of the fifth PMOS and the grid electrode of the eighth NMOS are respectively connected with the gating signal end.
The high-performance schmitt trigger capable of switching the working point provided by the application preferably enables the sixth NMOS to be disconnected and the fifth NMOS to be connected through the gating signal module to enter a high-voltage working point; the fifth NMOS is disconnected and the sixth NMOS is connected through the gating signal module, and a low-voltage working point is entered.
The application provides a high-performance schmitt trigger capable of switching working points, which is characterized in that a sixth NMOS is disconnected and a fifth NMOS is connected through a gating signal module to enter a high-voltage working point, specifically, the sixth NMOS is disconnected, the seventh NMOS is disconnected and the fifth NMOS is connected through the gating signal module to enter the high-voltage working point; the "turning off the fifth NMOS and turning on the sixth NMOS by the gating signal module, and entering the low voltage operating point" is specifically that turning off the fifth NMOS, turning on the sixth NMOS and turning on the seventh NMOS by the gating signal module, and entering the low voltage operating point.
The application has the following advantages:
the application provides a high-performance Schmitt trigger capable of switching working points, which comprises a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, a third NMOS, an input end, an output end and a power supply, wherein the first PMOS is connected with the second PMOS; the source electrode of the first PMOS is connected with a power supply; the source electrode of the second PMOS is respectively connected with the drain electrode of the first PMOS and the source electrode of the third PMOS; the drain electrode of the second PMOS is connected with the drain electrode of the first NMOS; the source electrode of the first NMOS is respectively connected with the drain electrode of the second NMOS and the source electrode of the third NMOS; the source electrode of the second NMOS is grounded; the input end is connected with the grid electrode of the first PMOS, the grid electrode of the second PMOS, the grid electrode of the first NMOS and the grid electrode of the second NMOS; the output end is connected with the drain electrode of the second PMOS, the drain electrode of the second NMOS, the grid electrode of the third PMOS and the grid electrode of the third NMOS; the system comprises a positive threshold adjustment module, a negative threshold adjustment module and a gating information number module; the forward threshold adjustment module comprises a fourth NMOS and a fifth NMOS; the drain end of the third NMOS is connected with the source electrode of the fourth NMOS and the source electrode of the fifth NMOS; the drain electrode of the fourth NMOS and the drain electrode of the fifth NMOS are respectively connected with the power supply; the grid electrode of the fourth NMOS is connected with the output end; the negative threshold adjustment module comprises a fourth PMOS and a sixth NMOS; the drain electrode of the third PMOS is connected with the source electrode of the fourth PMOS and the source electrode of the sixth NMOS; the drain electrode of the fourth PMOS and the drain electrode of the sixth NMOS are respectively grounded; the grid electrode of the fourth PMOS is connected with the output end; the grid electrode of the fifth NMOS and the grid electrode of the sixth NMOS are respectively connected with the gating signal module; the gating signal module can switch the conduction of a fifth NMOS and the sixth NMOS, and only one of the fifth NMOS and the sixth NMOS is conducted at the same time. The application can switch the on-off of the fifth NMOS and the sixth NMOS through the gating signal module so as to finish the switching between the two working points, thereby ensuring the multi-signal compatibility of the circuit and also ensuring that the good noise interference resistance can be maintained at each working point.
Drawings
The application and its features, aspects and advantages will become more apparent from the detailed description of non-limiting embodiments with reference to the following drawings. Like numbers refer to like parts throughout. The drawings are not intended to be drawn to scale, emphasis instead being placed upon illustrating the principles of the application.
FIG. 1 is a circuit schematic of a prior art Schmitt trigger;
FIG. 2 is a schematic circuit diagram of a high performance Schmitt trigger capable of switching operating points according to embodiment 1 of the present application;
FIG. 3 is a schematic circuit diagram of another switchable operating point high performance Schmitt trigger according to embodiment 1 of the present application;
FIG. 4 is a schematic circuit diagram of another switchable operating point high performance Schmitt trigger according to embodiment 1 of the present application;
FIG. 5 is a schematic diagram of a characteristic curve of a high performance Schmitt trigger at a high voltage operating point for a switchable operating point according to embodiment 1 of the present application;
fig. 6 is a schematic diagram of a characteristic curve of the switchable operating point high performance schmitt trigger at a low voltage operating point according to embodiment 1 of the present application.
Detailed Description
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application.
As shown in fig. 2, the embodiment 1 of the present application provides a high performance schmitt trigger capable of switching operating points, which includes a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, a third NMOS, an input terminal, an output terminal, and a power supply; the source electrode of the first PMOS is connected with a power supply; the source electrode of the second PMOS is respectively connected with the drain electrode of the first PMOS and the source electrode of the third PMOS; the drain electrode of the second PMOS is connected with the drain electrode of the first NMOS; the source electrode of the first NMOS is respectively connected with the drain electrode of the second NMOS and the source electrode of the third NMOS; the source electrode of the second NMOS is grounded; the input end is connected with the grid electrode of the first PMOS, the grid electrode of the second PMOS, the grid electrode of the first NMOS and the grid electrode of the second NMOS; the output end is connected with the drain electrode of the second PMOS, the drain electrode of the second NMOS, the grid electrode of the third PMOS and the grid electrode of the third NMOS; the system comprises a positive threshold adjustment module, a negative threshold adjustment module and a gating information number module; the forward threshold adjustment module comprises a fourth NMOS and a fifth NMOS; the drain end of the third NMOS is connected with the source electrode of the fourth NMOS and the source electrode of the fifth NMOS; the drain electrode of the fourth NMOS and the drain electrode of the fifth NMOS are respectively connected with a power supply; the grid electrode of the fourth NMOS is connected with the output end; the negative threshold adjustment module comprises a fourth PMOS and a sixth NMOS; the drain electrode of the third PMOS is connected with the source electrode of the fourth PMOS and the source electrode of the sixth NMOS; the drain electrode of the fourth PMOS and the drain electrode of the sixth NMOS are respectively grounded; the grid electrode of the fourth PMOS is connected with the output end; the grid electrode of the fifth NMOS and the grid electrode of the sixth NMOS are respectively connected with the gating signal module; the gating signal module can switch the conduction of the fifth NMOS and the sixth NMOS, and only one of the fifth NMOS and the sixth NMOS is conducted at the same time.
IN this embodiment, the input signal high level of the input terminal IN of the high voltage operating point is V equal to the power supply VDD level (e.g. 5V logic signal), and the input signal low level is equal to the power supply ground VSS level. The sixth NMOS is disconnected and the fifth NMOS is connected through the gating signal module, and a high-voltage working point is entered. After entering the high-voltage working point, the positive threshold voltage and the negative threshold voltage can be adjusted to obtain good noise interference resistance. Positive threshold voltage adjustment: the adjustment is mainly performed by adjusting the parameters of the third NMOS, and the auxiliary adjustment can be performed through the fourth NMOS, the fifth NMOS and the second NMOS. Negative threshold voltage adjustment: the adjustment is mainly performed by adjusting the parameters of the fourth PMOS, and the auxiliary adjustment can be performed through the third PMOS and the second NMOS. By the adjusting method, the positive threshold voltage VTH1+ and the negative threshold voltage VTH 1-can be kept symmetrically distributed about VDD/2 (as shown in FIG. 5), and thus, the high-voltage working point has good noise interference resistance.
IN this embodiment, the input signal level of the input terminal IN of the low voltage operation point is V '(e.g. 3.3V logic signal), wherein V' < power VDD, the input signal low level is equal to the power ground VSS level. The fifth NMOS is disconnected and the sixth NMOS is connected through the gating signal module, and a low-voltage working point is entered. After entering the low-voltage working point, the positive threshold voltage and the negative threshold voltage can be adjusted to obtain good noise interference resistance. Positive threshold voltage adjustment: the adjustment is mainly performed by adjusting parameters of the fourth NMOS, and the auxiliary adjustment is performed by the third NMOS. Negative threshold voltage adjustment: the adjustment is mainly performed by adjusting the parameters of the third PMOS. By the adjusting method, the positive threshold voltage VTH2+ and the negative threshold voltage VTH 2-can be kept symmetrically distributed about V'/2 (as shown in fig. 6), and therefore good noise interference resistance of the low-voltage working point is achieved.
Therefore, through the circuit structure, the on-off of the fifth NMOS and the sixth NMOS can be switched through the gating signal module so as to finish the switching between the two working points, thereby ensuring the multi-signal compatibility of the circuit and ensuring that the good anti-noise interference capability is maintained at each working point.
As shown in fig. 3, the embodiment includes an auxiliary adjusting module; the auxiliary regulating module comprises a seventh NMOS; the drain electrode of the seventh NMOS is connected with the drain electrode of the second NMOS; the source electrode of the seventh NMOS is connected with the source electrode of the second NMOS; the grid electrode of the seventh NMOS is connected with the gating signal module; the gating signal module can enable the seventh NMOS to be conducted, and the sixth NMOS and the seventh NMOS are conducted simultaneously. When the high-performance schmitt trigger capable of switching the operating point provided by the embodiment enters the low-voltage operating point, the seventh NMOS is turned on, and when the negative threshold voltage is adjusted, the parameter of the seventh NMOS can be adjusted in an auxiliary manner.
As shown in fig. 4, the embodiment further includes a zeroth NMOS and a zeroth PMOS; the source electrode of the first NMOS is connected with the drain electrode of the second NMOS through a zeroth NMOS; the drain electrode of the second NMOS is connected with the source electrode of the zeroth NMOS; the source electrode of the first NMOS is connected with the drain electrode of the zeroth NMOS. The source electrode of the second PMOS is connected with the drain electrode of the first PMOS through a zeroth PMOS; the source electrode of the zeroth PMOS is connected with the drain electrode of the first PMOS; the drain of the zeroth PMOS is connected with the source of the second PMOS. By adding the zeroth PMOS and the zeroth NMOS, the positive and negative thresholds of the two working points can be in a reasonable range, so that the circuit parameter adjustment is easier to be compromised to an expected state.
The communication selecting module in the embodiment comprises a gating signal end, a fifth PMOS and an eighth NMOS; the grid electrode of the sixth NMOS and the grid electrode of the seventh NMOS are respectively connected with the gating signal end; the source end of the fifth PMOS is connected with the power supply; the drain terminal of the fifth PMOS is respectively connected with the grid electrode of the fifth NMOS and the drain electrode of the eighth NMOS; the source electrode of the eighth NMOS is grounded; the grid electrode of the fifth PMOS and the grid electrode of the eighth NMOS are respectively connected with the gating signal end. The gating signal end S is in a low level, the sixth NMOS is disconnected from the seventh NMOS, and the fifth NMOS is conducted, so that the high-performance Schmitt trigger provided by the embodiment enters a high-voltage working point; the high-performance schmitt trigger provided in this embodiment enters the low-voltage operating point by switching the gating signal terminal S at a high level, the sixth NMOS being turned on with the seventh NMOS, and the fifth NMOS being turned off.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the application, and all equivalent structural changes made by the present application and the accompanying drawings, or direct or indirect application in other related technical fields, are included in the scope of the present application.

Claims (7)

1. A high-performance Schmitt trigger capable of switching an operating point comprises a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, a third NMOS, an input end, an output end and a power supply; the source electrode of the first PMOS is connected with a power supply; the source electrode of the second PMOS is respectively connected with the drain electrode of the first PMOS and the source electrode of the third PMOS; the drain electrode of the second PMOS is connected with the drain electrode of the first NMOS; the source electrode of the first NMOS is respectively connected with the drain electrode of the second NMOS and the source electrode of the third NMOS; the source electrode of the second NMOS is grounded; the input end is connected with the grid electrode of the first PMOS, the grid electrode of the second PMOS, the grid electrode of the first NMOS and the grid electrode of the second NMOS; the output end is connected with the drain electrode of the second PMOS, the drain electrode of the second NMOS, the grid electrode of the third PMOS and the grid electrode of the third NMOS; the device is characterized by comprising a positive threshold adjusting module, a negative threshold adjusting module and a gating signal module; the forward threshold adjustment module comprises a fourth NMOS and a fifth NMOS; the drain end of the third NMOS is connected with the source electrode of the fourth NMOS and the source electrode of the fifth NMOS; the drain electrode of the fourth NMOS and the drain electrode of the fifth NMOS are respectively connected with the power supply; the grid electrode of the fourth NMOS is connected with the output end; the negative threshold adjustment module comprises a fourth PMOS and a sixth NMOS; the drain electrode of the third PMOS is connected with the source electrode of the fourth PMOS and the source electrode of the sixth NMOS; the drain electrode of the fourth PMOS and the drain electrode of the sixth NMOS are respectively grounded; the grid electrode of the fourth PMOS is connected with the output end; the grid electrode of the fifth NMOS and the grid electrode of the sixth NMOS are respectively connected with the gating signal module; the gating signal module can switch the conduction of a fifth NMOS and the sixth NMOS, and only one of the fifth NMOS and the sixth NMOS is conducted at the same time.
2. The switchable operating point high performance schmitt trigger of claim 1 comprising an auxiliary regulation module; the auxiliary regulating module comprises a seventh NMOS; the drain electrode of the seventh NMOS is connected with the drain electrode of the second NMOS; the source electrode of the seventh NMOS is connected with the source electrode of the second NMOS; the grid electrode of the seventh NMOS is connected with the gating signal module; the gating signal module can enable a seventh NMOS to be conducted, and the sixth NMOS and the seventh NMOS are conducted simultaneously.
3. The switchable operating point high performance schmitt trigger of claim 1 further comprising a zeroth NMOS; the source electrode of the first NMOS is connected with the drain electrode of the second NMOS through the zeroth NMOS; the drain electrode of the second NMOS is connected with the source electrode of the zeroth NMOS; and the source electrode of the first NMOS is connected with the drain electrode of the zeroth NMOS.
4. The switchable operating point high performance schmitt trigger of claim 1 further comprising a zeroth PMOS; the source electrode of the second PMOS is connected with the drain electrode of the first PMOS through the zeroth PMOS; the source electrode of the zeroth PMOS is connected with the drain electrode of the first PMOS; and the drain electrode of the zeroth PMOS is connected with the source electrode of the second PMOS.
5. The switchable operating point high performance schmitt trigger of any one of claims 1-4, wherein the gating signal module comprises a gating signal terminal, a fifth PMOS and an eighth NMOS; the grid electrode of the sixth NMOS and the grid electrode of the seventh NMOS are respectively connected with the gating signal end; the source end of the fifth PMOS is connected with the power supply; the drain terminal of the fifth PMOS is respectively connected with the grid electrode of the fifth NMOS and the drain electrode of the eighth NMOS; the source electrode of the eighth NMOS is grounded; and the grid electrode of the fifth PMOS and the grid electrode of the eighth NMOS are respectively connected with the gating signal end.
6. The method for switching an operating point of a switchable operating point high performance schmitt trigger according to any one of claims 1 to 5, wherein a sixth NMOS is turned off and a fifth NMOS is turned on by a gating signal module to enter a high voltage operating point; the fifth NMOS is disconnected and the sixth NMOS is connected through the gating signal module, and a low-voltage working point is entered.
7. The method for switching operating points according to claim 6, wherein the "turning off the sixth NMOS and turning on the fifth NMOS by the gating signal module to enter the high voltage operating point" is specifically turning off the sixth NMOS, turning off the seventh NMOS and turning on the fifth NMOS by the gating signal module to enter the high voltage operating point; the "turning off the fifth NMOS and turning on the sixth NMOS by the gating signal module, and entering the low voltage operating point" is specifically that turning off the fifth NMOS, turning on the sixth NMOS and turning on the seventh NMOS by the gating signal module, and entering the low voltage operating point.
CN202011614038.XA 2020-12-30 2020-12-30 High-performance Schmitt trigger capable of switching working points and working point switching method Active CN112821882B (en)

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CN106209026A (en) * 2014-08-29 2016-12-07 台湾积体电路制造股份有限公司 Flip-flop circuit
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