CN112821882A - High-performance Schmitt trigger capable of switching working points and working point switching method - Google Patents
High-performance Schmitt trigger capable of switching working points and working point switching method Download PDFInfo
- Publication number
- CN112821882A CN112821882A CN202011614038.XA CN202011614038A CN112821882A CN 112821882 A CN112821882 A CN 112821882A CN 202011614038 A CN202011614038 A CN 202011614038A CN 112821882 A CN112821882 A CN 112821882A
- Authority
- CN
- China
- Prior art keywords
- nmos
- pmos
- electrode
- drain electrode
- source electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
Abstract
The invention provides a high-performance Schmitt trigger capable of switching working points, which relates to the field of semiconductor integrated circuit design and comprises a positive threshold adjusting module, a negative threshold adjusting module and a gating information signal module.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit design, in particular to a high-performance Schmitt trigger capable of switching working points.
Background
The Schmitt trigger has bidirectional hysteresis characteristics for an input signal, respectively corresponds to a positive threshold voltage and a negative threshold voltage, and outputs an inverted output of the input signal. When the input signal rises from a low level to a high level, the output is inverted from the high level to the low level only if the voltage value is greater than the positive threshold voltage; when the input signal falls from a high level to a low level, the output will be inverted from the low level to the high level only if the voltage value is less than the negative threshold voltage. Due to the existence of positive and negative threshold voltages, the Schmitt trigger has excellent anti-noise interference capability, and therefore, the Schmitt trigger is widely applied to various interface circuits.
The schmitt trigger in the prior art is generally formed by connecting three PMOS transistors and three NMOS transistors as shown in fig. 1, and the value of the positive threshold voltage can be adjusted by simply adjusting the width-to-length ratio of the MN-2 transistor and the MN-3 transistor, and the value of the negative threshold voltage can be adjusted by adjusting MP-1, MP-3, MN-2, and MN-3. The method can generally obtain the ideal high-low level anti-noise interference capability for the input signal with a specific level.
However, in some application scenarios, the integrated circuit product is often required to have an input signal of one chip compatible with multiple levels, for example, the input signal of the high-voltage power driving circuit is required to have compatibility of 3.3V/5.0V, so that the product can be more widely applied. With the schmitt trigger circuit configuration shown in fig. 1, developers can adjust the positive and negative threshold voltages to be within the operating range of the low-voltage signal, which is also operable for the high-voltage signal, thereby obtaining multi-signal compatibility. However, this compatibility comes at the expense of noise immunity under high voltage signals. The schmitt trigger works under a high-voltage signal, and the negative threshold voltage of the schmitt trigger can be properly higher than the value of a low-voltage signal, so that the schmitt trigger has excellent noise interference resistance. For the schmitt circuit structure in the prior art, if the anti-interference capability under the working condition of high-voltage signals is required to be properly increased, the positive and negative threshold voltages of the schmitt circuit structure are normally properly increased, but the anti-noise interference capability under the working condition of low-voltage signals is greatly reduced due to the overlarge forward threshold voltage. Therefore, in the schmitt trigger in the prior art, after the transistor parameters are determined, the operating point of the circuit is generally only one, and even if two operating points can be compatible, the anti-noise capability of the schmitt trigger is obtained by sacrificing part of the operating points.
Disclosure of Invention
The high-performance Schmitt trigger capable of switching the working points, provided by the invention, is used for solving the problem that a Schmitt circuit in the prior art is difficult to perfectly compatible with two working points, so that the circuit can be compatible with the two working points, and excellent anti-noise interference capability can be obtained at both the two working points.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
the invention provides a high-performance Schmitt trigger capable of switching working points, which comprises a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, a third NMOS, an input end, an output end and a power supply; the source electrode of the first PMOS is connected with a power supply; the source electrode of the second PMOS is respectively connected with the drain electrode of the first PMOS and the source electrode of the third PMOS; the drain electrode of the second PMOS is connected with the drain electrode of the first NMOS; the source electrode of the first NMOS is respectively connected with the drain electrode of the second NMOS and the source electrode of the third NMOS; the source electrode of the second NMOS is grounded; the input end of the first NMOS is connected with the grid of the first PMOS, the grid of the second PMOS, the grid of the first NMOS and the grid of the second NMOS; the output end of the first PMOS is connected with the drain electrode of the first NMOS, the drain electrode of the second NMOS, the grid electrode of the third PMOS and the grid electrode of the third NMOS; the device comprises a positive threshold adjusting module, a negative threshold adjusting module and a gating information number module; the forward threshold adjusting module comprises a fourth NMOS and a fifth NMOS; the drain terminal of the third NMOS is connected with the source electrode of the fourth NMOS and the source electrode of the fifth NMOS; the drain electrode of the fourth NMOS and the drain electrode of the fifth NMOS are respectively connected with the power supply; the grid electrode of the fourth NMOS is connected with the output end; the negative threshold adjusting module comprises a fourth PMOS and a sixth NMOS; the drain electrode of the third PMOS is connected with the source electrode of the fourth PMOS and the source electrode of the sixth NMOS; the drain electrode of the fourth PMOS and the drain electrode of the sixth NMOS are respectively grounded; the grid electrode of the fourth PMOS is connected with the output end; the grid electrode of the fifth NMOS and the grid electrode of the sixth NMOS are respectively connected with the gating signal module; the gating signal module can switch the conduction of a fifth NMOS and a sixth NMOS, and only one of the fifth NMOS and the sixth NMOS is conducted at the same time.
The high-performance Schmitt trigger capable of switching the working point preferably comprises an auxiliary adjusting module; the auxiliary regulation module comprises a seventh NMOS; the drain electrode of the seventh NMOS is connected with the drain electrode of the second NMOS; the source electrode of the seventh NMOS is connected with the source electrode of the second NMOS; the grid electrode of the seventh NMOS is connected with the gating signal module; the gating signal module may turn on a seventh NMOS, and the sixth NMOS and the seventh NMOS are turned on at the same time.
The high-performance Schmitt trigger capable of switching the working point preferably further comprises a zeroth NMOS; the source electrode of the first NMOS is connected with the drain electrode of the second NMOS through the zeroth NMOS; the drain electrode of the second NMOS is connected with the source electrode of the zeroth NMOS; and the source electrode of the first NMOS is connected with the drain electrode of the zeroth NMOS.
The high-performance Schmitt trigger capable of switching the working point provided by the invention preferably further comprises a zeroth PMOS; the source electrode of the second PMOS is connected with the drain electrode of the first PMOS through the zeroth PMOS; the source electrode of the zeroth PMOS is connected with the drain electrode of the first PMOS; and the drain electrode of the zeroth PMOS is connected with the source electrode of the second PMOS.
The high-performance schmitt trigger capable of switching the working point is preferably characterized in that the gating signal module comprises a gating signal end, a fifth PMOS and an eighth NMOS; the grid electrode of the sixth NMOS and the grid electrode of the seventh NMOS are respectively connected with the gating signal end; the source end of the fifth PMOS is connected with the power supply; the drain end of the fifth PMOS is respectively connected with the grid electrode of the fifth NMOS and the drain electrode of the eighth NMOS; the source of the eighth NMOS is grounded; and the grid electrode of the fifth PMOS and the grid electrode of the eighth NMOS are respectively connected with the gating signal end.
According to the high-performance Schmitt trigger capable of switching the working point, preferably, the sixth NMOS is disconnected and the fifth NMOS is connected through the gating signal module, and the high-voltage working point is entered; and the fifth NMOS is disconnected and the sixth NMOS is connected through the gating signal module, and the low-voltage working point is entered.
Preferably, the step of turning off the sixth NMOS, turning on the fifth NMOS, and turning into the high-voltage operating point by the gating signal module is to turn off the sixth NMOS, turn off the seventh NMOS, turn on the fifth NMOS, and turn into the high-voltage operating point by the gating signal module; specifically, the gating signal module turns off the fifth NMOS, turns on the sixth NMOS, turns on the seventh NMOS, and enters the low-voltage operating point.
The invention has the following advantages:
the invention provides a high-performance Schmitt trigger capable of switching working points, which comprises a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, a third NMOS, an input end, an output end and a power supply; the source electrode of the first PMOS is connected with a power supply; the source electrode of the second PMOS is respectively connected with the drain electrode of the first PMOS and the source electrode of the third PMOS; the drain electrode of the second PMOS is connected with the drain electrode of the first NMOS; the source electrode of the first NMOS is respectively connected with the drain electrode of the second NMOS and the source electrode of the third NMOS; the source electrode of the second NMOS is grounded; the input end of the first NMOS is connected with the grid of the first PMOS, the grid of the second PMOS, the grid of the first NMOS and the grid of the second NMOS; the output end of the first PMOS is connected with the drain electrode of the first NMOS, the drain electrode of the second NMOS, the grid electrode of the third PMOS and the grid electrode of the third NMOS; the device comprises a positive threshold adjusting module, a negative threshold adjusting module and a gating information number module; the forward threshold adjusting module comprises a fourth NMOS and a fifth NMOS; the drain terminal of the third NMOS is connected with the source electrode of the fourth NMOS and the source electrode of the fifth NMOS; the drain electrode of the fourth NMOS and the drain electrode of the fifth NMOS are respectively connected with the power supply; the grid electrode of the fourth NMOS is connected with the output end; the negative threshold adjusting module comprises a fourth PMOS and a sixth NMOS; the drain electrode of the third PMOS is connected with the source electrode of the fourth PMOS and the source electrode of the sixth NMOS; the drain electrode of the fourth PMOS and the drain electrode of the sixth NMOS are respectively grounded; the grid electrode of the fourth PMOS is connected with the output end; the grid electrode of the fifth NMOS and the grid electrode of the sixth NMOS are respectively connected with the gating signal module; the gating signal module can switch the conduction of a fifth NMOS and a sixth NMOS, and only one of the fifth NMOS and the sixth NMOS is conducted at the same time. According to the invention, the switching between the fifth NMOS and the sixth NMOS can be completed through the gating signal module, so that the multi-signal compatibility of the circuit can be ensured, and the good anti-noise interference capability at each working point can be ensured.
Drawings
The invention and its features, aspects and advantages will become more apparent from reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Like reference symbols in the various drawings indicate like elements. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.
FIG. 1 is a circuit schematic of a Schmitt trigger in the prior art;
fig. 2 is a schematic circuit diagram of a high-performance schmitt trigger capable of switching an operating point according to embodiment 1 of the present invention;
FIG. 3 is a schematic circuit diagram of another high-performance Schmitt trigger capable of switching operating points according to embodiment 1 of the present invention;
FIG. 4 is a schematic circuit diagram of another high-performance Schmitt trigger capable of switching operating points according to embodiment 1 of the present invention;
fig. 5 is a schematic diagram of a characteristic curve of a high-performance schmitt trigger with switchable operating points at a high-voltage operating point according to embodiment 1 of the present invention;
fig. 6 is a schematic diagram of a characteristic curve of a high-performance schmitt trigger with switchable operating points at a low-voltage operating point according to embodiment 1 of the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application.
As shown in fig. 2, a high-performance schmitt trigger capable of switching operating points according to embodiment 1 of the present invention includes a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, a third NMOS, an input terminal, an output terminal, and a power supply; the source electrode of the first PMOS is connected with a power supply; the source electrode of the second PMOS is respectively connected with the drain electrode of the first PMOS and the source electrode of the third PMOS; the drain electrode of the second PMOS is connected with the drain electrode of the first NMOS; the source electrode of the first NMOS is respectively connected with the drain electrode of the second NMOS and the source electrode of the third NMOS; the source electrode of the second NMOS is grounded; the input end is connected with the grid of the first PMOS, the grid of the second PMOS, the grid of the first NMOS and the grid of the second NMOS; the output end of the first PMOS is connected with the drain electrode of the first NMOS, the drain electrode of the second NMOS, the grid electrode of the third PMOS and the grid electrode of the third NMOS; the device comprises a positive threshold adjusting module, a negative threshold adjusting module and a gating information number module; the positive threshold adjusting module comprises a fourth NMOS and a fifth NMOS; the drain terminal of the third NMOS is connected with the source electrode of the fourth NMOS and the source electrode of the fifth NMOS; the drain electrode of the fourth NMOS and the drain electrode of the fifth NMOS are respectively connected with a power supply; the grid electrode of the fourth NMOS is connected with the output end; the negative threshold adjusting module comprises a fourth PMOS and a sixth NMOS; the drain electrode of the third PMOS is connected with the source electrode of the fourth PMOS and the source electrode of the sixth NMOS; the drain electrode of the fourth PMOS and the drain electrode of the sixth NMOS are grounded respectively; the grid electrode of the fourth PMOS is connected with the output end; the grid electrode of the fifth NMOS and the grid electrode of the sixth NMOS are respectively connected with the gating signal module; the gating signal module can switch the conduction of the fifth NMOS and the sixth NMOS, and only one of the fifth NMOS and the sixth NMOS is conducted at the same time.
IN this embodiment, the high level of the input signal at the input terminal IN of the high voltage operating point is V equal to the level of the power supply VDD (e.g. 5V logic signal), and the low level of the input signal is equal to the level of the power supply ground VSS. And the sixth NMOS is disconnected and the fifth NMOS is connected through the gating signal module, and the high-voltage working point is entered. After entering a high-voltage working point, the positive threshold voltage and the negative threshold voltage can be adjusted to obtain good anti-noise interference capability. Positive threshold voltage adjustment: the adjustment is mainly performed by adjusting the parameter of the third NMOS, and the auxiliary adjustment can be performed by the fourth NMOS, the fifth NMOS and the second NMOS. Negative threshold voltage adjustment: the adjustment is mainly performed by adjusting the parameters of the fourth PMOS, and the auxiliary adjustment can be performed by the third PMOS and the second NMOS. By the adjusting method, the positive threshold voltage VTH1+ and the negative threshold voltage VTH 1-can be kept symmetrically distributed about VDD/2 (as shown in FIG. 5), and good noise interference resistance of the high-voltage operating point can be obtained.
IN this embodiment, the input signal level at the input terminal IN of the low-voltage operating point is V '(e.g., 3.3V logic signal), where V' < power VDD, and the input signal low level is equal to the power ground VSS level. And the fifth NMOS is disconnected and the sixth NMOS is connected through the gating signal module, and the low-voltage working point is entered. After entering a low-voltage working point, the positive threshold voltage and the negative threshold voltage can be adjusted to obtain good noise interference resistance. Positive threshold voltage adjustment: the adjustment is mainly performed by adjusting the parameters of the fourth NMOS, and the auxiliary adjustment is performed by the third NMOS. Negative threshold voltage adjustment: the adjustment is mainly performed by adjusting the parameters of the third PMOS. The positive threshold voltage VTH2+ and the negative threshold voltage VTH 2-can be kept symmetrically distributed about V'/2 (as shown in FIG. 6) by the above-mentioned adjusting method, so that good noise immunity of the low-voltage operating point can be obtained.
Therefore, through the circuit structure, the switching of the fifth NMOS and the sixth NMOS can be switched through the gating signal module to complete the switching between the two working points, so that the multi-signal compatibility of the circuit can be ensured, and the good anti-noise interference capability of each working point can be ensured.
As shown in fig. 3, the present embodiment includes an auxiliary adjusting module; the auxiliary regulation module comprises a seventh NMOS; the drain electrode of the seventh NMOS is connected with the drain electrode of the second NMOS; the source electrode of the seventh NMOS is connected with the source electrode of the second NMOS; the grid electrode of the seventh NMOS is connected with the gating signal module; the gating signal module can enable the seventh NMOS to be conducted, and the sixth NMOS and the seventh NMOS are conducted simultaneously. When the high-performance schmitt trigger capable of switching the operating point provided by this embodiment enters the low-voltage operating point, the seventh NMOS is turned on, and when the negative threshold voltage is adjusted, the parameter of the seventh NMOS may be adjusted to assist in adjustment.
As shown in fig. 4, the present embodiment further includes a zeroth NMOS and a zeroth PMOS; the source electrode of the first NMOS is connected with the drain electrode of the second NMOS through a zeroth NMOS; the drain electrode of the second NMOS is connected with the source electrode of the zeroth NMOS; the source of the first NMOS is connected with the drain of the zeroth NMOS. The source electrode of the second PMOS is connected with the drain electrode of the first PMOS through a zeroth PMOS; the source electrode of the zeroth PMOS is connected with the drain electrode of the first PMOS; and the drain electrode of the zeroth PMOS is connected with the source electrode of the second PMOS. By adding the zeroth PMOS and the zeroth NMOS, the positive and negative thresholds of two working points can be in a reasonable range, and the circuit parameter adjustment is easier to compromise to an expected state.
In this embodiment, the strobe signal module includes a strobe signal terminal, a fifth PMOS and an eighth NMOS; the grid electrode of the sixth NMOS and the grid electrode of the seventh NMOS are respectively connected with the gating signal end; the source end of the fifth PMOS is connected with the power supply; the drain end of the fifth PMOS is respectively connected with the grid electrode of the fifth NMOS and the drain electrode of the eighth NMOS; the source electrode of the eighth NMOS is grounded; and the grid of the fifth PMOS and the grid of the eighth NMOS are respectively connected with the gating signal end. By enabling the gating signal end S to be at a low level, the sixth NMOS is disconnected from the seventh NMOS, and the fifth NMOS is connected, the high-performance schmitt trigger provided by the embodiment enters a high-voltage working point; by switching the gating signal end S to be at a high level, the sixth NMOS is turned on with the seventh NMOS, and the fifth NMOS is turned off, the high-performance schmitt trigger provided by this embodiment enters a low-voltage operating point.
The above description is only for the preferred embodiment of the present invention and is not intended to limit the scope of the present invention, and all equivalent structural changes made by using the contents of the present specification and the drawings, or any other related technical fields, are included in the scope of the present invention.
Claims (7)
1. A high-performance Schmitt trigger capable of switching working points comprises a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, a third NMOS, an input end, an output end and a power supply; the source electrode of the first PMOS is connected with a power supply; the source electrode of the second PMOS is respectively connected with the drain electrode of the first PMOS and the source electrode of the third PMOS; the drain electrode of the second PMOS is connected with the drain electrode of the first NMOS; the source electrode of the first NMOS is respectively connected with the drain electrode of the second NMOS and the source electrode of the third NMOS; the source electrode of the second NMOS is grounded; the input end of the first NMOS is connected with the grid of the first PMOS, the grid of the second PMOS, the grid of the first NMOS and the grid of the second NMOS; the output end of the first PMOS is connected with the drain electrode of the first NMOS, the drain electrode of the second NMOS, the grid electrode of the third PMOS and the grid electrode of the third NMOS; the device is characterized by comprising a positive threshold adjusting module, a negative threshold adjusting module and a gating information number module; the forward threshold adjusting module comprises a fourth NMOS and a fifth NMOS; the drain terminal of the third NMOS is connected with the source electrode of the fourth NMOS and the source electrode of the fifth NMOS; the drain electrode of the fourth NMOS and the drain electrode of the fifth NMOS are respectively connected with the power supply; the grid electrode of the fourth NMOS is connected with the output end; the negative threshold adjusting module comprises a fourth PMOS and a sixth NMOS; the drain electrode of the third PMOS is connected with the source electrode of the fourth PMOS and the source electrode of the sixth NMOS; the drain electrode of the fourth PMOS and the drain electrode of the sixth NMOS are respectively grounded; the grid electrode of the fourth PMOS is connected with the output end; the grid electrode of the fifth NMOS and the grid electrode of the sixth NMOS are respectively connected with the gating signal module; the gating signal module can switch the conduction of a fifth NMOS and a sixth NMOS, and only one of the fifth NMOS and the sixth NMOS is conducted at the same time.
2. The switchable operating point high performance schmitt trigger of claim 1, comprising an auxiliary regulation module; the auxiliary regulation module comprises a seventh NMOS; the drain electrode of the seventh NMOS is connected with the drain electrode of the second NMOS; the source electrode of the seventh NMOS is connected with the source electrode of the second NMOS; the grid electrode of the seventh NMOS is connected with the gating signal module; the gating signal module may turn on a seventh NMOS, and the sixth NMOS and the seventh NMOS are turned on at the same time.
3. The switchable operating point high performance schmitt trigger of claim 1, further comprising a zeroth NMOS; the source electrode of the first NMOS is connected with the drain electrode of the second NMOS through the zeroth NMOS; the drain electrode of the second NMOS is connected with the source electrode of the zeroth NMOS; and the source electrode of the first NMOS is connected with the drain electrode of the zeroth NMOS.
4. The switchable operating point high performance schmitt trigger of claim 1, further comprising a zeroth PMOS; the source electrode of the second PMOS is connected with the drain electrode of the first PMOS through the zeroth PMOS; the source electrode of the zeroth PMOS is connected with the drain electrode of the first PMOS; and the drain electrode of the zeroth PMOS is connected with the source electrode of the second PMOS.
5. The high-performance Schmitt trigger capable of switching the operating point according to any one of claims 1-4, wherein the gating signal module comprises a gating signal terminal, a fifth PMOS and an eighth NMOS; the grid electrode of the sixth NMOS and the grid electrode of the seventh NMOS are respectively connected with the gating signal end; the source end of the fifth PMOS is connected with the power supply; the drain end of the fifth PMOS is respectively connected with the grid electrode of the fifth NMOS and the drain electrode of the eighth NMOS; the source of the eighth NMOS is grounded; and the grid electrode of the fifth PMOS and the grid electrode of the eighth NMOS are respectively connected with the gating signal end.
6. The method for switching the working point of the Schmitt trigger with the switchable working point and the high performance is characterized in that a gating signal module is used for disconnecting a sixth NMOS and connecting a fifth NMOS to enter a high-voltage working point; and the fifth NMOS is disconnected and the sixth NMOS is connected through the gating signal module, and the low-voltage working point is entered.
7. The method of switching an operating point according to claim 6, wherein the step of turning off the sixth NMOS, turning on the fifth NMOS, and entering the high voltage operating point by the gate signal module is to turn off the sixth NMOS, turn off the seventh NMOS, turn on the fifth NMOS, and enter the high voltage operating point by the gate signal module; specifically, the gating signal module turns off the fifth NMOS, turns on the sixth NMOS, turns on the seventh NMOS, and enters the low-voltage operating point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011614038.XA CN112821882B (en) | 2020-12-30 | 2020-12-30 | High-performance Schmitt trigger capable of switching working points and working point switching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011614038.XA CN112821882B (en) | 2020-12-30 | 2020-12-30 | High-performance Schmitt trigger capable of switching working points and working point switching method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112821882A true CN112821882A (en) | 2021-05-18 |
| CN112821882B CN112821882B (en) | 2023-09-12 |
Family
ID=75855498
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011614038.XA Active CN112821882B (en) | 2020-12-30 | 2020-12-30 | High-performance Schmitt trigger capable of switching working points and working point switching method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112821882B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020075052A1 (en) * | 2000-08-11 | 2002-06-20 | Stmircoelectronics S.A. | Threshold amplifier |
| EP1564885A2 (en) * | 2004-02-10 | 2005-08-17 | Texas Instruments Incorporated | A hysteresis input circuit |
| CN104202037A (en) * | 2014-08-20 | 2014-12-10 | 合肥工业大学 | Single event radiation effect resistant reinforced latch circuit |
| CN106209026A (en) * | 2014-08-29 | 2016-12-07 | 台湾积体电路制造股份有限公司 | Flip-flop circuit |
| US20180069534A1 (en) * | 2015-04-01 | 2018-03-08 | Japan Science And Technology Agency | Electronic circuit |
| CN112385145A (en) * | 2019-06-04 | 2021-02-19 | 小龙知识产权控股有限责任公司 | Low power flip-flop circuit |
-
2020
- 2020-12-30 CN CN202011614038.XA patent/CN112821882B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020075052A1 (en) * | 2000-08-11 | 2002-06-20 | Stmircoelectronics S.A. | Threshold amplifier |
| EP1564885A2 (en) * | 2004-02-10 | 2005-08-17 | Texas Instruments Incorporated | A hysteresis input circuit |
| CN104202037A (en) * | 2014-08-20 | 2014-12-10 | 合肥工业大学 | Single event radiation effect resistant reinforced latch circuit |
| CN106209026A (en) * | 2014-08-29 | 2016-12-07 | 台湾积体电路制造股份有限公司 | Flip-flop circuit |
| US20180069534A1 (en) * | 2015-04-01 | 2018-03-08 | Japan Science And Technology Agency | Electronic circuit |
| CN112385145A (en) * | 2019-06-04 | 2021-02-19 | 小龙知识产权控股有限责任公司 | Low power flip-flop circuit |
Non-Patent Citations (3)
| Title |
|---|
| ZHE CHEN; ET., AL.;: "A high-speed low voltage CMOS Schmitt Trigger with adjustable hysteresis", 2017 IEEE/ACIS 16TH INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION SCIENCE * |
| 冯勇等: "一种新型CMOS施密特触发器", 计算机测量与控制 * |
| 王思远: "施密特触发器电路优化与在SRAM中应用的研究", 《中国优秀硕士学位论文全文数据库》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112821882B (en) | 2023-09-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7199617B1 (en) | Level shifter | |
| US8154323B2 (en) | Output driver operable over wide range of voltages | |
| EP1239591B1 (en) | Input circuit for an integrated circuit | |
| US10347325B1 (en) | DDR4 memory I/O driver | |
| US20060132179A1 (en) | Low voltage differential signaling drivers including branches with series resistors | |
| US7173472B2 (en) | Input buffer structure with single gate oxide | |
| US7154309B1 (en) | Dual-mode output driver configured for outputting a signal according to either a selected high voltage/low speed mode or a low voltage/high speed mode | |
| US20130222037A1 (en) | Voltage level shifter | |
| JPS63112893A (en) | Semiconductor integrated circuit | |
| US6285209B1 (en) | Interface circuit and input buffer integrated circuit including the same | |
| KR20010049227A (en) | Level adjustment circuit and data output circuit thereof | |
| US7583110B2 (en) | High-speed, low-power input buffer for integrated circuit devices | |
| US20060145735A1 (en) | Output buffer circuit eliminating high voltage insulated transistor and level shift circuit, and an interface circuit using the output buffer circuit | |
| US6819159B1 (en) | Level shifter circuit | |
| US7724069B1 (en) | Analog switch for operation outside power rails with low supply current | |
| JP3657243B2 (en) | Level shifter, semiconductor integrated circuit, and information processing system | |
| US20030132794A1 (en) | Level conversion circuit | |
| JP3950120B2 (en) | Driver circuit and system having driver circuit | |
| US6489815B2 (en) | Low-noise buffer circuit that suppresses current variation | |
| CN112821882B (en) | High-performance Schmitt trigger capable of switching working points and working point switching method | |
| JPH098637A (en) | Semiconductor device | |
| CN113285706B (en) | Voltage level conversion circuit | |
| US7746146B2 (en) | Junction field effect transistor input buffer level shifting circuit | |
| KR20100133610A (en) | Voltage level shifter | |
| US11621705B2 (en) | Semiconductor integrated circuit device and level shifter circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |