JPH01248820A - Flip flop circuit - Google Patents

Abstract

PURPOSE:To fasten an action speed by connecting a switch to the output terminal side of first and second inverters for holding data, and separating first and second nodes from the second and first inverter output terminals at the time of fetching the input data and the inverting input data of first and second transfer gates. CONSTITUTION:The title circuit provides a first switch 61 connected between the output terminal of a first inverter 51 and the input terminal of a second inverter 52, and on-off-operated by a clock signal and the inverting clock signal of the inverse phase and a second switch 62 connected between the output terminal of the second inverter 52 and the input terminal of the first inverter 51 and on-off-operated by an inverting clock signal by the inverting clock signal. Switches 61 and 62 go to an off condition at the time of fetching the input data and the inverting input data of first and second transfer gates 41 and 42, separate first and second nodes N41 and N42 and the output terminal of inverters 51 and 52, reduce the charging discharging quantity of the nodes N41 and N42, shorten the data transfer time in the transfer gates 41 and 42 and a high speed action is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a flip-flop circuit (hereinafter referred to as an FF circuit) in a semiconductor digital integrated circuit or the like.

(Prior Art) Conventionally, this type of FF circuit has been described in the 1986 IEICE Semiconductor/Materials Division National Conference 200, Review of rGaAsDCFL Flip-Flop Circuits JP by Shikata, Kuninaka, and Akiyama.

There was one described in 1-201. The configuration will be explained below using figures.

FIG. 2 is a circuit diagram showing a configuration example of a conventional master-slave type FF circuit.

This FF circuit is composed of a master side circuit and a slave side circuit. The master side circuit uses clock signal CK
Transfer gate 1 turns on and off to input input data D, and is turned on by clock signal CK.

and a transfer gate 2 which is turned off and inputs inverted data, and the outputs of the transfer gates 1 and 2 (
rule node N1. Connected to N2 are two inverters 11.12 which are cross-connected to temporarily hold data, and a gate driving inverter 13.14 at the next stage. Output nodes Nil, N1 of inverters 13 and 14
Similarly to the master side circuit, the slave side circuit connected to 2 is equipped with a transfer gate (21, 22) which is turned on and off by an inverted clock signal πK, and has a data holding circuit at its output node N21, 22. The two inverters 31 and 32 are connected to the output inverters 33 and 34, and the output Q and the inverted output are sent out from the inverters 33 and 34.

FIG. 3 is a time chart showing the operation of FIG. 2,
The operation of the FF circuit shown in FIG. 2 will be explained with reference to this diagram.

First, as an initial state, a clock signal CK at a low level (hereinafter referred to as "Lll"), an inverted clock signal π at a high level (hereinafter referred to as "H"), input data D of "Hll", and "°L' The inverted input data 100° is applied to the nodes Nl, N2.NIL.

N12. N21. N22 is "Lpa" respectively.

'Hll, lHIT, 1L,H
'', 'H'°.

At time T1, when the clock signal CK becomes "H" and the inverted clock signal 7 becomes "LIT", transfer gates 1.
2 is turned on, and after a delay of time tl, at time T2, the node N1 becomes "H" due to the input data D, and the node N2 becomes "Loo" due to the inverted input data 100. Here, the node N1 becomes "H1".
In order to reach l, it is necessary to charge the input capacitance of inverters 11 and 13 with the current flowing through transfer gate 1, and it is also necessary to supply the sink current of inverter 12, which causes a time delay in tl. .

Furthermore, in order for the node N2 to become "Ltl", the current flowing through the transfer gate 2 causes the inverter 12.
It is necessary to discharge the input capacitance of inverter 1.
Since it is necessary to sink an output current of 1, a time delay of tl occurs.

At time T2, when the node N1 becomes "H'°, the inverter 13 causes the node Nll to
It becomes "L" at time T3 after a delay time t2 of 3 seconds. Since the node N2 is "L", the node N12 becomes "H'°" by the inverter 14. The inverted clock signal πK becomes "L'".
Therefore, transfer gates 21.22 are turned off, and nodes N21.22 are turned off. The level of N22 is determined by the inverter 31.
32, the state before the inverted clock signal GK becomes "L'° is maintained. In other words, the node N here.

21 is in the II HII state, and the node N22 is in the L power state.

At time T4, when the clock signal CK becomes "Lll" and the inverted clock signal CK becomes "Hll", the transfer gate 1.2 is turned off, so that the inverter 11.12 sets the levels of nodes Nl and N2 to "IHII" and "Hll", respectively.
l “L” is maintained. Inverted clock signal OK is “H”
”, the transfer gates 21 and 23 are turned on, and the level of nodes N21 and N22 becomes the level “L′° of nodes NIL and N12, respectively, at time T5 after time t3.
, "H". At this time, inverters 31, 32
, 33.degree. 34, the output current of the inverter 31.32, and the current flowing through the transfer gate 21.22, a delay of time t3 occurs. Then, the output Q and the inverted output enable become "I HII" at time T6 after the delay time t4 of the inverters 33 and 34, respectively.

It becomes "L'".

As described above, in this FF circuit, the clock signal CK is “I”.
(The flip-flop operates to output the input data D of "H11" and the inverted input data "H11" of "H11" in the form of an output Q and an inverted output possible when the clock signal CK becomes "°L" during the output. do.

(Problems to be Solved by the Invention) However, the FF circuit having the above configuration has the following problems.

The operating speed of the conventional FF circuit is as follows: transfer gate 1,
2 is in the on state and then the node Nl.

Time t1 until the level of N2 is determined and inverter 1
3 and the delay time t2. In other words, in order to increase the operating speed, it is important to shorten the delay times tl and t2. Further, after transfer gates 21.22 are turned on, node N21. The same applies to the time t3 until the level of N22 is determined and the delay time t4 of the inverters 33 and 32. Incidentally, the delay times t1 and t3 are determined not only by the input capacity of the inverter but also by the output current. Since the output current of the inverters 11, 12, 31 and 32 is larger than the current for charging the input capacitor, the delay times tl and t3 become longer, making it difficult to increase the operating speed. .

The present invention solves the problem of the prior art, which is that it is difficult to increase the operating speed due to the increase in delay time when inverting the output of the inverter.
This provides an F circuit.

(Means for Solving the Problems) In order to solve the above problems, the present invention turns on by a clock signal. a first transfer gate that operates off and inputs input data; a second transfer gate that operates on and off according to the clock signal and inputs inverted input data having a phase opposite to that of the input data; 1st
a first inverter having an output terminal connected to a first node on the output side of the transfer gate and a second node on the output side of the second transfer gate, and an input terminal having an input terminal connected to the input side of the first inverter; a second inverter connected to each terminal, a third inverter for output connected to the first node, and a fourth inverter for output connected to the second node. In the FF circuit, the output terminal of the first inverter and the second
a first switch connected between an input terminal of the inverter and turned on and off by an inverted clock signal having a phase opposite to the clock signal; an output terminal of the second inverter and an input terminal of the first inverter; and is turned on by the inverted clock signal.

A second switch that is turned off is provided.

(Function) According to the present invention, since the FF circuit is configured as described above, the first. The second switch is turned off when the input data and inverted input data of the first and second transfer gates are taken in, and the second switch is turned off when the input data and the inverted input data of the first and second transfer gates are taken in. 1st
The output terminal of the first inverter is disconnected from the output terminal of the first inverter. The amount of charging and discharging of the second node is reduced, and the amount of charging and discharging of the second node is reduced. It works to shorten the data transfer time at the second transfer gate. This enables high-speed operation. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a circuit diagram of a master-slave type FF circuit showing an embodiment of the present invention.

This FF circuit is composed of a master side circuit and a slave side circuit as in the conventional case. The master side circuit is turned on by the clock signal CK. Field effect transistor (hereinafter referred to as FET) that turns off and inputs input data D
The first transfer gate 41 is turned on by the clock signal CK. The second transfer gate 42 is comprised of a FET that is turned off and inputs inverted data. The first node N41 of the output A law of the first transfer gate 41 has the first . Third inverter 51.
53 are connected to the second node N42 on the output side of the second transfer gate 41. The respective input terminals of the fourth inverters 52 and 54 are connected. The output side of the first inverter 51 is connected to the input terminal of the second inverter 52 via a first switch 61 consisting of a FET that is turned on and off by an inverted clock signal πK, and the output terminal of the inverter 52 is connected to the input terminal of the second inverter 52. ,
Turns on by inverted clock signal CK. It is connected to the input terminal of the first inverter 51 via a second switch 62 that is turned off. The first one connected by a sash. Second inverter 51.52 and first and second switches 61.62
has the function of temporarily holding data. Third. The fourth inverter 53,54 is for driving the gate of the next stage, and the slave side circuit is connected to its output side node N5L N52.

The slave side circuit, like the master side circuit, consists of a first FET that is turned on and off depending on the inverted clock signal. comprising a second transfer gate 71.72;
The first one on the output side. Second node N61. N62 has
The first one is connected by a sash to hold data. The second inverter 81°82 and the first inverter 81°82. Second switch 91.
92, and a third one for output. A fourth inverter 83.84 is connected, and the inverter 83.84 outputs an output Q and an inverted output. 1st, 2nd
The switches 91 and 92 are turned on by the clock signal CK.

It is composed of an FET that operates in the off state.

FIG. 4 is a time chart showing the operation of FIG. 1,
The operation of the FF circuit shown in FIG. 1 will be explained with reference to this diagram.

The basic operation of the FF circuit in Figure 1 is similar to that of the conventional FF circuit in Figure 2.
Same as the circuit, but switch 61゜62.91.92
The difference is that the time t11°T13 in FIG. 4, which corresponds to the times tl and t3 in FIG. 3, is shorter than that of the conventional circuit, and the operating speed of the FF circuit is improved.

The operation will be explained below.

First, as an initial state, “Lll clock signal CK,
Inverted clock signal CK of “Ho”, input data D of “H”, and inverted input data 100 of II L jl are applied, and nodes N41 and N42 are connected to Lll and I, respectively.
Suppose that it is IHII. At this time, switches 61, 62 and transfer gates 71, 72 are turned on, transfer gates 41, 42 and switches 91, 92 are turned off, and the output terminal of inverter 51 is Since the output terminal of the inverter 52 is connected to the node N41 via the switch 62, II L T1 of the node N41 and Hll of the node N42 are maintained in this state. N51.N52
．． N61. N62, output Q, and inverted output enable are "H", "Lll", and "H'', respectively.

“L”, “11.II”, “r”Hll.

At time T1, when the clock signal CK becomes 11 H11 and the inverted clock signal ■ becomes "Lll," the transfer gates 41, 42 and switches 91, 92 are turned on, and the switches 61, 62 and transfer gate 7172 are turned off. input data D is transmitted to the node N41 via the transfer gate 41, and the “L”
The inverted input data of ll is transmitted to node N42 via transfer gate 42. For example, in the case of transmission to node N41, the time required for transmission at this time is determined by the current flowing through transfer gate 41, which causes inverter 51.
It is determined by the time required to charge the input capacitance of the inverter 53 and to draw in the output current of the inverter 52 via the switch 62.

By the way, in this circuit configuration, the switch 62 is in an off state at this time. In other words, transfer gate 4
All of the current flowing through 1 is used only to charge the input capacitance of the inverter 51, 53, so that charging is performed quickly and the delay time tll is shorter than the conventional delay time t1.
At a later time T2, node N41 becomes it Hn. Similarly, when measuring node N42, since the switch 61 is in the off state, the current flowing through the transfer gate 42 is used only to increase the input capacitance of the inverter 52,54, so the level of the node N42 quickly changes to "Lll". becomes.

Note that at time T1, transfer gates 71 and 72
is off and switches 91 and 92 are on, so at time T1
Previous node N61. "Hp,"t,91 of N62 is held by an inverter 81.82 and a switch 91.92. That is, II H91 of node N61 is connected to inverter 81.
The output of the inverter 82 is set to "LIT", that is, the node N61 is set to "°L'°", and the output of the node N61 is set to "L'°".
This state becomes a stable state because the output of the node N6L is set to 11 HJl, that is, the node N6L is set to H''.

At time T2, node N41 says “Hoo, node N4
2 becomes "Lll", the node N51 becomes "Loo,
Node N52 becomes high.

At time T4, when the clock signal CK becomes "LIT" and the inverted clock signal ff becomes "HPA", the transfer gate 41.42 and the switch 91.92 are turned off, and the switch 6 is turned off.
1.62 and transfer gates 71 and 72 are turned on. By turning off the transfer gates 41 and 42 and turning on the switches 61 and 62, the "H" state of the node N41 and the "L" state of the node N42 are stably maintained in this state. Further, by turning on transfer gates 71, 72 and turning off switches 91 and 92, node N61. N62 are the respective nodes N51. N52's 11 L 11, °“H”
trying to be on the same level. At this time, the time t required for nodes N61 and N62 to become "L" and H1l, respectively
13 is determined by the time it takes for the current flowing through transfer gates 71.72 to charge and discharge the input capacitances of inverters 81.83 and 82.84, respectively. switch 91.92
Since the inverter is off, the inverter 81 and 82 are
Since there is no need to sink the output current of node N6, at time T5 after time t43, which is shorter than conventional delay time t3
1゜N62 respectively "1, 11, l"H
”.

Then, time T after delay time t4 of inverters 83 and 84
6, the output Q becomes "IIH" and the inverted output enable becomes "L".

As mentioned above, in this embodiment, the switch 61.62°919
2, transfer gates 41, 42, 71
．． The transfer time t11゜t13 in 72 is the conventional time t
l and t3, and the operating speed of the FF circuit becomes faster.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

(a) F consisting only of the master side circuit shown in Figure 1
The present invention can also be applied to F circuits.

(b) The transfer gates 41, 42, 71° 72 and the switches 61, 62, 91, 92 may be constructed of transistors other than FETs.

(Effects of the Invention) As described above in detail, according to the present invention, the first and second switches are connected to the output terminal sides of the first and second inverters for data retention, so the first and second switches are connected to the output terminal sides of the first and second inverters for data retention. When input data and inverted input data are taken into the second transfer gate, the first and second switches are in the off state, and the first and second switches are in the off state. The second node is the second. disconnected from the first inverter output terminal, thereby causing the first inverter output terminal to be disconnected from the first inverter output terminal. The transfer time in the second transfer gate is shortened, and the operating speed of the FF circuit is increased.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an FF circuit without showing an embodiment of the present invention; Fig. 2 is a circuit diagram of an FF circuit;
3 is a circuit diagram of a conventional FF circuit, FIG. 3 is a time chart of FIG. 2, and FIG. 4 is a time chart of FIG. 1. 41.71...First transfer gate, 4
2.72...Second transfer gate, 51
゜81...First inverter, 52.82...
...Second inverter, 53.83...Third inverter, 54.84...Fourth inverter, 61.91...First switch , 62.
92...Second switch, CK...Clock signal, OK...Inverted clock signal, D.
...Input data, ■...Inverted input data, Q...Output, Mutual...Inverted output.

Claims (1)

[Claims] A first transfer gate that operates on and off according to a clock signal to input input data, and a first transfer gate that operates on and off according to the clock signal and inputs inverted input data having a phase opposite to the input data. a second transfer gate; and a first transfer gate whose input terminal is on the output side of the first transfer gate.
a first inverter whose output terminal is connected to a second node on the output side of the second transfer gate; a second inverter connected to each input terminal of the inverter; a third inverter for output connected to the first node; and a fourth inverter for output connected to the second node. In a flip-flop circuit comprising: a first inverter connected between an output terminal of the first inverter and an input terminal of the second inverter and turned on and off by an inverted clock signal having a phase opposite to the clock signal; a switch, an output terminal of the second inverter and the first inverter;
and a second switch connected between the input terminal of the inverter and turned on and off by the inverted clock signal.