JPS63183643U - - Google Patents
Info
- Publication number
- JPS63183643U JPS63183643U JP7316587U JP7316587U JPS63183643U JP S63183643 U JPS63183643 U JP S63183643U JP 7316587 U JP7316587 U JP 7316587U JP 7316587 U JP7316587 U JP 7316587U JP S63183643 U JPS63183643 U JP S63183643U
- Authority
- JP
- Japan
- Prior art keywords
- shift register
- address code
- signal
- output
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Information Transfer Systems (AREA)
Description
第１図は本考案の実施例を示すブロツク図、第
２図及び第３図は、第１図の実施例の動作を示す
タイミング図である。
１……第１のシフトレジスタ、２……デコーダ
、３……クロツク制御回路、４……第２のシフト
レジスタ、５……ラツチ回路、６……カウンタ、
７……ラツチ制御回路。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are timing diagrams showing the operation of the embodiment of FIG. DESCRIPTION OF SYMBOLS 1...First shift register, 2...Decoder, 3...Clock control circuit, 4...Second shift register, 5...Latch circuit, 6...Counter,
7...Latch control circuit.
Claims (1)
シフトレジスタと、該第２のシフトレジスタをア
ドレス指定するためのアドレスコードをシリアル
に入力する第１のシフトレジスタと、該第１のシ
フトレジスタの出力に基いて所定のアドレスコー
ドであることを検出するデコーダと、前記アドレ
スコードの入力時とデータの入力時に異なる状態
となる制御信号と前記デコーダの出力に基いて前
記アドレスコード及びデータと同期するクロツク
信号を前記第２のシフトレジスタに印加するクロ
ツク制御回路と、前記第２のシフトレジスタの内
容を保持するラツチ回路と、前記クロツク制御回
路からクロツク信号の出力と同時に出力される信
号により動作を開始し前記クロツク信号を計数す
るカウンタと、該カウンタが所定値以上になつた
ことを検出し、且つ、前記制御信号が所定変化し
たときのみ前記ラツチ回路のラツチ信号を発生す
るラツチ制御回路とを備えたデータ受信回路。 a second shift register into which serially applied data is input; a first shift register into which an address code for addressing the second shift register is serially input; and an output of the first shift register. a decoder that detects a predetermined address code based on the address code; a control signal that has different states when the address code is input and when the data is input; and a clock that synchronizes with the address code and data based on the output of the decoder. The operation is started by a clock control circuit that applies a signal to the second shift register, a latch circuit that holds the contents of the second shift register, and a signal that is output from the clock control circuit at the same time as the clock signal is output. and a latch control circuit that detects that the counter has exceeded a predetermined value and generates a latch signal for the latch circuit only when the control signal changes to a predetermined value. data receiving circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987073165U JPH0546105Y2 (en) | 1987-05-15 | 1987-05-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987073165U JPH0546105Y2 (en) | 1987-05-15 | 1987-05-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63183643U true JPS63183643U (en) | 1988-11-25 |
| JPH0546105Y2 JPH0546105Y2 (en) | 1993-12-01 |
Family
ID=30917255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987073165U Expired - Lifetime JPH0546105Y2 (en) | 1987-05-15 | 1987-05-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0546105Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59205644A (en) * | 1983-05-09 | 1984-11-21 | Nec Corp | Input and output control circuit |
| JPS60100248A (en) * | 1983-11-07 | 1985-06-04 | Ricoh Co Ltd | Input/output device |
-
1987
- 1987-05-15 JP JP1987073165U patent/JPH0546105Y2/ja not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59205644A (en) * | 1983-05-09 | 1984-11-21 | Nec Corp | Input and output control circuit |
| JPS60100248A (en) * | 1983-11-07 | 1985-06-04 | Ricoh Co Ltd | Input/output device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0546105Y2 (en) | 1993-12-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS63183643U (en) | ||
| JPS6128070U (en) | digital frequency phase comparator | |
| JPS63185319U (en) | ||
| JPS6257442U (en) | ||
| JPS5851340U (en) | input control circuit | |
| JPS60113572U (en) | Data setting device | |
| JPH0427730B2 (en) | ||
| JPS6010391U (en) | Alarm | |
| JPS6119767U (en) | Rotation speed detection device | |
| JPS60132699U (en) | integrated circuit | |
| JPS5986742U (en) | Programmable timing generation circuit | |
| JPS5874194U (en) | alarm clock | |
| JPS58124804U (en) | process input/output device | |
| JPS5837252U (en) | pulse width modulation circuit | |
| JPS58124895U (en) | Alarm signal holding circuit | |
| JPS5921795U (en) | Pointer display alarm clock | |
| JPS60169947U (en) | Parallel/serial conversion circuit | |
| JPS6347625U (en) | ||
| JPS5947896U (en) | electronic clock | |
| JPH0166697U (en) | ||
| JPS5871843U (en) | BCD signal reading device | |
| JPS60111443U (en) | Remote control device for water heaters, etc. | |
| JPH02111846U (en) | ||
| JPS5836402U (en) | Sequencer | |
| JPS63122832U (en) |